M480 BSP V3.05.006
The Board Support Package for M480 Series
bpwm.c
Go to the documentation of this file.
1/**************************************************************************/
9#include "NuMicro.h"
10
35uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
36{
37 uint32_t u32Src;
38 uint32_t u32PWMClockSrc;
39 uint32_t u32NearestUnitTimeNsec;
40 uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU;
41
42 if(bpwm == BPWM0)
43 {
44 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
45 }
46 else /* (bpwm == BPWM1) */
47 {
48 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
49 }
50
51 if(u32Src == 0U)
52 {
53 /* clock source is from PLL clock */
54 u32PWMClockSrc = CLK_GetPLLClockFreq();
55 }
56 else
57 {
58 /* clock source is from PCLK */
60 if(bpwm == BPWM0)
61 {
62 u32PWMClockSrc = CLK_GetPCLK0Freq();
63 }
64 else /* (bpwm == BPWM1) */
65 {
66 u32PWMClockSrc = CLK_GetPCLK1Freq();
67 }
68 }
69
70 u32PWMClockSrc /= 1000UL;
71 for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++)
72 {
73 uint32_t u32Exit = 0U;
74 u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc;
75 if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
76 {
77 if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
78 {
79 u32Exit = 1U;
80 }
81 else
82 {
83 u32Exit = 0U;
84 }
85 if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))
86 {
87 u32Exit = 1U;
88 }
89 else
90 {
91 u32Exit = 0U;
92 }
93 }
94 else
95 {
96 u32Exit = 1U;
97 }
98 if (u32Exit == 1U)
99 {
100 break;
101 }
102 else {}
103 }
104
105 /* convert to real register value */
106 /* all channels share a prescaler */
107 u16Prescale -= 1U;
108 BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale);
109
110 /* set BPWM to down count type(edge aligned) */
111 (bpwm)->CTL1 = (1UL);
112
113 BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
114
115 return (u32NearestUnitTimeNsec);
116}
117
130uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
131{
132 uint32_t u32Src;
133 uint32_t u32PWMClockSrc;
134 uint32_t i;
135 uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
136
137 if(bpwm == BPWM0)
138 {
139 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
140 }
141 else /* (bpwm == BPWM1) */
142 {
143 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
144 }
145
146 if(u32Src == 0U)
147 {
148 /* clock source is from PLL clock */
149 u32PWMClockSrc = CLK_GetPLLClockFreq();
150 }
151 else
152 {
153 /* clock source is from PCLK */
155 if(bpwm == BPWM0)
156 {
157 u32PWMClockSrc = CLK_GetPCLK0Freq();
158 }
159 else /* (bpwm == BPWM1) */
160 {
161 u32PWMClockSrc = CLK_GetPCLK1Freq();
162 }
163 }
164
165 for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */
166 {
167 i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
168 /* If target value is larger than CNR, need to use a larger prescaler */
169 if(i < (0x10000U))
170 {
171 u32CNR = i;
172 break;
173 }
174 }
175 /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
176 i = u32PWMClockSrc / (u32Prescale * u32CNR);
177
178 /* convert to real register value */
179 /* all channels share a prescaler */
180 u32Prescale -= 1U;
181 BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
182 /* set BPWM to down count type(edge aligned) */
183 (bpwm)->CTL1 = (1UL);
184
185 u32CNR -= 1U;
186 BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
187 if(u32DutyCycle)
188 {
189 BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL);
190 (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U));
191 (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTL0_Pos));
192 (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U));
193 (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos));
194 }
195 else
196 {
197 BPWM_SET_CMR(bpwm, u32ChannelNum, 0U);
198 (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2U));
199 (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTL0_Pos));
200 (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2U));
201 (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTL0_Pos));
202 }
203
204 return(i);
205}
206
217void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
218{
219 (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
220}
221
232void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
233{
234 (bpwm)->PERIOD = 0U;
235}
236
247void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
248{
249 (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
250}
251
269void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
270{
271 if(u32ChannelNum < 4U)
272 {
273 (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U));
274 (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U));
275 }
276 else
277 {
278 (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U));
279 (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U));
280 }
281}
282
292void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
293{
294 if(u32ChannelNum < 4U)
295 {
296 (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U));
297 }
298 else
299 {
300 (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U));
301 }
302}
303
314void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
315{
316 (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
317}
318
329uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
330{
331 return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
332}
333
344void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
345{
346 (bpwm)->CAPINEN |= u32ChannelMask;
347 (bpwm)->CAPCTL |= u32ChannelMask;
348}
349
360void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
361{
362 (bpwm)->CAPINEN &= ~u32ChannelMask;
363 (bpwm)->CAPCTL &= ~u32ChannelMask;
364}
365
376void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
377{
378 (bpwm)->POEN |= u32ChannelMask;
379}
380
391void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
392{
393 (bpwm)->POEN &= ~u32ChannelMask;
394}
395
408void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
409{
410 (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
411}
412
425void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
426{
427 (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
428}
429
442void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
443{
444 (bpwm)->CAPIF = (u32Edge << u32ChannelNum);
445}
446
459uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
460{
461 return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
462 (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
463}
476void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
477{
478 (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
479}
480
490void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
491{
492
493 (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
494}
495
505void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
506{
507 (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
508}
509
521uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
522{
523 return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
524}
525
537void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
538{
539 (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
540}
541
552void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
553{
554 (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
555}
556
567void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
568{
569 (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
570}
571
584uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
585{
586 return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
587}
588
599void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
600{
601 (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
602}
603
614void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
615{
616 (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
617}
618
629void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
630{
631 (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
632}
633
646uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
647{
648 return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
649}
650
663void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
664{
665 (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
666}
667
680void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
681{
682 (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
683}
684
701void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
702{
703 (bpwm)->CLKSRC = (u32ClkSrcSel);
704}
705
718uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
719{
720 return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
721}
722
733void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
734{
735 (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
736}
737
738 /* end of group BPWM_EXPORTED_FUNCTIONS */
740 /* end of group BPWM_Driver */
742 /* end of group Standard_Driver */
744
745/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
NuMicro peripheral access layer header file.
#define BPWM_OUTPUT_LOW
Definition: bpwm.h:54
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
Definition: bpwm.h:87
#define BPWM_OUTPUT_HIGH
Definition: bpwm.h:55
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
Definition: bpwm.h:86
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Enable selected channel to trigger ADC.
Definition: bpwm.c:269
#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR)
This macro set the period of all channels.
Definition: bpwm.h:233
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Clear capture interrupt of selected channel.
Definition: bpwm.c:442
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
Start BPWM module.
Definition: bpwm.c:217
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Clear the time-base counter reached its maximum value flag of selected channel.
Definition: bpwm.c:733
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
Enable capture of selected channel(s)
Definition: bpwm.c:344
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get the time-base counter reached its maximum value flag of selected channel.
Definition: bpwm.c:718
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Clear duty interrupt flag of selected channel.
Definition: bpwm.c:505
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
Disable period interrupt of selected channel.
Definition: bpwm.c:552
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
Stop BPWM module.
Definition: bpwm.c:232
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Enable load mode of selected channel.
Definition: bpwm.c:663
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Disable capture interrupt of selected channel.
Definition: bpwm.c:425
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get capture interrupt of selected channel.
Definition: bpwm.c:459
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
Enable period interrupt of selected channel.
Definition: bpwm.c:537
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode...
Definition: bpwm.c:130
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get zero interrupt of selected channel.
Definition: bpwm.c:646
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get duty interrupt flag of selected channel.
Definition: bpwm.c:521
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Enable capture interrupt of selected channel.
Definition: bpwm.c:408
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
Disable capture of selected channel(s)
Definition: bpwm.c:360
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
Disable duty interrupt of selected channel.
Definition: bpwm.c:490
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Clear selected channel trigger ADC flag.
Definition: bpwm.c:314
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
Disables BPWM output generation of selected channel(s)
Definition: bpwm.c:391
#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR)
This macro set the duty of the selected channel.
Definition: bpwm.h:212
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
Configure BPWM capture and get the nearest unit time.
Definition: bpwm.c:35
#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler)
This macro set the prescaler of all channels.
Definition: bpwm.h:201
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
Enables BPWM output generation of selected channel(s)
Definition: bpwm.c:376
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Clear zero interrupt of selected channel.
Definition: bpwm.c:629
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get period interrupt of selected channel.
Definition: bpwm.c:584
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
Enable duty interrupt of selected channel.
Definition: bpwm.c:476
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Get selected channel trigger ADC flag.
Definition: bpwm.c:329
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Disable load mode of selected channel.
Definition: bpwm.c:680
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
Stop BPWM generation immediately by clear channel enable bit.
Definition: bpwm.c:247
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
Set BPWM clock source.
Definition: bpwm.c:701
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
Clear period interrupt of selected channel.
Definition: bpwm.c:567
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
Disable zero interrupt of selected channel.
Definition: bpwm.c:614
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
Enable zero interrupt of selected channel.
Definition: bpwm.c:599
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
Disable selected channel to trigger ADC.
Definition: bpwm.c:292
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:206
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:166
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1201
#define CLK
Definition: M480.h:368
#define BPWM0
Definition: M480.h:417
#define BPWM_WGCTL0_PRDPCTL0_Pos
Definition: bpwm_reg.h:2571
#define BPWM_INTSTS_CMPDIF0_Msk
Definition: bpwm_reg.h:2794
#define BPWM_STATUS_EADCTRG0_Msk
Definition: bpwm_reg.h:2863
#define BPWM_WGCTL1_CMPDCTL0_Pos
Definition: bpwm_reg.h:2613
#define BPWM_EADCTS1_TRGSEL4_Msk
Definition: bpwm_reg.h:2839
#define BPWM_CAPIF_CAPRIF0_Msk
Definition: bpwm_reg.h:3073
#define BPWM_WGCTL1_CMPUCTL0_Msk
Definition: bpwm_reg.h:2593
#define BPWM_EADCTS1_TRGEN4_Msk
Definition: bpwm_reg.h:2842
#define BPWM_WGCTL0_ZPCTL0_Msk
Definition: bpwm_reg.h:2551
#define BPWM_INTSTS_CMPUIF0_Msk
Definition: bpwm_reg.h:2773
#define BPWM_CNTEN_CNTEN0_Msk
Definition: bpwm_reg.h:2518
#define BPWM_EADCTS0_TRGSEL0_Msk
Definition: bpwm_reg.h:2815
#define BPWM_INTEN_ZIEN0_Msk
Definition: bpwm_reg.h:2719
#define BPWM_INTSTS_PIF0_Msk
Definition: bpwm_reg.h:2770
#define BPWM_EADCTS0_TRGEN0_Msk
Definition: bpwm_reg.h:2818
#define BPWM_INTEN_PIEN0_Msk
Definition: bpwm_reg.h:2722
#define BPWM_WGCTL0_PRDPCTL0_Msk
Definition: bpwm_reg.h:2572
#define BPWM_WGCTL1_CMPDCTL0_Msk
Definition: bpwm_reg.h:2614
#define CLK_CLKSEL2_BPWM1SEL_Msk
Definition: clk_reg.h:2571
#define BPWM_INTSTS_ZIF0_Msk
Definition: bpwm_reg.h:2767
#define BPWM_WGCTL0_ZPCTL0_Pos
Definition: bpwm_reg.h:2550
#define CLK_CLKSEL2_BPWM0SEL_Msk
Definition: clk_reg.h:2568
#define BPWM_CAPIF_CAPFIF0_Msk
Definition: bpwm_reg.h:3094
#define BPWM_STATUS_CNTMAX0_Msk
Definition: bpwm_reg.h:2860
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29