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M480 BSP V3.05.006
The Board Support Package for M480 Series
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Modules | |
EPWM Exported Functions | |
#define EPWM_CAPTURE_INT_FALLING_LATCH |
#define EPWM_CAPTURE_INT_RISING_LATCH |
#define EPWM_CAPTURE_PDMA_FALLING_LATCH |
#define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH |
#define EPWM_CAPTURE_PDMA_RISING_LATCH |
#define EPWM_CENTER_ALIGNED |
#define EPWM_CLKSRC_EPWM_CLK |
#define EPWM_CLKSRC_TIMER0 |
#define EPWM_CLKSRC_TIMER1 |
#define EPWM_CLKSRC_TIMER2 |
#define EPWM_CLKSRC_TIMER3 |
#define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP |
#define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP |
#define EPWM_EDGE_ALIGNED |
#define EPWM_FB_EDGE_ACMP0 |
#define EPWM_FB_EDGE_ACMP1 |
#define EPWM_FB_EDGE_ADCRM |
#define EPWM_FB_EDGE_BKP0 |
#define EPWM_FB_EDGE_BKP1 |
#define EPWM_FB_EDGE_SYS_BOD |
#define EPWM_FB_EDGE_SYS_COR |
#define EPWM_FB_EDGE_SYS_CSS |
#define EPWM_FB_EDGE_SYS_RAM |
#define EPWM_FB_LEVEL_ACMP0 |
#define EPWM_FB_LEVEL_ACMP1 |
#define EPWM_FB_LEVEL_ADCRM |
#define EPWM_FB_LEVEL_BKP0 |
#define EPWM_FB_LEVEL_BKP1 |
#define EPWM_FB_LEVEL_SYS_BOD |
#define EPWM_FB_LEVEL_SYS_COR |
#define EPWM_FB_LEVEL_SYS_CSS |
#define EPWM_FB_LEVEL_SYS_RAM |
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_1 |
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_2 |
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_4 |
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_8 |
#define EPWM_IFA_COMPARE_DOWN_COUNT_POINT |
#define EPWM_IFA_COMPARE_UP_COUNT_POINT |
#define EPWM_LEBCTL_SRCEN0 |
#define EPWM_LEBCTL_SRCEN0_2 |
#define EPWM_LEBCTL_SRCEN0_2_4 |
#define EPWM_LEBCTL_SRCEN0_4 |
#define EPWM_LEBCTL_SRCEN2 |
#define EPWM_LEBCTL_SRCEN2_4 |
#define EPWM_LEBCTL_SRCEN4 |
#define EPWM_LEBCTL_TRGTYPE_FALLING |
#define EPWM_LEBCTL_TRGTYPE_RISING |
#define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING |
#define EPWM_NF_CLK_DIV_1 |
#define EPWM_NF_CLK_DIV_128 |
#define EPWM_NF_CLK_DIV_16 |
#define EPWM_NF_CLK_DIV_2 |
#define EPWM_NF_CLK_DIV_32 |
#define EPWM_NF_CLK_DIV_4 |
#define EPWM_NF_CLK_DIV_64 |
#define EPWM_NF_CLK_DIV_8 |
#define EPWM_SSCTL_SSRC_BPWM0 |
#define EPWM_SSCTL_SSRC_BPWM1 |
#define EPWM_SSCTL_SSRC_EPWM0 |
#define EPWM_SSCTL_SSRC_EPWM1 |
#define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR |
#define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO |
#define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC |
#define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN |
#define EPWM_TRG_ADC_CH_0_FREE_CMP_UP |
#define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN |
#define EPWM_TRG_ADC_CH_2_FREE_CMP_UP |
#define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN |
#define EPWM_TRG_ADC_CH_4_FREE_CMP_UP |
#define EPWM_TRG_ADC_EVEN_COMPARE_DOWN |
#define EPWM_TRG_ADC_EVEN_COMPARE_UP |
#define EPWM_TRG_ADC_EVEN_PERIOD |
#define EPWM_TRG_ADC_EVEN_ZERO |
#define EPWM_TRG_ADC_EVEN_ZERO_PERIOD |
#define EPWM_TRG_ADC_ODD_COMPARE_DOWN |
#define EPWM_TRG_ADC_ODD_COMPARE_UP |
#define EPWM_TRG_ADC_ODD_PERIOD |
#define EPWM_TRG_ADC_ODD_ZERO |
#define EPWM_TRG_ADC_ODD_ZERO_PERIOD |
#define EPWM_TRIGGER_DAC_COMPARE_DOWN |
#define EPWM_TRIGGER_DAC_COMPARE_UP |
#define EPWM_TRIGGER_DAC_PERIOD |
#define EPWM_TRIGGER_DAC_ZERO |