188#define __CM4_REV 0x0201UL
189#define __NVIC_PRIO_BITS 4UL
190#define __Vendor_SysTickConfig 0UL
191#define __MPU_PRESENT 1UL
194#define __FPU_PRESENT 1UL
196#define __FPU_PRESENT 1UL
208#if defined ( __CC_ARM )
264#define FLASH_BASE ((uint32_t)0x00000000)
265#define SRAM_BASE ((uint32_t)0x20000000)
266#define PERIPH_BASE ((uint32_t)0x40000000)
267#define AHBPERIPH_BASE PERIPH_BASE
268#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000)
271#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
272#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
273#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
274#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
275#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
276#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
277#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
278#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
279#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
280#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
281#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
282#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
283#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
284#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
285#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
286#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
287#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
288#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
289#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
290#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
291#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
292#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
293#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
294#define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)
295#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
296#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
299#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
300#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
301#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
302#define I2S_BASE (APBPERIPH_BASE + 0x08000UL)
303#define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)
304#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
305#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
306#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
307#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
308#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
309#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
310#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
311#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
312#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
313#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
314#define UART6_BASE (APBPERIPH_BASE + 0x36000UL)
315#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
316#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
317#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
318#define CAN2_BASE (APBPERIPH_BASE + 0x62000UL)
319#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
320#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
321#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
325#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
326#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
327#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
328#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
329#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
330#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
331#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
332#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
333#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
334#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
335#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
336#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
337#define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)
338#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
339#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
340#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
341#define UART7_BASE (APBPERIPH_BASE + 0x37000UL)
342#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
343#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
344#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
345#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
346#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
347#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
348#define CRPT_BASE (0x50080000UL)
349#define SPIM_BASE (0x40007000UL)
351#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
352#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
353#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
354#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
355#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
356#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
357#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
367#define SYS ((SYS_T *) SYS_BASE)
368#define CLK ((CLK_T *) CLK_BASE)
369#define NMI ((NMI_T *) NMI_BASE)
370#define PA ((GPIO_T *) GPIOA_BASE)
371#define PB ((GPIO_T *) GPIOB_BASE)
372#define PC ((GPIO_T *) GPIOC_BASE)
373#define PD ((GPIO_T *) GPIOD_BASE)
374#define PE ((GPIO_T *) GPIOE_BASE)
375#define PF ((GPIO_T *) GPIOF_BASE)
376#define PG ((GPIO_T *) GPIOG_BASE)
377#define PH ((GPIO_T *) GPIOH_BASE)
378#define GPA ((GPIO_T *) GPIOA_BASE)
379#define GPB ((GPIO_T *) GPIOB_BASE)
380#define GPC ((GPIO_T *) GPIOC_BASE)
381#define GPD ((GPIO_T *) GPIOD_BASE)
382#define GPE ((GPIO_T *) GPIOE_BASE)
383#define GPF ((GPIO_T *) GPIOF_BASE)
384#define GPG ((GPIO_T *) GPIOG_BASE)
385#define GPH ((GPIO_T *) GPIOH_BASE)
386#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
387#define PDMA ((PDMA_T *) PDMA_BASE)
388#define USBH ((USBH_T *) USBH_BASE)
389#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
390#define EMAC ((EMAC_T *) EMAC_BASE)
391#define FMC ((FMC_T *) FMC_BASE)
392#define SDH0 ((SDH_T *) SDH0_BASE)
393#define SDH1 ((SDH_T *) SDH1_BASE)
394#define EBI ((EBI_T *) EBI_BASE)
395#define CRC ((CRC_T *) CRC_BASE)
396#define TAMPER ((TAMPER_T *) TAMPER_BASE)
398#define WDT ((WDT_T *) WDT_BASE)
399#define WWDT ((WWDT_T *) WWDT_BASE)
400#define RTC ((RTC_T *) RTC_BASE)
401#define EADC ((EADC_T *) EADC_BASE)
402#define EADC0 ((EADC_T *) EADC_BASE)
403#define EADC1 ((EADC_T *) EADC1_BASE)
404#define ACMP01 ((ACMP_T *) ACMP01_BASE)
406#define I2S0 ((I2S_T *) I2S_BASE)
407#define USBD ((USBD_T *) USBD_BASE)
408#define OTG ((OTG_T *) OTG_BASE)
409#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
410#define HSOTG ((HSOTG_T *) HSOTG_BASE)
411#define TIMER0 ((TIMER_T *) TIMER0_BASE)
412#define TIMER1 ((TIMER_T *) TIMER1_BASE)
413#define TIMER2 ((TIMER_T *) TIMER2_BASE)
414#define TIMER3 ((TIMER_T *) TIMER3_BASE)
415#define EPWM0 ((EPWM_T *) EPWM0_BASE)
416#define EPWM1 ((EPWM_T *) EPWM1_BASE)
417#define BPWM0 ((BPWM_T *) BPWM0_BASE)
418#define BPWM1 ((BPWM_T *) BPWM1_BASE)
419#define ECAP0 ((ECAP_T *) ECAP0_BASE)
420#define ECAP1 ((ECAP_T *) ECAP1_BASE)
421#define QEI0 ((QEI_T *) QEI0_BASE)
422#define QEI1 ((QEI_T *) QEI1_BASE)
423#define QSPI0 ((QSPI_T *) QSPI0_BASE)
424#define QSPI1 ((QSPI_T *) QSPI1_BASE)
425#define SPI0 ((SPI_T *) SPI0_BASE)
426#define SPI1 ((SPI_T *) SPI1_BASE)
427#define SPI2 ((SPI_T *) SPI2_BASE)
428#define SPI3 ((SPI_T *) SPI3_BASE)
429#define UART0 ((UART_T *) UART0_BASE)
430#define UART1 ((UART_T *) UART1_BASE)
431#define UART2 ((UART_T *) UART2_BASE)
432#define UART3 ((UART_T *) UART3_BASE)
433#define UART4 ((UART_T *) UART4_BASE)
434#define UART5 ((UART_T *) UART5_BASE)
435#define UART6 ((UART_T *) UART6_BASE)
436#define UART7 ((UART_T *) UART7_BASE)
437#define I2C0 ((I2C_T *) I2C0_BASE)
438#define I2C1 ((I2C_T *) I2C1_BASE)
439#define I2C2 ((I2C_T *) I2C2_BASE)
440#define SC0 ((SC_T *) SC0_BASE)
441#define SC1 ((SC_T *) SC1_BASE)
442#define SC2 ((SC_T *) SC2_BASE)
443#define CAN0 ((CAN_T *) CAN0_BASE)
444#define CAN1 ((CAN_T *) CAN1_BASE)
445#define CAN2 ((CAN_T *) CAN2_BASE)
446#define CRPT ((CRPT_T *) CRPT_BASE)
447#define TRNG ((TRNG_T *) TRNG_BASE)
448#define SPIM ((volatile SPIM_T *) SPIM_BASE)
449#define DAC0 ((DAC_T *) DAC0_BASE)
450#define DAC1 ((DAC_T *) DAC1_BASE)
451#define USPI0 ((USPI_T *) USCI0_BASE)
452#define USPI1 ((USPI_T *) USCI1_BASE)
453#define OPA ((OPA_T *) OPA_BASE)
454#define UI2C0 ((UI2C_T *) USCI0_BASE)
455#define UI2C1 ((UI2C_T *) USCI1_BASE)
456#define UUART0 ((UUART_T *) USCI0_BASE)
457#define UUART1 ((UUART_T *) USCI1_BASE)
458#define CCAP ((CCAP_T *) CCAP_BASE)
467typedef volatile uint8_t
vu8;
477#define M8(addr) (*((vu8 *) (addr)))
485#define M16(addr) (*((vu16 *) (addr)))
493#define M32(addr) (*((vu32 *) (addr)))
502#define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
510#define inpw(port) (*((volatile unsigned int *)(port)))
519#define outps(port,value) *((volatile unsigned short *)(port)) = (value)
527#define inps(port) (*((volatile unsigned short *)(port)))
535#define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
542#define inpb(port) (*((volatile unsigned char *)(port)))
551#define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
559#define inp32(port) (*((volatile unsigned int *)(port)))
568#define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
576#define inp16(port) (*((volatile unsigned short *)(port)))
584#define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
591#define inp8(port) (*((volatile unsigned char *)(port)))
615#define BIT0 (0x00000001UL)
616#define BIT1 (0x00000002UL)
617#define BIT2 (0x00000004UL)
618#define BIT3 (0x00000008UL)
619#define BIT4 (0x00000010UL)
620#define BIT5 (0x00000020UL)
621#define BIT6 (0x00000040UL)
622#define BIT7 (0x00000080UL)
623#define BIT8 (0x00000100UL)
624#define BIT9 (0x00000200UL)
625#define BIT10 (0x00000400UL)
626#define BIT11 (0x00000800UL)
627#define BIT12 (0x00001000UL)
628#define BIT13 (0x00002000UL)
629#define BIT14 (0x00004000UL)
630#define BIT15 (0x00008000UL)
631#define BIT16 (0x00010000UL)
632#define BIT17 (0x00020000UL)
633#define BIT18 (0x00040000UL)
634#define BIT19 (0x00080000UL)
635#define BIT20 (0x00100000UL)
636#define BIT21 (0x00200000UL)
637#define BIT22 (0x00400000UL)
638#define BIT23 (0x00800000UL)
639#define BIT24 (0x01000000UL)
640#define BIT25 (0x02000000UL)
641#define BIT26 (0x04000000UL)
642#define BIT27 (0x08000000UL)
643#define BIT28 (0x10000000UL)
644#define BIT29 (0x20000000UL)
645#define BIT30 (0x40000000UL)
646#define BIT31 (0x80000000UL)
649#define BYTE0_Msk (0x000000FFUL)
650#define BYTE1_Msk (0x0000FF00UL)
651#define BYTE2_Msk (0x00FF0000UL)
652#define BYTE3_Msk (0xFF000000UL)
654#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) )
655#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8)
656#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16)
657#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24)
M480 Series ACMP Driver Header File.
ACMP register definition header file.
M480 series PWM driver header file.
BPWM register definition header file.
M480 Series CAN Driver Header File.
CAN register definition header file.
M480 Series CCAP Driver Header File.
CCAP register definition header file.
M480 Series CLK Driver Header File.
CLK register definition header file.
M480 series CRC driver header file.
CRC register definition header file.
Cryptographic Accelerator driver header file.
CRYPTO register definition header file.
M480 series DAC driver header file.
DAC register definition header file.
M480 series EADC driver header file.
EADC register definition header file.
M480 series External Bus Interface(EBI) driver header file.
EBI register definition header file.
EnHanced Input Capture Timer(ECAP) driver header file.
ECAP register definition header file.
M480 EMAC driver header file.
EMAC register definition header file.
M480 series EPWM driver header file.
EPWM register definition header file.
M480 Series Flash Memory Controller Driver Header File.
FMC register definition header file.
M480 series GPIO driver header file.
GPIO register definition header file.
volatile uint64_t vu64
Define 64-bit unsigned volatile data type.
volatile uint16_t vu16
Define 16-bit unsigned volatile data type.
volatile uint32_t vu32
Define 32-bit unsigned volatile data type.
volatile uint8_t vu8
Define 8-bit unsigned volatile data type.
M480 Series HSOTG Driver Header File.
HSOTG register definition header file.
M480 HSUSBD driver header file.
HSUSBD register definition header file.
HSUSBH register definition header file.
M480 series I2C driver header file.
I2C register definition header file.
M480 I2S driver header file.
I2S register definition header file.
M480 series OPA driver header file.
OPA register definition header file.
M480 Series OTG Driver Header File.
OTG register definition header file.
M480 series PDMA driver header file.
PDMA register definition header file.
Quadrature Encoder Interface (QEI) driver header file.
QEI register definition header file.
M480 series QSPI driver header file.
QSPI register definition header file.
M480 series RTC driver header file.
RTC register definition header file.
M480 Smartcard (SC) driver header file.
SC register definition header file.
M480 Smartcard UART mode (SCUART) driver header file.
M480 SDH driver header file.
SDH register definition header file.
M480 series SPI driver header file.
SPI register definition header file.
M480 series SPIM driver header file.
SPIM register definition header file.
M480 Series SYS Driver Header File.
SYS register definition header file.
CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480.
M480 series Timer Controller(Timer) driver header file.
M480 series Timer PWM Controller(Timer PWM) driver header file.
TIMER register definition header file.
TRNG register definition header file.
M480 series UART driver header file.
UART register definition header file.
UI2C register definition header file.
M480 series USB driver header file.
USBD register definition header file.
USBH register definition header file.
M480 series USCI I2C(UI2C) driver header file.
M480 series USCI_SPI driver header file.
M480 series USCI UART (UUART) driver header file.
USPI register definition header file.
UUART register definition header file.
M480 series WDT driver header file.
WDT register definition header file.
M480 series WWDT driver header file.
WWDT register definition header file.