M480 BSP V3.05.006
The Board Support Package for M480 Series
i2c.c
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1/**************************************************************************/
9#include "NuMicro.h"
10
19int32_t g_I2C_i32ErrCode = 0;
38uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
39{
40 uint32_t u32Div;
41 uint32_t u32Pclk;
42
43 if(i2c == I2C1)
44 {
45 u32Pclk = CLK_GetPCLK1Freq();
46 }
47 else
48 {
49 u32Pclk = CLK_GetPCLK0Freq();
50 }
51
52 u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
53 i2c->CLKDIV = u32Div;
54
55 /* Enable I2C */
57
58 return (u32Pclk / ((u32Div + 1U) << 2U));
59}
60
72void I2C_Close(I2C_T *i2c)
73{
74 /* Reset I2C Controller */
75 if((uint32_t)i2c == I2C0_BASE)
76 {
77 SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
78 SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
79 }
80 else if((uint32_t)i2c == I2C1_BASE)
81 {
82 SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
83 SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
84 }
85 else if((uint32_t)i2c == I2C2_BASE)
86 {
87 SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
88 SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
89 }
90
91 /* Disable I2C */
92 i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
93}
94
106{
108}
109
124void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
125{
126 uint32_t u32Reg = 0U;
127
128 if(u8Start)
129 {
130 u32Reg |= I2C_CTL_STA;
131 }
132
133 if(u8Stop)
134 {
135 u32Reg |= I2C_CTL_STO;
136 }
137
138 if(u8Si)
139 {
140 u32Reg |= I2C_CTL_SI;
141 }
142
143 if(u8Ack)
144 {
145 u32Reg |= I2C_CTL_AA;
146 }
147
148 i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg;
149}
150
162{
163 i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;
164}
165
177{
178 i2c->CTL0 |= I2C_CTL0_INTEN_Msk;
179}
180
191{
192 uint32_t u32Divider = i2c->CLKDIV;
193 uint32_t u32Pclk;
194
195 if(i2c == I2C1)
196 {
197 u32Pclk = CLK_GetPCLK1Freq();
198 }
199 else
200 {
201 u32Pclk = CLK_GetPCLK0Freq();
202 }
203
204 return (u32Pclk / ((u32Divider + 1U) << 2U));
205}
206
217uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
218{
219 uint32_t u32Div;
220 uint32_t u32Pclk;
221
222 if(i2c == I2C1)
223 {
224 u32Pclk = CLK_GetPCLK1Freq();
225 }
226 else
227 {
228 u32Pclk = CLK_GetPCLK0Freq();
229 }
230
231 u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
232 i2c->CLKDIV = u32Div;
233
234 return (u32Pclk / ((u32Div + 1U) << 2U));
235}
236
246uint32_t I2C_GetIntFlag(I2C_T *i2c)
247{
248 uint32_t u32Value;
249
250 if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk)
251 {
252 u32Value = 1U;
253 }
254 else
255 {
256 u32Value = 0U;
257 }
258
259 return u32Value;
260}
261
271uint32_t I2C_GetStatus(I2C_T *i2c)
272{
273 return (i2c->STATUS0);
274}
275
285uint8_t I2C_GetData(I2C_T *i2c)
286{
287 return (uint8_t)(i2c->DAT);
288}
289
300void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
301{
302 i2c->DAT = u8Data;
303}
304
319void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
320{
321 switch(u8SlaveNo)
322 {
323 case 1:
324 i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
325 break;
326 case 2:
327 i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
328 break;
329 case 3:
330 i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
331 break;
332 case 0:
333 default:
334 i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
335 break;
336 }
337}
338
351void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
352{
353 switch(u8SlaveNo)
354 {
355 case 1:
356 i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U;
357 break;
358 case 2:
359 i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U;
360 break;
361 case 3:
362 i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U;
363 break;
364 case 0:
365 default:
366 i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U;
367 break;
368 }
369}
370
383void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
384{
385 if(u8LongTimeout)
386 {
388 }
389 else
390 {
391 i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
392 }
393
395}
396
408{
409 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
410}
411
423{
425}
426
438{
439 i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
440}
441
453{
454 return (i2c->BUSSTS);
455}
456
468void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
469{
470 i2c->BUSSTS = u8SMBusIntFlag;
471}
472
484void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
485{
486 i2c->PKTSIZE = u32PktSize;
487}
488
500void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
501{
502 /* Clear BMHEN, BMDEN of BUSCTL Register */
504
505 /* Set SMBus Host/Device Mode, and enable Bus Management*/
506 if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE)
507 {
509 }
510 else
511 {
513 }
514}
515
527{
528
529 i2c->BUSCTL = 0x00U;
530}
531
543void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
544{
545 i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
546
547 if(u8PECTxEn)
548 {
550 }
551 else
552 {
554 }
555}
556
568{
569 return (uint8_t)i2c->PKTCRC;
570}
571
585void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
586{
587 uint32_t u32Div, u32Hclk_kHz;
588
590 u32Hclk_kHz = u32Hclk / 1000U;
591 u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U;
592 if(u32Div > 255U)
593 {
594 i2c->BUSTOUT = 0xFFU;
595 }
596 else
597 {
598 i2c->BUSTOUT = u32Div;
599 }
600
601}
602
617void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
618{
619 uint32_t u32Div, u32Pclk_kHz;
620
621 i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
622
623 /* DIV4 disabled */
624 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
625 u32Pclk_kHz = u32Pclk / 1000U;
626 u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
627 if(u32Div <= 0xFFU)
628 {
629 i2c->BUSTOUT = u32Div;
630 }
631 else
632 {
633 /* DIV4 enabled */
635 i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
636 }
637}
638
653void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
654{
655 uint32_t u32Div, u32Pclk_kHz;
656
657 i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
658
659 /* DIV4 disabled */
660 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
661 u32Pclk_kHz = u32Pclk / 1000U;
662 u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
663 if(u32Div <= 0xFFU)
664 {
665 i2c->CLKTOUT = u32Div;
666 }
667 else
668 {
669 /* DIV4 enabled */
671 i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
672 }
673}
674
675
690uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
691{
692 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
693
695
696 I2C_START(i2c);
697 while(u8Xfering && (u8Err == 0u))
698 {
699 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
700 I2C_WAIT_READY(i2c)
701 {
702 u32TimeOutCount--;
703 if(u32TimeOutCount == 0)
704 {
706 u8Err = 1u;
707 break;
708 }
709 }
710
711 switch(I2C_GET_STATUS(i2c))
712 {
713 case 0x08u:
714 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
715 u8Ctrl = I2C_CTL_SI; /* Clear SI */
716 break;
717 case 0x18u: /* Slave Address ACK */
718 I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */
719 break;
720 case 0x20u: /* Slave Address NACK */
721 case 0x30u: /* Master transmit data NACK */
722 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
723 u8Err = 1u;
724 break;
725 case 0x28u:
726 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
727 u8Xfering = 0u;
728 break;
729 case 0x38u: /* Arbitration Lost */
730 default: /* Unknow status */
731 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
732 u8Ctrl = I2C_CTL_SI;
733 u8Err = 1u;
734 break;
735 }
736 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
737 }
738 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
739}
740
755uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen)
756{
757 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
758 uint32_t u32txLen = 0u;
759
761
762 I2C_START(i2c); /* Send START */
763 while(u8Xfering && (u8Err == 0u))
764 {
765 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
766 I2C_WAIT_READY(i2c)
767 {
768 u32TimeOutCount--;
769 if(u32TimeOutCount == 0)
770 {
772 break;
773 }
774 }
775
776 switch(I2C_GET_STATUS(i2c))
777 {
778 case 0x08u:
779 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
780 u8Ctrl = I2C_CTL_SI; /* Clear SI */
781 break;
782 case 0x18u: /* Slave Address ACK */
783 case 0x28u:
784 if(u32txLen < u32wLen)
785 {
786 I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */
787 }
788 else
789 {
790 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
791 u8Xfering = 0u;
792 }
793 break;
794 case 0x20u: /* Slave Address NACK */
795 case 0x30u: /* Master transmit data NACK */
796 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
797 u8Err = 1u;
798 break;
799 case 0x38u: /* Arbitration Lost */
800 default: /* Unknow status */
801 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
802 u8Ctrl = I2C_CTL_SI;
803 u8Err = 1u;
804 break;
805 }
806 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
807 }
808 return u32txLen; /* Return bytes length that have been transmitted */
809}
810
826uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
827{
828 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
829 uint32_t u32txLen = 0u;
830
832
833 I2C_START(i2c); /* Send START */
834 while(u8Xfering && (u8Err == 0u))
835 {
836 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
837 I2C_WAIT_READY(i2c)
838 {
839 u32TimeOutCount--;
840 if(u32TimeOutCount == 0)
841 {
843 break;
844 }
845 }
846
847 switch(I2C_GET_STATUS(i2c))
848 {
849 case 0x08u:
850 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */
851 u8Ctrl = I2C_CTL_SI; /* Clear SI */
852 break;
853 case 0x18u: /* Slave Address ACK */
854 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
855 break;
856 case 0x20u: /* Slave Address NACK */
857 case 0x30u: /* Master transmit data NACK */
858 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
859 u8Err = 1u;
860 break;
861 case 0x28u:
862 if(u32txLen < 1u)
863 {
864 I2C_SET_DATA(i2c, data);
865 u32txLen++;
866 }
867 else
868 {
869 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
870 u8Xfering = 0u;
871 }
872 break;
873 case 0x38u: /* Arbitration Lost */
874 default: /* Unknow status */
875 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
876 u8Ctrl = I2C_CTL_SI;
877 u8Err = 1u;
878 break;
879 }
880 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
881 }
882 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
883}
884
885
901uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen)
902{
903 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
904 uint32_t u32txLen = 0u;
905
907
908 I2C_START(i2c); /* Send START */
909 while(u8Xfering && (u8Err == 0u))
910 {
911 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
912 I2C_WAIT_READY(i2c)
913 {
914 u32TimeOutCount--;
915 if(u32TimeOutCount == 0)
916 {
918 break;
919 }
920 }
921
922 switch(I2C_GET_STATUS(i2c))
923 {
924 case 0x08u:
925 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
926 u8Ctrl = I2C_CTL_SI;
927 break;
928 case 0x18u: /* Slave Address ACK */
929 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
930 break;
931 case 0x20u: /* Slave Address NACK */
932 case 0x30u: /* Master transmit data NACK */
933 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
934 u8Err = 1u;
935 break;
936 case 0x28u:
937 if(u32txLen < u32wLen)
938 {
939 I2C_SET_DATA(i2c, data[u32txLen++]);
940 }
941 else
942 {
943 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
944 u8Xfering = 0u;
945 }
946 break;
947 case 0x38u: /* Arbitration Lost */
948 default: /* Unknow status */
949 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
950 u8Ctrl = I2C_CTL_SI;
951 u8Err = 1u;
952 break;
953 }
954 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
955 }
956
957 return u32txLen; /* Return bytes length that have been transmitted */
958}
959
975uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
976{
977 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
978 uint32_t u32txLen = 0u;
979
981
982 I2C_START(i2c); /* Send START */
983 while(u8Xfering && (u8Err == 0u))
984 {
985 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
986 I2C_WAIT_READY(i2c)
987 {
988 u32TimeOutCount--;
989 if(u32TimeOutCount == 0)
990 {
992 break;
993 }
994 }
995
996 switch(I2C_GET_STATUS(i2c))
997 {
998 case 0x08u:
999 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1000 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1001 break;
1002 case 0x18u: /* Slave Address ACK */
1003 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1004 break;
1005 case 0x20u: /* Slave Address NACK */
1006 case 0x30u: /* Master transmit data NACK */
1007 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1008 u8Err = 1u;
1009 break;
1010 case 0x28u:
1011 if(u8Addr)
1012 {
1013 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1014 u8Addr = 0u;
1015 }
1016 else if((u32txLen < 1u) && (u8Addr == 0u))
1017 {
1018 I2C_SET_DATA(i2c, data);
1019 u32txLen++;
1020 }
1021 else
1022 {
1023 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1024 u8Xfering = 0u;
1025 }
1026 break;
1027 case 0x38u: /* Arbitration Lost */
1028 default: /* Unknow status */
1029 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1030 u8Ctrl = I2C_CTL_SI;
1031 u8Err = 1u;
1032 break;
1033 }
1034 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1035 }
1036 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
1037}
1038
1039
1055uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen)
1056{
1057 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
1058 uint32_t u32txLen = 0u;
1059
1060 g_I2C_i32ErrCode = 0;
1061
1062 I2C_START(i2c); /* Send START */
1063 while(u8Xfering && (u8Err == 0u))
1064 {
1065 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1066 I2C_WAIT_READY(i2c)
1067 {
1068 u32TimeOutCount--;
1069 if(u32TimeOutCount == 0)
1070 {
1072 break;
1073 }
1074 }
1075
1076 switch(I2C_GET_STATUS(i2c))
1077 {
1078 case 0x08u:
1079 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1080 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1081 break;
1082 case 0x18u: /* Slave Address ACK */
1083 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1084 break;
1085 case 0x20u: /* Slave Address NACK */
1086 case 0x30u: /* Master transmit data NACK */
1087 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1088 u8Err = 1u;
1089 break;
1090 case 0x28u:
1091 if(u8Addr)
1092 {
1093 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1094 u8Addr = 0u;
1095 }
1096 else if((u32txLen < u32wLen) && (u8Addr == 0u))
1097 {
1098 I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/
1099 }
1100 else
1101 {
1102 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1103 u8Xfering = 0u;
1104 }
1105 break;
1106 case 0x38u: /* Arbitration Lost */
1107 default: /* Unknow status */
1108 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1109 u8Ctrl = I2C_CTL_SI;
1110 u8Err = 1u;
1111 break;
1112 }
1113 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1114 }
1115 return u32txLen; /* Return bytes length that have been transmitted */
1116}
1117
1129uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
1130{
1131 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
1132
1133 g_I2C_i32ErrCode = 0;
1134
1135 I2C_START(i2c); /* Send START */
1136 while(u8Xfering && (u8Err == 0u))
1137 {
1138 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1139 I2C_WAIT_READY(i2c)
1140 {
1141 u32TimeOutCount--;
1142 if(u32TimeOutCount == 0)
1143 {
1145 break;
1146 }
1147 }
1148
1149 switch(I2C_GET_STATUS(i2c))
1150 {
1151 case 0x08u:
1152 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1153 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1154 break;
1155 case 0x40u: /* Slave Address ACK */
1156 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1157 break;
1158 case 0x48u: /* Slave Address NACK */
1159 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1160 u8Err = 1u;
1161 break;
1162 case 0x58u:
1163 rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1164 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1165 u8Xfering = 0u;
1166 break;
1167 case 0x38u: /* Arbitration Lost */
1168 default: /* Unknow status */
1169 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1170 u8Ctrl = I2C_CTL_SI;
1171 u8Err = 1u;
1172 break;
1173 }
1174 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1175 }
1176 if(u8Err)
1177 {
1178 rdata = 0u; /* If occurs error, return 0 */
1179 }
1180 return rdata; /* Return read data */
1181}
1182
1183
1198uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen)
1199{
1200 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
1201 uint32_t u32rxLen = 0u;
1202
1203 g_I2C_i32ErrCode = 0;
1204
1205 I2C_START(i2c); /* Send START */
1206 while(u8Xfering && (u8Err == 0u))
1207 {
1208 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1209 I2C_WAIT_READY(i2c)
1210 {
1211 u32TimeOutCount--;
1212 if(u32TimeOutCount == 0)
1213 {
1215 break;
1216 }
1217 }
1218
1219 switch(I2C_GET_STATUS(i2c))
1220 {
1221 case 0x08u:
1222 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1223 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1224 break;
1225 case 0x40u: /* Slave Address ACK */
1226 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1227 break;
1228 case 0x48u: /* Slave Address NACK */
1229 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1230 u8Err = 1u;
1231 break;
1232 case 0x50u:
1233 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1234 if(u32rxLen < (u32rLen - 1u))
1235 {
1236 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1237 }
1238 else
1239 {
1240 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1241 }
1242 break;
1243 case 0x58u:
1244 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1245 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1246 u8Xfering = 0u;
1247 break;
1248 case 0x38u: /* Arbitration Lost */
1249 default: /* Unknow status */
1250 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1251 u8Ctrl = I2C_CTL_SI;
1252 u8Err = 1u;
1253 break;
1254 }
1255 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1256 }
1257 return u32rxLen; /* Return bytes length that have been received */
1258}
1259
1260
1274uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
1275{
1276 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
1277
1278 g_I2C_i32ErrCode = 0;
1279
1280 I2C_START(i2c); /* Send START */
1281 while(u8Xfering && (u8Err == 0u))
1282 {
1283 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1284 I2C_WAIT_READY(i2c)
1285 {
1286 u32TimeOutCount--;
1287 if(u32TimeOutCount == 0)
1288 {
1290 break;
1291 }
1292 }
1293
1294 switch(I2C_GET_STATUS(i2c))
1295 {
1296 case 0x08u:
1297 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1298 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1299 break;
1300 case 0x18u: /* Slave Address ACK */
1301 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
1302 break;
1303 case 0x20u: /* Slave Address NACK */
1304 case 0x30u: /* Master transmit data NACK */
1305 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1306 u8Err = 1u;
1307 break;
1308 case 0x28u:
1309 u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
1310 break;
1311 case 0x10u:
1312 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1313 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1314 break;
1315 case 0x40u: /* Slave Address ACK */
1316 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1317 break;
1318 case 0x48u: /* Slave Address NACK */
1319 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1320 u8Err = 1u;
1321 break;
1322 case 0x58u:
1323 rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1324 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1325 u8Xfering = 0u;
1326 break;
1327 case 0x38u: /* Arbitration Lost */
1328 default: /* Unknow status */
1329 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1330 u8Ctrl = I2C_CTL_SI;
1331 u8Err = 1u;
1332 break;
1333 }
1334 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1335 }
1336 if(u8Err)
1337 {
1338 rdata = 0u; /* If occurs error, return 0 */
1339 }
1340 return rdata; /* Return read data */
1341}
1342
1358uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen)
1359{
1360 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
1361 uint32_t u32rxLen = 0u;
1362
1363 g_I2C_i32ErrCode = 0;
1364
1365 I2C_START(i2c); /* Send START */
1366 while(u8Xfering && (u8Err == 0u))
1367 {
1368 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1369 I2C_WAIT_READY(i2c)
1370 {
1371 u32TimeOutCount--;
1372 if(u32TimeOutCount == 0)
1373 {
1375 break;
1376 }
1377 }
1378
1379 switch(I2C_GET_STATUS(i2c))
1380 {
1381 case 0x08u:
1382 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1383 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1384 break;
1385 case 0x18u: /* Slave Address ACK */
1386 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
1387 break;
1388 case 0x20u: /* Slave Address NACK */
1389 case 0x30u: /* Master transmit data NACK */
1390 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1391 u8Err = 1u;
1392 break;
1393 case 0x28u:
1394 u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
1395 break;
1396 case 0x10u:
1397 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1398 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1399 break;
1400 case 0x40u: /* Slave Address ACK */
1401 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1402 break;
1403 case 0x48u: /* Slave Address NACK */
1404 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1405 u8Err = 1u;
1406 break;
1407 case 0x50u:
1408 rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1409 if(u32rxLen < (u32rLen - 1u))
1410 {
1411 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1412 }
1413 else
1414 {
1415 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1416 }
1417 break;
1418 case 0x58u:
1419 rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1420 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1421 u8Xfering = 0u;
1422 break;
1423 case 0x38u: /* Arbitration Lost */
1424 default: /* Unknow status */
1425 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1426 u8Ctrl = I2C_CTL_SI;
1427 u8Err = 1u;
1428 break;
1429 }
1430 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1431 }
1432 return u32rxLen; /* Return bytes length that have been received */
1433}
1434
1448uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
1449{
1450 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;
1451
1452 g_I2C_i32ErrCode = 0;
1453
1454 I2C_START(i2c); /* Send START */
1455 while(u8Xfering && (u8Err == 0u))
1456 {
1457 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1458 I2C_WAIT_READY(i2c)
1459 {
1460 u32TimeOutCount--;
1461 if(u32TimeOutCount == 0)
1462 {
1464 break;
1465 }
1466 }
1467
1468 switch(I2C_GET_STATUS(i2c))
1469 {
1470 case 0x08u:
1471 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1472 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1473 break;
1474 case 0x18u: /* Slave Address ACK */
1475 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1476 break;
1477 case 0x20u: /* Slave Address NACK */
1478 case 0x30u: /* Master transmit data NACK */
1479 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1480 u8Err = 1u;
1481 break;
1482 case 0x28u:
1483 if(u8Addr)
1484 {
1485 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1486 u8Addr = 0u;
1487 }
1488 else
1489 {
1490 u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
1491 }
1492 break;
1493 case 0x10u:
1494 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1495 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1496 break;
1497 case 0x40u: /* Slave Address ACK */
1498 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1499 break;
1500 case 0x48u: /* Slave Address NACK */
1501 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1502 u8Err = 1u;
1503 break;
1504 case 0x58u:
1505 rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1506 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1507 u8Xfering = 0u;
1508 break;
1509 case 0x38u: /* Arbitration Lost */
1510 default: /* Unknow status */
1511 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1512 u8Ctrl = I2C_CTL_SI;
1513 u8Err = 1u;
1514 break;
1515 }
1516 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1517 }
1518 if(u8Err)
1519 {
1520 rdata = 0u; /* If occurs error, return 0 */
1521 }
1522 return rdata; /* Return read data */
1523}
1524
1540uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen)
1541{
1542 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
1543 uint32_t u32rxLen = 0u;
1544
1545 g_I2C_i32ErrCode = 0;
1546
1547 I2C_START(i2c); /* Send START */
1548 while(u8Xfering && (u8Err == 0u))
1549 {
1550 uint32_t u32TimeOutCount = SystemCoreClock; // 1 second timeout
1551 I2C_WAIT_READY(i2c)
1552 {
1553 u32TimeOutCount--;
1554 if(u32TimeOutCount == 0)
1555 {
1557 break;
1558 }
1559 }
1560
1561 switch(I2C_GET_STATUS(i2c))
1562 {
1563 case 0x08u:
1564 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1565 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1566 break;
1567 case 0x18u: /* Slave Address ACK */
1568 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1569 break;
1570 case 0x20u: /* Slave Address NACK */
1571 case 0x30u: /* Master transmit data NACK */
1572 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1573 u8Err = 1u;
1574 break;
1575 case 0x28u:
1576 if(u8Addr)
1577 {
1578 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1579 u8Addr = 0u;
1580 }
1581 else
1582 {
1583 u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
1584 }
1585 break;
1586 case 0x10u:
1587 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1588 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1589 break;
1590 case 0x40u: /* Slave Address ACK */
1591 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1592 break;
1593 case 0x48u: /* Slave Address NACK */
1594 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1595 u8Err = 1u;
1596 break;
1597 case 0x50u:
1598 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1599 if(u32rxLen < (u32rLen - 1u))
1600 {
1601 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1602 }
1603 else
1604 {
1605 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1606 }
1607 break;
1608 case 0x58u:
1609 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1610 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1611 u8Xfering = 0u;
1612 break;
1613 case 0x38u: /* Arbitration Lost */
1614 default: /* Unknow status */
1615 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1616 u8Ctrl = I2C_CTL_SI;
1617 u8Err = 1u;
1618 break;
1619 }
1620 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1621 }
1622 return u32rxLen; /* Return bytes length that have been received */
1623}
1624
1625 /* end of group I2C_EXPORTED_FUNCTIONS */
1627 /* end of group I2C_Driver */
1629 /* end of group Standard_Driver */
1631
1632/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
NuMicro peripheral access layer header file.
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:206
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:166
int32_t g_I2C_i32ErrCode
Definition: i2c.c:19
#define I2C_CTL_STO
Definition: i2c.h:42
#define I2C_CTL_SI_AA
Definition: i2c.h:40
#define I2C_CTL_AA
Definition: i2c.h:43
#define I2C_CTL_STA_SI
Definition: i2c.h:35
#define I2C_CTL_SI
Definition: i2c.h:39
#define I2C_CTL_STO_SI
Definition: i2c.h:37
#define I2C_CTL_STA
Definition: i2c.h:41
#define I2C_SMBH_ENABLE
Definition: i2c.h:54
#define I2C_TIMEOUT_ERR
Definition: i2c.h:30
uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
To get SMBus Status.
Definition: i2c.c:452
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl)
The macro is used to set I2C bus condition at One Time.
Definition: i2c.h:77
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
Calculate Time-out of SMBus idle period.
Definition: i2c.c:585
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen)
Specify two bytes register address and write multi bytes to Slave.
Definition: i2c.c:1055
#define I2C_GET_DATA(i2c)
The macro is used to Read I2C Bus Data Register.
Definition: i2c.h:113
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
Configure the mask bits of 7-bit Slave Address.
Definition: i2c.c:351
#define I2C_GET_STATUS(i2c)
Get I2C Bus status code.
Definition: i2c.h:138
void I2C_Close(I2C_T *i2c)
Disable specify I2C Controller.
Definition: i2c.c:72
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
Set SMBus Bytes Counts of Transmission or Reception.
Definition: i2c.c:484
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
Set I2C Bus Clock.
Definition: i2c.c:217
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen)
Specify a byte register address and read multi bytes from Slave.
Definition: i2c.c:1358
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
Set Control bit of I2C Controller.
Definition: i2c.c:124
void I2C_SMBusClose(I2C_T *i2c)
Disable SMBus function.
Definition: i2c.c:526
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
Enable Time-out Counter Function and support Long Time-out.
Definition: i2c.c:383
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
Calculate Cumulative Clock low Time-out of SMBus active period.
Definition: i2c.c:653
void I2C_ClearTimeoutFlag(I2C_T *i2c)
Clear Time-out Counter flag.
Definition: i2c.c:105
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
Set 7-bit Slave Address and GC Mode.
Definition: i2c.c:319
void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
Send a byte to I2C Bus.
Definition: i2c.c:300
#define I2C_WAIT_READY(i2c)
The macro is used to wait I2C bus status get ready.
Definition: i2c.h:101
uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
Get I2C Bus Clock.
Definition: i2c.c:190
void I2C_EnableInt(I2C_T *i2c)
Enable Interrupt of I2C Controller.
Definition: i2c.c:176
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
Read a byte from Slave.
Definition: i2c.c:1129
void I2C_DisableWakeup(I2C_T *i2c)
Disable I2C Wake-up Function.
Definition: i2c.c:437
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen)
Read multi bytes from Slave.
Definition: i2c.c:1198
uint32_t I2C_GetStatus(I2C_T *i2c)
Get I2C Bus Status Code.
Definition: i2c.c:271
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen)
Write multi bytes to Slave.
Definition: i2c.c:755
void I2C_DisableInt(I2C_T *i2c)
Disable Interrupt of I2C Controller.
Definition: i2c.c:161
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen)
Specify two bytes register address and read multi bytes from Slave.
Definition: i2c.c:1540
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen)
Specify a byte register address and write multi bytes to Slave.
Definition: i2c.c:901
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
Specify two bytes register address and Write a byte to Slave.
Definition: i2c.c:975
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
Specify a byte register address and read a byte from Slave.
Definition: i2c.c:1274
#define I2C_SET_DATA(i2c, u8Data)
Write a Data to I2C Data Register.
Definition: i2c.h:126
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
Enable SMBus PEC Transmit Function.
Definition: i2c.c:543
void I2C_EnableWakeup(I2C_T *i2c)
Enable I2C Wake-up Function.
Definition: i2c.c:422
#define I2C_START(i2c)
The macro is used to set START condition of I2C Bus.
Definition: i2c.h:89
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
Specify two bytes register address and read a byte from Slave.
Definition: i2c.c:1448
void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
Init SMBus Host/Device Mode.
Definition: i2c.c:500
uint32_t I2C_GetIntFlag(I2C_T *i2c)
Get Interrupt Flag.
Definition: i2c.c:246
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
Calculate Time-out of SMBus active period.
Definition: i2c.c:617
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
Specify a byte register address and write a byte to Slave.
Definition: i2c.c:826
uint8_t I2C_GetData(I2C_T *i2c)
Read a Byte from I2C Bus.
Definition: i2c.c:285
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
Get SMBus CRC value.
Definition: i2c.c:567
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
Enable specify I2C Controller and set Clock Divider.
Definition: i2c.c:38
void I2C_DisableTimeout(I2C_T *i2c)
Disable Time-out Counter Function.
Definition: i2c.c:407
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
Clear SMBus Interrupt Flag.
Definition: i2c.c:468
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
Write a byte to Slave.
Definition: i2c.c:690
#define I2C1
Definition: M480.h:438
#define SYS
Definition: M480.h:367
#define I2C2_BASE
Definition: M480.h:316
#define I2C0_BASE
Definition: M480.h:315
#define I2C1_BASE
Definition: M480.h:342
#define SYS_IPRST1_I2C1RST_Msk
Definition: sys_reg.h:4915
#define I2C_BUSCTL_PECEN_Msk
Definition: i2c_reg.h:1209
#define I2C_BUSCTL_PECTXEN_Msk
Definition: i2c_reg.h:1230
#define I2C_TOCTL_TOIF_Msk
Definition: i2c_reg.h:1116
#define I2C_CTL0_I2CEN_Msk
Definition: i2c_reg.h:1095
#define SYS_IPRST1_I2C2RST_Msk
Definition: sys_reg.h:4918
#define I2C_TOCTL_TOCEN_Msk
Definition: i2c_reg.h:1122
#define I2C_BUSCTL_BMDEN_Msk
Definition: i2c_reg.h:1212
#define I2C_BUSCTL_TIDLE_Msk
Definition: i2c_reg.h:1233
#define I2C_WKCTL_WKEN_Msk
Definition: i2c_reg.h:1155
#define I2C_BUSCTL_BUSEN_Msk
Definition: i2c_reg.h:1227
#define SYS_IPRST1_I2C0RST_Msk
Definition: sys_reg.h:4912
#define I2C_BUSCTL_BMHEN_Msk
Definition: i2c_reg.h:1215
#define I2C_CTL0_SI_Msk
Definition: i2c_reg.h:1086
#define I2C_CTL0_INTEN_Msk
Definition: i2c_reg.h:1098
#define I2C_TOCTL_TOCDIV4_Msk
Definition: i2c_reg.h:1119
Definition: i2c_reg.h:27
__IO uint32_t CLKTOUT
Definition: i2c_reg.h:1073
__IO uint32_t ADDR2
Definition: i2c_reg.h:1053
__IO uint32_t ADDR3
Definition: i2c_reg.h:1054
__IO uint32_t ADDRMSK1
Definition: i2c_reg.h:1056
__IO uint32_t ADDR0
Definition: i2c_reg.h:1047
__IO uint32_t TOCTL
Definition: i2c_reg.h:1051
__IO uint32_t CLKDIV
Definition: i2c_reg.h:1050
__IO uint32_t DAT
Definition: i2c_reg.h:1048
__I uint32_t PKTCRC
Definition: i2c_reg.h:1071
__IO uint32_t ADDR1
Definition: i2c_reg.h:1052
__IO uint32_t BUSTOUT
Definition: i2c_reg.h:1072
__IO uint32_t CTL0
Definition: i2c_reg.h:1046
__IO uint32_t ADDRMSK2
Definition: i2c_reg.h:1057
__IO uint32_t BUSSTS
Definition: i2c_reg.h:1069
__IO uint32_t ADDRMSK0
Definition: i2c_reg.h:1055
__IO uint32_t BUSCTL
Definition: i2c_reg.h:1067
__IO uint32_t ADDRMSK3
Definition: i2c_reg.h:1058
__IO uint32_t PKTSIZE
Definition: i2c_reg.h:1070
__I uint32_t STATUS0
Definition: i2c_reg.h:1049
__IO uint32_t WKCTL
Definition: i2c_reg.h:1062
uint32_t SystemCoreClock
Definition: system_M480.c:21