M480 BSP V3.05.006
The Board Support Package for M480 Series
eadc.h
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1/**************************************************************************/
9#ifndef __EADC_H__
10#define __EADC_H__
11
12#ifdef __cplusplus
13extern "C"
14{
15#endif
16
17
30/*---------------------------------------------------------------------------------------------------------*/
31/* EADC_CTL Constant Definitions */
32/*---------------------------------------------------------------------------------------------------------*/
33#define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos)
34#define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos)
36#define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos)
37#define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos)
39/*---------------------------------------------------------------------------------------------------------*/
40/* EADC_SCTL Constant Definitions */
41/*---------------------------------------------------------------------------------------------------------*/
42#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos)
43#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos)
44#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos)
46#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos)
47#define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))
48#define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))
49#define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))
50#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos)
51#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos)
52#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos)
53#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos)
54#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos)
55#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos)
56#define EADC_EPWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos)
57#define EADC_EPWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos)
58#define EADC_EPWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos)
59#define EADC_EPWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos)
60#define EADC_EPWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos)
61#define EADC_EPWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos)
62#define EADC_EPWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos)
63#define EADC_EPWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos)
64#define EADC_EPWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos)
65#define EADC_EPWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos)
66#define EADC_EPWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos)
67#define EADC_EPWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos)
68#define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos)
69#define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos)
71#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos)
72#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos)
73#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos)
74#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos)
77/*---------------------------------------------------------------------------------------------------------*/
78/* EADC_CMP Constant Definitions */
79/*---------------------------------------------------------------------------------------------------------*/
80#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos)
81#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos)
82#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk)
83#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk)
84#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk)
85#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk)
88/*---------------------------------------------------------------------------------------------------------*/
89/* Define Error Code */
90/*---------------------------------------------------------------------------------------------------------*/
91#define EADC_TIMEOUT_ERR (-1) /* end of group EADC_EXPORTED_CONSTANTS */
94
95extern int32_t g_EADC_i32ErrCode;
96
100/*---------------------------------------------------------------------------------------------------------*/
101/* EADC Macro Definitions */
102/*---------------------------------------------------------------------------------------------------------*/
103
111#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
112
122#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
123
131#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
132
143#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask)
144
154#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask))
155
165#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
166
175#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
176
185#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
186
195#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
196
207#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
208
218#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
219
230#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
231
242#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
243
254#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
255
266#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
267
278#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
279
288#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
289
298#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
299
308#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
309
318#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
319
328#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
329
340#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
341
350#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
351
362#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
363
373#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
374
383#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
384
393#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
394
403#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
404
413#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
414
423#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
424
440#define EADC_ENABLE_CMP0(eadc,\
441 u32ModuleNum,\
442 u32Condition,\
443 u16CMPData,\
444 u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
445 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
446 (u32Condition) |\
447 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
448 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
449 EADC_CMP_ADCMPEN_Msk)))
450
466#define EADC_ENABLE_CMP1(eadc,\
467 u32ModuleNum,\
468 u32Condition,\
469 u16CMPData,\
470 u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
471 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
472 (u32Condition) |\
473 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
474 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
475 EADC_CMP_ADCMPEN_Msk)))
476
492#define EADC_ENABLE_CMP2(eadc,\
493 u32ModuleNum,\
494 u32Condition,\
495 u16CMPData,\
496 u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
497 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
498 (u32Condition) |\
499 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
500 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
501 EADC_CMP_ADCMPEN_Msk)))
502
518#define EADC_ENABLE_CMP3(eadc,\
519 u32ModuleNum,\
520 u32Condition,\
521 u16CMPData,\
522 u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
523 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
524 (u32Condition) |\
525 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
526 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
527 EADC_CMP_ADCMPEN_Msk)))
528
537#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
538
547#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
548
559#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
560
569#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
570
578#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
579
587#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
588
596#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
597
605#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
606
607/*---------------------------------------------------------------------------------------------------------*/
608/* Define EADC functions prototype */
609/*---------------------------------------------------------------------------------------------------------*/
610void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
611void EADC_Close(EADC_T *eadc);
612void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
613void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
614void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
615 /* end of group EADC_EXPORTED_FUNCTIONS */
617 /* end of group EADC_Driver */
619 /* end of group Standard_Driver */
621
622#ifdef __cplusplus
623}
624#endif
625
626#endif /* __EADC_H__ */
627
628/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
int32_t g_EADC_i32ErrCode
Definition: eadc.c:19
void EADC_Close(EADC_T *eadc)
Disable EADC_module.
Definition: eadc.c:61
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
Set ADC extend sample time.
Definition: eadc.c:142
void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider)
Set trigger delay time.
Definition: eadc.c:124
void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel)
Configure the sample control logic module.
Definition: eadc.c:100
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
This function make EADC_module be ready to convert.
Definition: eadc.c:36