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NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
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Modules | |
CLK Exported Functions | |
Variables | |
int32_t | g_CLK_i32ErrCode |
#define CLK_ADC_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_ADCDIV_Pos) & CLK_CLKDIV0_ADCDIV_Msk) /* CLKDIV0 Setting for ADC clock divider. It could be 1~256*/ |
#define CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002) |
#define CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001) |
#define CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004) |
#define CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010) |
#define CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020) |
#define CLK_APB0DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB0DIV_Pos) |
#define CLK_APB0DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB0DIV_Pos) |
#define CLK_APB0DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB0DIV_Pos) |
#define CLK_APB0DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB0DIV_Pos) |
#define CLK_APB0DIV_HCLK (0x0UL<<CLK_APBDIV_APB0DIV_Pos) |
#define CLK_APB1DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB1DIV_Pos) |
#define CLK_APB1DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB1DIV_Pos) |
#define CLK_APB1DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB1DIV_Pos) |
#define CLK_APB1DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB1DIV_Pos) |
#define CLK_APB1DIV_HCLK (0x0UL<<CLK_APBDIV_APB1DIV_Pos) |
#define CLK_APBCLK_ACMP0_EN ((uint32_t)0x00000800) |
#define CLK_APBCLK_ADC_EN ((uint32_t)0x10000000) |
#define CLK_APBCLK_CLKOC_EN ((uint32_t)0x00000040) |
#define CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100) |
#define CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200) |
#define CLK_APBCLK_PWM0_EN ((uint32_t)0x00100000) |
#define CLK_APBCLK_RTC_EN ((uint32_t)0x00000002) |
#define CLK_APBCLK_SC0_EN ((uint32_t)0x40000000) |
#define CLK_APBCLK_SC1_EN ((uint32_t)0x80000000) |
#define CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000) |
#define CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000) |
#define CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000) |
#define CLK_APBCLK_SPI3_EN ((uint32_t)0x00008000) |
#define CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004) |
#define CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008) |
#define CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010) |
#define CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020) |
#define CLK_APBCLK_UART0_EN ((uint32_t)0x00010000) |
#define CLK_APBCLK_UART1_EN ((uint32_t)0x00020000) |
#define CLK_APBCLK_WDT_EN ((uint32_t)0x00000001) |
#define CLK_CLKO_EN ((uint32_t)0x00000010) |
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_HIRC0 (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_HIRC1 (0xCUL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_MIRC (0x5UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
#define CLK_CLKSEL0_ISPSEL_HIRC (0x0UL<<CLK_CLKSEL0_ISPSEL_Pos) |
#define CLK_CLKSEL0_ISPSEL_MIRC (0x1UL<<CLK_CLKSEL0_ISPSEL_Pos) |
#define CLK_CLKSEL0_STCLKSEL_HCLK (1) |
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) |
#define CLK_CLKSEL1_ADCSEL_HCLK (0x5UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_ADCSEL_LXT (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_ADCSEL_MIRC (0x4UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_ADCSEL_PLL (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) |
#define CLK_CLKSEL1_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL1_PWM0SEL_Pos) |
#define CLK_CLKSEL1_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL1_PWM0SEL_Pos) |
#define CLK_CLKSEL1_SPI0SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos) |
#define CLK_CLKSEL1_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI0SEL_Pos) |
#define CLK_CLKSEL1_SPI0SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI0SEL_Pos) |
#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos) |
#define CLK_CLKSEL1_SPI2SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos) |
#define CLK_CLKSEL1_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI2SEL_Pos) |
#define CLK_CLKSEL1_SPI2SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI2SEL_Pos) |
#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR0SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_TMR1SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos) |
#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos) |
#define CLK_CLKSEL1_UART0SEL_LXT (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos) |
#define CLK_CLKSEL1_UART0SEL_MIRC (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos) |
#define CLK_CLKSEL1_UART0SEL_PLL (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos) |
#define CLK_CLKSEL1_WDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) |
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) |
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) |
#define CLK_CLKSEL1_WWDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) |
#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) |
#define CLK_CLKSEL2_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL2_CLKOSEL_Pos) |
#define CLK_CLKSEL2_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL2_CLKOSEL_Pos) |
#define CLK_CLKSEL2_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL2_CLKOSEL_Pos) |
#define CLK_CLKSEL2_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL2_CLKOSEL_Pos) |
#define CLK_CLKSEL2_CLKOSEL_MIRC (0x4UL<<CLK_CLKSEL2_CLKOSEL_Pos) |
#define CLK_CLKSEL2_SC0SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC0SEL_Pos) |
#define CLK_CLKSEL2_SC0SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC0SEL_Pos) |
#define CLK_CLKSEL2_SC0SEL_HXT (0x0UL<<CLK_CLKSEL2_SC0SEL_Pos) |
#define CLK_CLKSEL2_SC0SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC0SEL_Pos) |
#define CLK_CLKSEL2_SC0SEL_PLL (0x1UL<<CLK_CLKSEL2_SC0SEL_Pos) |
#define CLK_CLKSEL2_SC1SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC1SEL_Pos) |
#define CLK_CLKSEL2_SC1SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC1SEL_Pos) |
#define CLK_CLKSEL2_SC1SEL_HXT (0x0UL<<CLK_CLKSEL2_SC1SEL_Pos) |
#define CLK_CLKSEL2_SC1SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC1SEL_Pos) |
#define CLK_CLKSEL2_SC1SEL_PLL (0x1UL<<CLK_CLKSEL2_SC1SEL_Pos) |
#define CLK_CLKSEL2_SPI1SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
#define CLK_CLKSEL2_SPI1SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
#define CLK_CLKSEL2_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
#define CLK_CLKSEL2_SPI3SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos) |
#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) |
#define CLK_CLKSEL2_SPI3SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) |
#define CLK_CLKSEL2_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR2SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR2SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_TMR3SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR3SEL_Pos) |
#define CLK_CLKSEL2_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART1SEL_Pos) |
#define CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos) |
#define CLK_CLKSEL2_UART1SEL_LXT (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos) |
#define CLK_CLKSEL2_UART1SEL_MIRC (0x4UL<<CLK_CLKSEL2_UART1SEL_Pos) |
#define CLK_CLKSEL2_UART1SEL_PLL (0x2UL<<CLK_CLKSEL2_UART1SEL_Pos) |
#define CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080) |
#define CLK_CLKSTATUS_HIRC0_STB ((uint32_t)0x00000010) |
#define CLK_CLKSTATUS_HIRC1_STB ((uint32_t)0x00000020) |
#define CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001) |
#define CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008) |
#define CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002) |
#define CLK_CLKSTATUS_MIRC_STB ((uint32_t)0x00000040) |
#define CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004) |
#define CLK_HCLK_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_HCLKDIV_Pos) & CLK_CLKDIV0_HCLKDIV_Msk) /* CLKDIV0 Setting for HCLK clock divider. It could be 1~16*/ |
#define CLK_PLL_SRC_N | ( | x | ) | (((x)-1)<<8) |
#define CLK_PLLCTL_16MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16)) |
#define CLK_PLLCTL_16MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(16)) |
#define CLK_PLLCTL_16MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(16)) |
#define CLK_PLLCTL_22MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22)) |
#define CLK_PLLCTL_22MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(22)) |
#define CLK_PLLCTL_22MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(22)) |
#define CLK_PLLCTL_24MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24)) |
#define CLK_PLLCTL_24MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(24)) |
#define CLK_PLLCTL_24MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(24)) |
#define CLK_PLLCTL_28MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28)) |
#define CLK_PLLCTL_28MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(28)) |
#define CLK_PLLCTL_28MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(28)) |
#define CLK_PLLCTL_32MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32)) |
#define CLK_PLLCTL_32MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(32)) |
#define CLK_PLLCTL_32MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(32)) |
#define CLK_PLLCTL_36MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(36)) |
#define CLK_PLLCTL_36MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(36)) |
#define CLK_PLLCTL_36MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(36)) |
#define CLK_PLLCTL_PD ((uint32_t)0x00010000) |
#define CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000)) |
#define CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000)) |
#define CLK_PLLCTL_PLL_SRC_MIRC ((uint32_t)(0x00040000)) |
#define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010) |
#define CLK_PWRCTL_HIRC0_EN ((uint32_t)0x00000004) |
#define CLK_PWRCTL_HIRC1_EN ((uint32_t)0x01000000) |
#define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001) |
#define CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000C00) |
#define CLK_PWRCTL_HXT_GAIN_16M_24M ((uint32_t)0x00001000) |
#define CLK_PWRCTL_HXT_GAIN_24M_32M ((uint32_t)0x00001400) |
#define CLK_PWRCTL_HXT_GAIN_32M_36M ((uint32_t)0x00001800) |
#define CLK_PWRCTL_HXT_GAIN_36M ((uint32_t)0x00001C00) |
#define CLK_PWRCTL_HXT_GAIN_4M ((uint32_t)0x00000000) |
#define CLK_PWRCTL_HXT_GAIN_4M_8M ((uint32_t)0x00000400) |
#define CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000800) |
#define CLK_PWRCTL_HXT_HXTSLTYP ((uint32_t)0x00000100) |
#define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100) |
#define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008) |
#define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002) |
#define CLK_PWRCTL_MIRC_EN ((uint32_t)0x02000000) |
#define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040) |
#define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020) |
#define CLK_SC0_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_SC0DIV_Pos) & CLK_CLKDIV0_SC0DIV_Msk) /* CLKDIV0 Setting for SC0 clock divider. It could be 1~16*/ |
#define CLK_SC1_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_SC1DIV_Pos) & CLK_CLKDIV1_SC1DIV_Msk) /* CLKDIV1 Setting for SC1 clock divider. It could be 1~16*/ |
#define CLK_TMR0_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR0DIV_Pos) & CLK_CLKDIV1_TMR0DIV_Msk) /* CLKDIV1 Setting for TMR0 clock divider. It could be 1~16*/ |
#define CLK_TMR1_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR1DIV_Pos) & CLK_CLKDIV1_TMR1DIV_Msk) /* CLKDIV1 Setting for TMR1 clock divider. It could be 1~16*/ |
#define CLK_TMR2_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR2DIV_Pos) & CLK_CLKDIV1_TMR2DIV_Msk) /* CLKDIV1 Setting for TMR2 clock divider. It could be 1~16*/ |
#define CLK_TMR3_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR3DIV_Pos) & CLK_CLKDIV1_TMR3DIV_Msk) /* CLKDIV1 Setting for TMR3 clock divider. It could be 1~16*/ |
#define CLK_UART0_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_UART0DIV_Pos)& CLK_CLKDIV0_UART0DIV_Msk) /* CLKDIV0 Setting for UART0 clock divider. It could be 1~16*/ |
#define CLK_UART1_CLK_DIVIDER | ( | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_UART1DIV_Pos)& CLK_CLKDIV0_UART1DIV_Msk) /* CLKDIV0 Setting for UART1 clock divider. It could be 1~16*/ |
#define CLK_WK_INTSTS_IS ((uint32_t)0x00000001) |
#define MODULE_APBCLK | ( | x | ) | ((x >>31) & 0x1) |
#define MODULE_APBCLK_ENC | ( | x | ) | (((x) & 0x01) << 31) |
#define MODULE_CLKDIV | ( | x | ) | ((x >>18) & 0x3) |
#define MODULE_CLKDIV_ENC | ( | x | ) | (((x) & 0x03) << 18) |
#define MODULE_CLKDIV_Msk | ( | x | ) | ((x >>10) & 0xff) |
#define MODULE_CLKDIV_Msk_ENC | ( | x | ) | (((x) & 0xff) << 10) |
#define MODULE_CLKDIV_Pos | ( | x | ) | ((x >>5 ) & 0x1f) |
#define MODULE_CLKDIV_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 5) |
#define MODULE_CLKSEL | ( | x | ) | ((x >>29) & 0x3) |
#define MODULE_CLKSEL_ENC | ( | x | ) | (((x) & 0x03) << 29) |
#define MODULE_CLKSEL_Msk | ( | x | ) | ((x >>25) & 0xf) |
#define MODULE_CLKSEL_Msk_ENC | ( | x | ) | (((x) & 0x0f) << 25) |
#define MODULE_CLKSEL_Pos | ( | x | ) | ((x >>20) & 0x1f) |
#define MODULE_CLKSEL_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 20) |
#define MODULE_IP_EN_Pos | ( | x | ) | ((x >>0 ) & 0x1f) |
#define MODULE_IP_EN_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 0) |
#define NA MODULE_NoMsk |