Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
PWM_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t PRES
 
__IO uint32_t CLKSEL
 
__IO uint32_t CTL
 
__IO uint32_t INTEN
 
__IO uint32_t INTSTS
 
__IO uint32_t OE
 
uint32_t RESERVE0 [1]
 
__IO uint32_t DUTY0
 
__I uint32_t DATA0
 
uint32_t RESERVE1 [1]
 
__IO uint32_t DUTY1
 
__I uint32_t DATA1
 
uint32_t RESERVE2 [1]
 
__IO uint32_t DUTY2
 
__I uint32_t DATA2
 
uint32_t RESERVE3 [1]
 
__IO uint32_t DUTY3
 
__I uint32_t DATA3
 
uint32_t RESERVE4 [3]
 
__IO uint32_t CAPCTL
 
__IO uint32_t CAPINTEN
 
__IO uint32_t CAPINTSTS
 
__I uint32_t CRL0
 
__I uint32_t CFL0
 
__I uint32_t CRL1
 
__I uint32_t CFL1
 
__I uint32_t CRL2
 
__I uint32_t CFL2
 
__I uint32_t CRL3
 
__I uint32_t CFL3
 
__I uint32_t PDMACH0
 
__I uint32_t PDMACH2
 
__IO uint32_t ADTRGEN
 
__IO uint32_t ADTRGSTS
 

Detailed Description

@addtogroup PWM Pulse Width Modulation Controller(PWM)
Memory Mapped Structure for PWM Controller

Definition at line 5734 of file Nano1X2Series.h.

Field Documentation

◆ ADTRGEN

__IO uint32_t PWM_T::ADTRGEN

ADTRGEN

Offset: 0x88 PWM Center-Triggered Control Register

Bits Field Descriptions
[0] TRGCH0EN PWM CH0 Center-Triggered Enable Control
0 = PWM CH0 center-triggered function Disabled.
1 = PWM CH0 center-triggered function Enabled.
Note: The center-triggered function is only valid in PWM center-aligned mode.
[1] TRGCH1EN PWM CH1 Center-Triggered Enable Control
0 = PWM CH1 center-triggered function Disabled.
1 = PWM CH1 center-triggered function Enabled.
Note: The center-triggered function is only valid in PWM center-aligned mode.
[2] TRGCH2EN PWM CH2 Center-Triggered Enable Control
0 = PWM CH2 center-triggered function Disabled.
1 = PWM CH2 center-triggered function Enabled.
Note: The center-triggered function is only valid in PWM center-aligned mode.
[3] TRGCH3EN PWM CH3 Center-Triggered Enable Control
0 = PWM CH3 center-triggered function Disabled.
1 = PWM CH3 center-triggered function Enabled.
Note: The center-triggered function is only valid in PWM center-aligned mode.

Definition at line 6579 of file Nano1X2Series.h.

◆ ADTRGSTS

__IO uint32_t PWM_T::ADTRGSTS

ADTRGSTS

Offset: 0x8C PWM Center-Triggered Indication Register

Bits Field Descriptions
[0] ADTRG0Flag PWM CH0 Center-Triggered Flag
0 = PWM CH0 has not crossed half of PWM period yet.
1 = PWM CH0 has crossed half of PWM period.
Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
[1] ADTRG1Flag PWM CH1 Center-Triggered Flag
0 = PWM CH1 has not crossed half of PWM period yet.
1 = PWM CH1 has crossed half of PWM period.
Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
[2] ADTRG2Flag PWM CH2 Center-Triggered Flag
0 = PWM CH2 has not crossed half of PWM period yet.
1 = PWM CH2 has crossed half of PWM period.
Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
[3] ADTRG3Flag PWM CH3 Center-Triggered Flag
0 = PWM CH3 has not crossed half of PWM period yet.
1 = PWM CH3 has crossed half of PWM period.
Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag

Definition at line 6605 of file Nano1X2Series.h.

◆ CAPCTL

__IO uint32_t PWM_T::CAPCTL

CAPCTL

Offset: 0x54 Capture Control Register

Bits Field Descriptions
[0] INV0 Channel 0 Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
[1] CAPCH0EN Capture Channel 0 Transition Enable/Disable Control
0 = Capture function on channel 0 Disabled.
1 = Capture function on channel 0 Enabled.
When Enabled, Capture latched the PWM-timer value and saved to CRL0 (PWM_CRL0[15:0]) for rising latch and CFL0 (PWM_CFL0[15:0]) for falling latch.
When Disabled, Capture does not update CRL0 (PWM_CRL0[15:0]) and CFL0 (PWM_CFL0[15:0]), and disable Channel 0 Interrupt.
[2] CAPCH0PADEN Capture Input Enable Control
0 = Disable the channel 0 input capture signal from corresponding multi-function pin.
1 = Enable the channel 0 input capture signal from corresponding multi-function pin.
[3] CH0PDMAEN Channel 0 PDMA Enable Control
0 = Channel 0 PDMA function Disabled.
1 = Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory.
[5:4] PDMACAPMOD0 Select CRL0 Or CFL0 For PDMA Transfer
00 = reserved.
01 = CRL0 will be transmitted.
10 = CFL0 will be transmitted.
11 = Both CRL0 and CFL0 will be transmitted.
[6] CAPRELOADREN0 Reload CNR0 When CH0 Capture Rising Event Comes
0 = Rising capture reload for CH0 Disabled.
1 = Rising capture reload for CH0 Enabled.
[7] CAPRELOADFEN0 Reload CNR0 When CH0 Capture Falling Event Comes
0 = Falling capture reload for CH0 Disabled.
1 = Falling capture reload for CH0 Enabled.
[8] INV1 Channel 1 Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
[9] CAPCH1EN Capture Channel 1 Transition Enable/Disable Control
0 = Capture function on channel 1 Disabled.
1 = Capture function on channel 1 Enabled.
When Enabled, Capture latched the PMW-counter and saved to CRL1 (PWM_CRL1[15:0]) for rising latch and CFL1 (PWM_CFL1[15:0]) for falling latch.
When Disabled, Capture does not update CRL1 (PWM_CRL1[15:0]) and CFL1 (PWM_CFL1[15:0]), and disable Channel 1 Interrupt.
[10] CAPCH1PADEN Capture Input Enable Control
0 = Disable the channel 1 input capture signal from corresponding multi-function pin.
1 = Enable the channel 1 input capture signal from corresponding multi-function pin.
[12] CH0RFORDER Channel 0 capture order control
Set this bit to determine whether the PWM_CRL0 or PWM_CFL0 is the first captured data transferred to memory through PDMA when PDMACAPMOD0 =2'b11.
0 = PWM_CFL0 is the first captured data to memory.
1 = PWM_CRL0 is the first captured data to memory.
[13] CH01CASK Cascade channel 0 and channel 1 PWM timer for capturing usage
[14] CAPRELOADREN1 Reload CNR1 When CH1 Capture Rising Event Comes
0 = Rising capture reload for CH1 Disabled.
1 = Rising capture reload for CH1 Enabled.
[15] CAPRELOADFEN1 Reload CNR1 When CH1 Capture Falling Event Coming
0 = Capture falling reload for CH1 Disabled.
1 = Capture falling reload for CH1 Enabled.
[16] INV2 Channel 2 Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
[17] CAPCH2EN Capture Channel 2 Transition Enable/Disable Control
0 = Capture function on channel 2 Disabled.
1 = Capture function on channel 2 Enabled.
When Enabled, Capture latched the PWM-timer value and saved to CRL2 (PWM_CRL2[15:0]) for rising latch and CFL2 (PWM_CFL2[15:0]) for falling latch.
When Disabled, Capture does not update CRL2 (PWM_CRL2[15:0]) and CFL2 (PWM_CFL2[15:0]), and disable Channel 2 Interrupt.
[18] CAPCH2PADEN Capture Input Enable Control
0 = Disable the channel 2 input capture signal from corresponding multi-function pin.
1 = Enable the channel 2 input capture signal from corresponding multi-function pin.
[19] CH2PDMAEN Channel 2 PDMA Enable Control
0 = Channel 2 PDMA function Disabled.
1 = Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory.
[21:20] PDMACAPMOD2 Select CRL2 Or CFL2 For PDMA Transfer
00 = reserved.
01 = CRL2 will be transmitted.
10 = CFL2 will be transmitted.
11 = Both CRL2 and CFL2 will be transmitted.
[22] CAPRELOADREN2 Reload CNR2 When CH2 Capture Rising Event Coming
0 = Rising capture reload for CH2 Disabled.
1 = Rising capture reload for CH2 Enabled.
[23] CAPRELOADFEN2 Reload CNR2 When CH2 Capture Failing Event Coming
0 = Failing capture reload for CH2 Disabled.
1 = Failing capture reload for CH2 Enabled.
[24] INV3 Channel 3 Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
[25] CAPCH3EN Capture Channel 3 Transition Enable/Disable Control
0 = Capture function on channel 3 Disabled.
1 = Capture function on channel 3 Enabled.
When Enabled, Capture latched the PMW-timer and saved to CRL3 (PWM_CRL3[15:0]) for rising latch and CFL3 (PWM_CFL3[15:0]) for falling latch.
When Disabled, Capture does not update CRL3 (PWM_CRL3[15:0]) and CFL3 (PWM_CFL3[15:0]), and disable Channel 3 Interrupt.
[26] CAPCH3PADEN Capture Input Enable Control
0 = Disable the channel 3 input capture signal from corresponding multi-function pin.
1 = Enable the channel 3 input capture signal from corresponding multi-function pin.
[28] CH2RFORDER Channel 2 capture order control
Set this bit to determine whether the PWM_CRL2 or PWM_CFL2 is the first captured data transferred to memory through PDMA when PDMACAPMOD2 = 2'b11.
0 = PWM_CFL2 is the first captured data to memory.
1 = PWM_CRL2 is the first captured data to memory.
[29] CH23CASK Cascade channel 2 and channel 3 PWM counter for capturing usage
[30] CAPRELOADREN3 Reload CNR3 When CH3 Rising Capture Event Comes
0 = Rising capture reload for CH3 Disabled.
1 = Rising capture reload for CH3 Enabled.
[31] CAPRELOADFEN3 Reload CNR3 When CH3 Falling Capture Event Comes
0 = Falling capture reload for CH3 Disabled.
1 = Falling capture reload for CH3 Enabled.

Definition at line 6296 of file Nano1X2Series.h.

◆ CAPINTEN

__IO uint32_t PWM_T::CAPINTEN

CAPINTEN

Offset: 0x58 Capture interrupt enable Register

Bits Field Descriptions
[0] CRL_IE0 Channel 0 Rising Latch Interrupt Enable ON/OFF
0 = Rising latch interrupt Disabled.
1 = Rising latch interrupt Enabled.
When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
[1] CFL_IE0 Channel 0 Falling Latch Interrupt Enable ON/OFF
0 = Falling latch interrupt Disabled.
1 = Falling latch interrupt Enabled.
When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
[8] CRL_IE1 Channel 1 Rising Latch Interrupt Enable Control
0 = Rising latch interrupt Disabled.
1 = Rising latch interrupt Enabled.
When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
[9] CFL_IE1 Channel 1 Falling Latch Interrupt Enable Control
0 = Falling latch interrupt Disabled.
1 = Falling latch interrupt Enabled.
When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
[16] CRL_IE2 Channel 2 Rising Latch Interrupt Enable ON/OFF
0 = Rising latch interrupt Disabled.
1 = Rising latch interrupt Enabled.
When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
[17] CFL_IE2 Channel 2 Falling Latch Interrupt Enable ON/OFF
0 = Falling latch interrupt Disabled.
1 = Falling latch interrupt Enabled.
When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
[24] CRL_IE3 Channel 3 Rising Latch Interrupt Enable ON/OFF
0 = Rising latch interrupt Disabled.
1 = Rising latch interrupt Enabled.
When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
[25] CFL_IE3 Channel 3 Falling Latch Interrupt Enable ON/OFF
0 = Falling latch interrupt Disabled.
1 = Falling latch interrupt Enabled.
When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.

Definition at line 6338 of file Nano1X2Series.h.

◆ CAPINTSTS

__IO uint32_t PWM_T::CAPINTSTS

CAPINTSTS

Offset: 0x5C Capture Interrupt Indication Register

Bits Field Descriptions
[0] CAPIF0 Capture0 Interrupt Indication Flag
If channel 0 rising latch interrupt (CRL_IE0, PWM_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWM_CAPINTEN[1]) is enabled.
This flag is cleared by software with a write 1 on it.
[1] CRLI0 PWM_CRL0 Latched Indicator Bit
When input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[2] CFLI0 PWM_CFL0 Latched Indicator Bit
When input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[3] CAPOVR0 Capture Rising Flag Over Run For Channel 0
This flag indicate CRL0 update faster than software reading it when it is set
This bit will be cleared automatically when user clears CRLI0 (PWM_CAPINTSTS[1]).
[4] CAPOVF0 Capture Falling Flag Over Run For Channel 0
This flag indicate CFL0 update faster than software read it when it is set
This bit will be cleared automatically when user clear CFLI0 (PWM_CAPINTSTS[2])
[8] CAPIF1 Capture1 Interrupt Indication Flag
If channel 1 rising latch interrupt (CRL_IE1, PWM_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWM_CAPINTEN[9]) is enabled.
This flag is cleared by software with a write 1 on it.
[9] CRLI1 PWM_CRL1 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[10] CFLI1 PWM_CFL1 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[11] CAPOVR1 Capture Rising Flag Over Run For Channel 1
This flag indicate CRL1 update faster than software reading it when it is set
This bit will be cleared automatically when user clear CRLI1 (PWM_CAPINTSTS[9])
[12] CAPOVF1 Capture Falling Flag Over Run For Channel 1
This flag indicate CFL1 update faster than software reading it when it is set
This bit will be cleared automatically when user clear CFLI1 (PWM_CAPINTSTS[10])
[16] CAPIF2 Capture2 Interrupt Indication Flag
If channel 2 rising latch interrupt (CRL_IE2, PWM_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWM_CAPINTEN[17]) is enabled.
This flag is cleared by software with a write 1 on it.
[17] CRLI2 PWM_CRL2 Latched Indicator Bit
When input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[18] CFLI2 PWM_CFL2 Latched Indicator Bit
When input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[19] CAPOVR2 Capture Rising Flag Over Run For Channel 2
This flag indicate CRL2 update faster than software reading it when it is set
This bit will be cleared automatically when user clear CRLI2 (PWM_CAPINTSTS[17])
[20] CAPOVF2 Capture Falling Flag Over Run For Channel 2
This flag indicate CFL2 update faster than software reading it when it is set
This bit will be cleared automatically when user clear CFLI2 (PWM_CAPINTSTS[18])
[24] CAPIF3 Capture3 Interrupt Indication Flag
If channel 3 rising latch interrupt (CRL_IE3, PWM_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWM_CAPINTEN[25]) is enabled.
This flag is cleared by software with a write 1 on it.
[25] CRLI3 PWM_CRL3 Latched Indicator Bit
When input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[26] CFLI3 PWM_CFL3 Latched Indicator Bit
When input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
[27] CAPOVR3 Capture Rising Flag Over Run For Channel 3
This flag indicate CRL3update faster than software reading it when it is set
This bit will be cleared automatically when user clear CRLI3 (PWM_CAPINTSTS[25])
[28] CAPOVF3 Capture Falling Flag Over Run For Channel 3
This flag indicate CFL3 update faster than software reading it when it is set
This bit will be cleared automatically when user clear CFLI3 (PWM_CAPINTSTS[26])

Definition at line 6400 of file Nano1X2Series.h.

◆ CFL0

__I uint32_t PWM_T::CFL0

CFL0

Offset: 0x64 Capture Falling Latch Register (Channel 0)

Bits Field Descriptions
[15:0] CFL Capture Falling Latch Register
Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
[31:16] CFL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,

Definition at line 6428 of file Nano1X2Series.h.

◆ CFL1

__I uint32_t PWM_T::CFL1

CFL1

Offset: 0x6C Capture Falling Latch Register (Channel 1)

Bits Field Descriptions
[15:0] CFL Capture Falling Latch Register
Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
[31:16] CFL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,

Definition at line 6456 of file Nano1X2Series.h.

◆ CFL2

__I uint32_t PWM_T::CFL2

CFL2

Offset: 0x74 Capture Falling Latch Register (Channel 2)

Bits Field Descriptions
[15:0] CFL Capture Falling Latch Register
Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
[31:16] CFL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,

Definition at line 6484 of file Nano1X2Series.h.

◆ CFL3

__I uint32_t PWM_T::CFL3

CFL3

Offset: 0x7C Capture Falling Latch Register (Channel 3)

Bits Field Descriptions
[15:0] CFL Capture Falling Latch Register
Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
[31:16] CFL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,

Definition at line 6512 of file Nano1X2Series.h.

◆ CLKSEL

__IO uint32_t PWM_T::CLKSEL

CLKSEL

Offset: 0x04 PWM Clock Select Register

Bits Field Descriptions
[2:0] CLKSEL0 Timer 0 Clock Source Selection
Select clock input for timer 0.
(Table is the same as CLKSEL3)
[6:4] CLKSEL1 Timer 1 Clock Source Selection
Select clock input for timer 1.
(Table is the same as CLKSEL3)
[10:8] CLKSEL2 Timer 2 Clock Source Selection
Select clock input for timer 2.
(Table is the same as CLKSEL3)
[14:12] CLKSEL3 Timer 3 Clock Source Selection
Select clock input for timer 3.
000 = input clock is divided by 2.
001 = input clock is divided by 4.
010 = input clock is divided by 8.
011 = input clock is divided by 16.
100 = input clock is divided by 1.

Definition at line 5784 of file Nano1X2Series.h.

◆ CRL0

__I uint32_t PWM_T::CRL0

CRL0

Offset: 0x60 Capture Rising Latch Register (Channel 0)

Bits Field Descriptions
[15:0] CRL Capture Rising Latch Register
Latch the PWM counter when Channel 0/1/2/3 has rising transition.
[31:16] CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,

Definition at line 6414 of file Nano1X2Series.h.

◆ CRL1

__I uint32_t PWM_T::CRL1

CRL1

Offset: 0x68 Capture Rising Latch Register (Channel 1)

Bits Field Descriptions
[15:0] CRL Capture Rising Latch Register
Latch the PWM counter when Channel 0/1/2/3 has rising transition.
[31:16] CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,

Definition at line 6442 of file Nano1X2Series.h.

◆ CRL2

__I uint32_t PWM_T::CRL2

CRL2

Offset: 0x70 Capture Rising Latch Register (Channel 2)

Bits Field Descriptions
[15:0] CRL Capture Rising Latch Register
Latch the PWM counter when Channel 0/1/2/3 has rising transition.
[31:16] CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,

Definition at line 6470 of file Nano1X2Series.h.

◆ CRL3

__I uint32_t PWM_T::CRL3

CRL3

Offset: 0x78 Capture Rising Latch Register (Channel 3)

Bits Field Descriptions
[15:0] CRL Capture Rising Latch Register
Latch the PWM counter when Channel 0/1/2/3 has rising transition.
[31:16] CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,

Definition at line 6498 of file Nano1X2Series.h.

◆ CTL

__IO uint32_t PWM_T::CTL

CTL

Offset: 0x08 PWM Control Register

Bits Field Descriptions
[0] CH0EN PWM-Timer 0 Enable/Disable Start Run
0 = PWM-Timer 0 Running Stopped.
1 = PWM-Timer 0 Start Run Enabled.
[2] CH0INV PWM-Timer 0 Output Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON.
[3] CH0MOD PWM-Timer 0 Continuous/One-Shot Mode
0 = One-Shot Mode.
1 = Continuous Mode.
Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared.
[4] DZEN01 Dead-Zone 0 Generator Enable/Disable Control
0 = Disabled.
1 = Enabled.
Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
[5] DZEN23 Dead-Zone 2 Generator Enable/Disable Control
0 = Disabled.
1 = Enabled.
Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair.
[8] CH1EN PWM-Timer 1 Enable/Disable Start Run
0 = PWM-Timer 1 Running Stopped.
1 = PWM-Timer 1 Start Run Enabled.
[10] CH1INV PWM-Timer 1 Output Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON.
[11] CH1MOD PWM-Timer 1 Continuous/One-Shot Mode
0 = One-Shot Mode.
1 = Continuous Mode.
Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared.
[16] CH2EN PWM-Timer 2 Enable/Disable Start Run
0 = PWM-Timer 2 Running Stopped.
1 = PWM-Timer 2 Start Run Enabled.
[18] CH2INV PWM-Timer 2 Output Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON.
[19] CH2MOD PWM-Timer 2 Continuous/One-Shot Mode
0 = One-Shot Mode.
1 = Continuous Mode.
Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared.
[24] CH3EN PWM-Timer 3 Enable/Disable Start Run
0 = PWM-Timer 3 Running Stopped.
1 = PWM-Timer 3 Start Run Enabled.
[26] CH3INV PWM-Timer 3 Output Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON.
[27] CH3MOD PWM-Timer 3 Continuous/One-Shot Mode
0 = One-Shot Mode.
1 = Continuous Mode.
Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared.
[30] PWMTYPE01 Channel 0,1 Counter Mode
0 = Edge-aligned Mode.
1 = Center-aligned Mode.
[31] PWMTYPE23 Channel 2,3 Counter Mode
0 = Edge-aligned Mode.
1 = Center-aligned Mode.

Definition at line 5848 of file Nano1X2Series.h.

◆ DATA0

__I uint32_t PWM_T::DATA0

DATA0

Offset: 0x20 PWM Data Register 0

Bits Field Descriptions
[15:0] DATA PWM Data Register
User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
[30:16] DATA_H PWM Data Register
User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
Notes: This will be valid only for the corresponding cascade enable bit is set
[31] sync CN Value Sync With PWM Counter
0 = CN value is sync to PWM counter.
1 = CN value is not sync to PWM counter.
Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel

Definition at line 5995 of file Nano1X2Series.h.

◆ DATA1

__I uint32_t PWM_T::DATA1

DATA1

Offset: 0x2C PWM Data Register 1

Bits Field Descriptions
[15:0] DATA PWM Data Register
User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
[30:16] DATA_H PWM Data Register
User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
Notes: This will be valid only for the corresponding cascade enable bit is set
[31] sync CN Value Sync With PWM Counter
0 = CN value is sync to PWM counter.
1 = CN value is not sync to PWM counter.
Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel

Definition at line 6060 of file Nano1X2Series.h.

◆ DATA2

__I uint32_t PWM_T::DATA2

DATA2

Offset: 0x38 PWM Data Register 2

Bits Field Descriptions
[15:0] DATA PWM Data Register
User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
[30:16] DATA_H PWM Data Register
User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
Notes: This will be valid only for the corresponding cascade enable bit is set
[31] sync CN Value Sync With PWM Counter
0 = CN value is sync to PWM counter.
1 = CN value is not sync to PWM counter.
Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel

Definition at line 6125 of file Nano1X2Series.h.

◆ DATA3

__I uint32_t PWM_T::DATA3

DATA3

Offset: 0x44 PWM Data Register 3

Bits Field Descriptions
[15:0] DATA PWM Data Register
User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
[30:16] DATA_H PWM Data Register
User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
Notes: This will be valid only for the corresponding cascade enable bit is set
[31] sync CN Value Sync With PWM Counter
0 = CN value is sync to PWM counter.
1 = CN value is not sync to PWM counter.
Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel

Definition at line 6190 of file Nano1X2Series.h.

◆ DUTY0

__IO uint32_t PWM_T::DUTY0

DUTY0

Offset: 0x1C PWM Counter/Comparator Register 0

Bits Field Descriptions
[15:0] CN PWM Counter/Timer Loaded Value
CN determines the PWM period.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note: Any write to CN will take effect in next PWM cycle.
[31:16] CM PWM Comparator Register
CM determines the PWM duty.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note:Any write to CM will take effect in next PWM cycle.

Definition at line 5976 of file Nano1X2Series.h.

◆ DUTY1

__IO uint32_t PWM_T::DUTY1

DUTY1

Offset: 0x28 PWM Counter/Comparator Register 1

Bits Field Descriptions
[15:0] CN PWM Counter/Timer Loaded Value
CN determines the PWM period.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note: Any write to CN will take effect in next PWM cycle.
[31:16] CM PWM Comparator Register
CM determines the PWM duty.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note:Any write to CM will take effect in next PWM cycle.

Definition at line 6041 of file Nano1X2Series.h.

◆ DUTY2

__IO uint32_t PWM_T::DUTY2

DUTY2

Offset: 0x34 PWM Counter/Comparator Register 2

Bits Field Descriptions
[15:0] CN PWM Counter/Timer Loaded Value
CN determines the PWM period.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note: Any write to CN will take effect in next PWM cycle.
[31:16] CM PWM Comparator Register
CM determines the PWM duty.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note:Any write to CM will take effect in next PWM cycle.

Definition at line 6106 of file Nano1X2Series.h.

◆ DUTY3

__IO uint32_t PWM_T::DUTY3

DUTY3

Offset: 0x40 PWM Counter/Comparator Register 3

Bits Field Descriptions
[15:0] CN PWM Counter/Timer Loaded Value
CN determines the PWM period.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note: Any write to CN will take effect in next PWM cycle.
[31:16] CM PWM Comparator Register
CM determines the PWM duty.
In edge-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (CM+1)/(CN+1).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
In center-aligned mode,
PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
Duty ratio = (2xCM+1)/(2x(CN+1)).
CM >= CN: PWM output is always high.
CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
(Unit = one PWM clock cycle).
Note:Any write to CM will take effect in next PWM cycle.

Definition at line 6171 of file Nano1X2Series.h.

◆ INTEN

__IO uint32_t PWM_T::INTEN

INTEN

Offset: 0x0C PWM Interrupt Enable Register

Bits Field Descriptions
[0] TMIE0 PWM Timer 0 Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[1] TMIE1 PWM Timer 1 Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[2] TMIE2 PWM Timer 2 Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[3] TMIE3 PWM Timer 3 Interrupt Enable Control
0 = Disabled.
1 = Enabled.

Definition at line 5870 of file Nano1X2Series.h.

◆ INTSTS

__IO uint32_t PWM_T::INTSTS

INTSTS

Offset: 0x10 PWM Interrupt Indication Register

Bits Field Descriptions
[0] TMINT0 PWM Timer 0 Interrupt Flag
Flag is set by hardware when PWM0 down counter reaches 0, software can clear this bit by writing a one to it.
[1] TMINT1 PWM Timer 1 Interrupt Flag
Flag is set by hardware when PWM1 down counter reaches 0, software can clear this bit by writing a one to it.
[2] TMINT2 PWM Timer 2 Interrupt Flag
Flag is set by hardware when PWM2 down counter reaches 0, software can clear this bit by writing a one to it.
[3] TMINT3 PWM Timer 3 Interrupt Flag
Flag is set by hardware when PWM3 down counter reaches 0, software can clear this bit by writing a one to it.
[4] Duty0Syncflag Duty0 Synchronize Flag
0 = Duty0 has been synchronized to PWM_CLK domain of channel 0, 1.
1 = Duty0 is synchronizing to PWM_CLK domain of channel 0, 1.
Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
[5] Duty1Syncflag Duty1 Synchronize Flag
0 = Duty1 has been synchronized to PWM_CLK domain of channel 0, 1.
1 = Duty1 is synchronizing to PWM_CLK domain of channel 0, 1.
Note: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
[6] Duty2Syncflag Duty2 Synchronize Flag
0 = Duty2 has been synchronized to PWM_CLK domain of channel 2, 3.
1 = Duty2 is synchronizing to PWM_CLK domain of channel 2, 3.
Note: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
[7] Duty3Syncflag Duty3 Synchronize Flag
0 = Duty3 has been synchronized to PWM_CLK domain of channel 2, 3.
1 = Duty3 is synchronizing to PWM_CLK domain of channel 2, 3.
Note: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
[8] PresSyncFlag Prescale Synchronize Flag
0 = Two Prescales have been synchronized to corresponding PWM_CLK (of channel 0,1 or channel 2, 3) domain respectively.
1 = Prescale01 is synchronizing to PWM_CLK domain of channel 0,1 or Prescaler23 is synchronizing to PWM_CLK domain of channel 2, 3.
Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle

Definition at line 5908 of file Nano1X2Series.h.

◆ OE

__IO uint32_t PWM_T::OE

OE

Offset: 0x14 PWM Output Enable for PWM0~PWM3

Bits Field Descriptions
[0] CH0_OE PWM CH0 Output Enable Control
0 = PWM CH0 output to pin Disabled.
1 = PWM CH0 output to pin Enabled.
[1] CH1_OE PWM CH1 Output Enable Control
0 = PWM CH1 output to pin Disabled.
1 = PWM CH1 output to pin Enabled.
[2] CH2_OE PWM CH2 Output Enable Control R
0 = PWM CH2 output to pin Disabled.
1 = PWM CH2 output to pin Enabled.
[3] CH3_OE PWM CH3 Output Enable Control
0 = PWM CH3 output to pin Disabled.
1 = PWM CH3 output to pin Enabled.

Definition at line 5930 of file Nano1X2Series.h.

◆ PDMACH0

__I uint32_t PWM_T::PDMACH0

PDMACH0

Offset: 0x80 PDMA Channel 0 Captured Data

Bits Field Descriptions
[7:0] PDMACH01 Captured Data Of Channel 0 When CH01CASK Is Disabled, It Is The Capturing Value(CFL0/CRL0) For Channel 0
When CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0
[15:8] PDMACH02 Captured Data Of Channel 0
When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0
When CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0
[23:16] PDMACH03 Captured Data Of Channel 0 When CH01CASK Is Disabled, This Byte Is 0
When CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0
[31:24] PDMACH04 Captured Data Of Channel 0
When CH01CASK is disabled, this byte is 0
When CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0

Definition at line 6532 of file Nano1X2Series.h.

◆ PDMACH2

__I uint32_t PWM_T::PDMACH2

PDMACH2

Offset: 0x84 PDMA Channel 2 Captured Data

Bits Field Descriptions
[7:0] PDMACH21 Captured Data Of Channel 2 When CH23CASK Is Disabled, It Is The Capturing Value(CFL2/CRL2) For Channel 2
When CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2
[15:8] PDMACH22 Captured Data Of Channel 2
When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2
When CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2
[23:16] PDMACH23 Captured Data Of Channel 2
When CH23CASK is disabled, this byte is 0
When CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2
[31:24] PDMACH24 Captured Data Of Channel 2
When CH23CASK is disabled, this byte is 0
When CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2

Definition at line 6553 of file Nano1X2Series.h.

◆ PRES

__IO uint32_t PWM_T::PRES

PRES

Offset: 0x00 PWM Prescaler Register

Bits Field Descriptions
[7:0] CP01 Clock Prescaler 0 For PWM Timer 0 & 1
Clock input is divided by (CP01 + 1) before it is fed to the PWM counter 0 & 1
If CP01 =0, the prescaler 0 output clock will be stopped. So PWM counter 0 and 1 will be stopped also.
[15:8] CP23 Clock Prescaler 2 For PWM Timer 2 & 3
Clock input is divided by (CP23 + 1) before it is fed to the PWM counter 2 & 3
If CP23=0, the prescaler 2 output clock will be stopped. So PWM counter 2 and 3 will be stopped also.
[23:16] DZ01 Dead Zone Interval Register For CH0 And CH1 Pair
These 8 bits determine dead zone length.
The unit time of dead zone length is received from clock selector 0.
[31:24] DZ23 Dead Zone Interval Register For CH2 And CH3 Pair
These 8 bits determine dead zone length.
The unit time of dead zone length is received from clock selector 2.

Definition at line 5758 of file Nano1X2Series.h.

◆ RESERVE0

uint32_t PWM_T::RESERVE0[1]

Definition at line 5931 of file Nano1X2Series.h.

◆ RESERVE1

uint32_t PWM_T::RESERVE1[1]

Definition at line 5996 of file Nano1X2Series.h.

◆ RESERVE2

uint32_t PWM_T::RESERVE2[1]

Definition at line 6061 of file Nano1X2Series.h.

◆ RESERVE3

uint32_t PWM_T::RESERVE3[1]

Definition at line 6126 of file Nano1X2Series.h.

◆ RESERVE4

uint32_t PWM_T::RESERVE4[3]

Definition at line 6191 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: