NANO100_BSP V3.04.002
The Board Support Package for Nano100BN Series
NuEdu-Basic01_System.c
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1/**************************************************************************/
12#include <stdio.h>
13#include "Nano100Series.h"
15
16
34/*---------------------------------------------------------------------------------------------------------*/
35/* Init System Clock */
36/*---------------------------------------------------------------------------------------------------------*/
37void SYS_Init(void)
38{
39 /* Unlock protected registers */
41
42 /* Set HCLK source from HXT and HCLK source divide 1 */
44
45 /* Enable external 12MHz HXT, 32KHz LXT and HIRC */
47
48 /* Set HCLK frequency 42MHz */
49 CLK_SetCoreClock(42000000);
50
51 /* Lock protected registers */
53
54}
55
56 /* end of group Nano130_Basic01_FUNCTIONS System Exported Functions */
58 /* end of group NuEdu-SDK-Nano130_Basic01 Nano130_Basic01 Library */
60 /* end of group NANO100_Library NANO100 Library */
62
63/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
NuEdu-Basic01 System driver header file.
#define CLK_CLKSEL0_HCLK_S_HXT
Definition: clk.h:101
#define CLK_HCLK_CLK_DIVIDER(x)
Definition: clk.h:188
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:223
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:369
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz.
Definition: clk.c:177
#define CLK_PWRCTL_LXT_EN_Msk
#define CLK_PWRCTL_HIRC_EN_Msk
#define CLK_PWRCTL_HXT_EN_Msk
__STATIC_INLINE void SYS_LockReg(void)
Enable register write-protection function.
Definition: sys.h:843
__STATIC_INLINE void SYS_UnlockReg(void)
Disable register write-protection function.
Definition: sys.h:826
void SYS_Init(void)
This function enables HXT, LXT and LIRC clock and sets HCLK source from HXT to 42MHz.