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NUC029FAE_BSP V3.01.004
The Board Support Package for NUC029FAE MCU
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Functions that configure the System. More...
Functions that configure the System.
__STATIC_INLINE uint32_t SysTick_Config | ( | uint32_t | ticks | ) |
System Tick Configuration.
Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts.
[in] | ticks | Number of ticks between two interrupts. |
Definition at line 769 of file core_cm0.h.
uint32_t APSR_Type::_reserved0 |
bit: 0..27 Reserved
Definition at line 251 of file core_cm0.h.
uint32_t { ... } ::_reserved0 |
bit: 0..27 Reserved
Definition at line 251 of file core_cm0.h.
uint32_t IPSR_Type::_reserved0 |
bit: 9..31 Reserved
Definition at line 282 of file core_cm0.h.
uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 282 of file core_cm0.h.
uint32_t xPSR_Type::_reserved0 |
bit: 9..23 Reserved
Definition at line 300 of file core_cm0.h.
uint32_t { ... } ::_reserved0 |
bit: 9..23 Reserved
Definition at line 300 of file core_cm0.h.
uint32_t { ... } ::_reserved0 |
bit: 0 Reserved
Definition at line 338 of file core_cm0.h.
uint32_t CONTROL_Type::_reserved0 |
bit: 0 Reserved
Definition at line 338 of file core_cm0.h.
uint32_t xPSR_Type::_reserved1 |
bit: 25..27 Reserved
Definition at line 302 of file core_cm0.h.
uint32_t { ... } ::_reserved1 |
bit: 25..27 Reserved
Definition at line 302 of file core_cm0.h.
uint32_t CONTROL_Type::_reserved1 |
bit: 2..31 Reserved
Definition at line 340 of file core_cm0.h.
uint32_t { ... } ::_reserved1 |
bit: 2..31 Reserved
Definition at line 340 of file core_cm0.h.
__IOM uint32_t SCB_Type::AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 394 of file core_cm0.h.
struct { ... } APSR_Type::b |
Structure used for bit access
struct { ... } IPSR_Type::b |
Structure used for bit access
struct { ... } xPSR_Type::b |
Structure used for bit access
struct { ... } CONTROL_Type::b |
Structure used for bit access
uint32_t APSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 253 of file core_cm0.h.
uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 253 of file core_cm0.h.
uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 304 of file core_cm0.h.
uint32_t xPSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 304 of file core_cm0.h.
__IM uint32_t SysTick_Type::CALIB |
Offset: 0x00C (R/ ) SysTick Calibration Register
Definition at line 501 of file core_cm0.h.
__IOM uint32_t SCB_Type::CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 396 of file core_cm0.h.
__IM uint32_t SCB_Type::CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 391 of file core_cm0.h.
__IOM uint32_t SysTick_Type::CTRL |
Offset: 0x000 (R/W) SysTick Control and Status Register
Definition at line 498 of file core_cm0.h.
__IOM uint32_t NVIC_Type::ICER[1U] |
Offset: 0x080 (R/W) Interrupt Clear Enable Register
Definition at line 366 of file core_cm0.h.
__IOM uint32_t NVIC_Type::ICPR[1U] |
Offset: 0x180 (R/W) Interrupt Clear Pending Register
Definition at line 370 of file core_cm0.h.
__IOM uint32_t SCB_Type::ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 392 of file core_cm0.h.
__IOM uint32_t NVIC_Type::IP[8U] |
Offset: 0x300 (R/W) Interrupt Priority Register
Definition at line 373 of file core_cm0.h.
__IOM uint32_t NVIC_Type::ISER[1U] |
Offset: 0x000 (R/W) Interrupt Set Enable Register
Definition at line 364 of file core_cm0.h.
__IOM uint32_t NVIC_Type::ISPR[1U] |
Offset: 0x100 (R/W) Interrupt Set Pending Register
Definition at line 368 of file core_cm0.h.
uint32_t IPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 281 of file core_cm0.h.
uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 281 of file core_cm0.h.
uint32_t xPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 299 of file core_cm0.h.
uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 299 of file core_cm0.h.
__IOM uint32_t SysTick_Type::LOAD |
Offset: 0x004 (R/W) SysTick Reload Value Register
Definition at line 499 of file core_cm0.h.
uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 255 of file core_cm0.h.
uint32_t APSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 255 of file core_cm0.h.
uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 306 of file core_cm0.h.
uint32_t xPSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 306 of file core_cm0.h.
uint32_t NVIC_Type::RESERVED0[31U] |
Definition at line 365 of file core_cm0.h.
uint32_t SCB_Type::RESERVED0 |
Definition at line 393 of file core_cm0.h.
uint32_t SCB_Type::RESERVED1 |
Definition at line 397 of file core_cm0.h.
uint32_t NVIC_Type::RESERVED2[31U] |
Definition at line 369 of file core_cm0.h.
uint32_t NVIC_Type::RESERVED3[31U] |
Definition at line 371 of file core_cm0.h.
uint32_t NVIC_Type::RESERVED4[64U] |
Definition at line 372 of file core_cm0.h.
uint32_t NVIC_Type::RSERVED1[31U] |
Definition at line 367 of file core_cm0.h.
__IOM uint32_t SCB_Type::SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 395 of file core_cm0.h.
__IOM uint32_t SCB_Type::SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 399 of file core_cm0.h.
__IOM uint32_t SCB_Type::SHP[2U] |
Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED
Definition at line 398 of file core_cm0.h.
uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 339 of file core_cm0.h.
uint32_t CONTROL_Type::SPSEL |
bit: 1 Stack to be used
Definition at line 339 of file core_cm0.h.
uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 301 of file core_cm0.h.
uint32_t xPSR_Type::T |
bit: 24 Thumb bit (read 0)
Definition at line 301 of file core_cm0.h.
uint32_t APSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 252 of file core_cm0.h.
uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 252 of file core_cm0.h.
uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 303 of file core_cm0.h.
uint32_t xPSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 303 of file core_cm0.h.
__IOM uint32_t SysTick_Type::VAL |
Offset: 0x008 (R/W) SysTick Current Value Register
Definition at line 500 of file core_cm0.h.
uint32_t APSR_Type::w |
Type used for word access
Definition at line 257 of file core_cm0.h.
uint32_t IPSR_Type::w |
Type used for word access
Definition at line 284 of file core_cm0.h.
uint32_t xPSR_Type::w |
Type used for word access
Definition at line 308 of file core_cm0.h.
uint32_t CONTROL_Type::w |
Type used for word access
Definition at line 342 of file core_cm0.h.
uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 254 of file core_cm0.h.
uint32_t APSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 254 of file core_cm0.h.
uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 305 of file core_cm0.h.
uint32_t xPSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 305 of file core_cm0.h.