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NUC029FAE_BSP V3.01.004
The Board Support Package for NUC029FAE MCU
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Modules | |
CLK Exported Functions | |
Macros | |
#define | CLK_PWRCON_XTL12M 0x01UL |
#define | CLK_PWRCON_HXT 0x01UL |
#define | CLK_PWRCON_XTL32K 0x02UL |
#define | CLK_PWRCON_LXT 0x02UL |
#define | CLK_CLKSEL0_HCLK_S_XTAL 0x00UL |
#define | CLK_CLKSEL0_HCLK_S_IRC10K 0x03UL |
#define | CLK_CLKSEL0_HCLK_S_LIRC 0x03UL |
#define | CLK_CLKSEL0_HCLK_S_IRC22M 0x07UL |
#define | CLK_CLKSEL0_HCLK_S_HIRC 0x07UL |
#define | CLK_CLKSEL0_STCLK_S_XTAL 0x00UL |
#define | CLK_CLKSEL0_STCLK_S_XTAL_DIV2 0x10UL |
#define | CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL |
#define | CLK_CLKSEL0_STCLK_S_IRC22M_DIV2 0x38UL |
#define | CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL |
#define | CLK_CLKSEL1_WDT_S_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL |
#define | CLK_CLKSEL1_WDT_S_IRC10K 0x00000003UL |
#define | CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL |
#define | CLK_CLKSEL1_ADC_S_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL |
#define | CLK_CLKSEL1_ADC_S_IRC22M 0x0000000CUL |
#define | CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL |
#define | CLK_CLKSEL1_SPI_S_HXTorLXT 0x00000000UL |
#define | CLK_CLKSEL1_SPI_S_HCLK 0x00000010UL |
#define | CLK_CLKSEL1_TMR0_S_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_TMR0_S_IRC10K 0x00000100UL |
#define | CLK_CLKSEL1_TMR0_S_LIRC 0x00000100UL |
#define | CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL |
#define | CLK_CLKSEL1_TMR0_S_IRC22M 0x00000700UL |
#define | CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL |
#define | CLK_CLKSEL1_TMR1_S_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_TMR1_S_IRC10K 0x00001000UL |
#define | CLK_CLKSEL1_TMR1_S_LIRC 0x00001000UL |
#define | CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL |
#define | CLK_CLKSEL1_TMR1_S_IRC22M 0x00007000UL |
#define | CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL |
#define | CLK_CLKSEL1_UART_S_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_UART_S_IRC22M 0x02000000UL |
#define | CLK_CLKSEL1_UART_S_HIRC 0x02000000UL |
#define | CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL |
#define | CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL |
#define | CLK_CLKSEL2_FRQDIV_XTAL 0x00000000UL |
#define | CLK_CLKSEL2_FRQDIV_HXT 0x00000000UL |
#define | CLK_CLKSEL2_FRQDIV_LXT 0x00000000UL |
#define | CLK_CLKSEL2_FRQDIV_HCLK 0x00000008UL |
#define | CLK_CLKSEL2_FRQDIV_IRC22M 0x0000000CUL |
#define | CLK_CLKSEL2_FRQDIV_HIRC 0x0000000CUL |
#define | CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL |
#define | CLK_CLKDIV_ADC(x) (((x)-1) << 16) |
#define | CLK_CLKDIV_UART(x) (((x)-1) << 8) |
#define | CLK_CLKDIV_HCLK(x) ((x)-1) |
#define | MODULE_APBCLK(x) ((x >>31) & 0x1) |
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3) |
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) |
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) |
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3) |
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) |
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) |
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) |
#define | MODULE_NoMsk 0x0 |
#define | WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDT_EN_Pos ) |
#define | TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0_EN_Pos) |
#define | TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1_EN_Pos) |
#define | FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_FDIV_EN_Pos) |
#define | I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2C_EN_Pos) |
#define | SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPI_EN_Pos) |
#define | UART_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART_EN_Pos) |
#define | PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM01_EN_Pos) |
#define | PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM23_EN_Pos) |
#define | PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM45_EN_Pos) |
#define | ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos) |
#define | ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMP_EN_Pos) |
#define ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMP_EN_Pos) |
#define ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos) |
#define CLK_CLKDIV_ADC | ( | x | ) | (((x)-1) << 16) |
#define CLK_CLKDIV_HCLK | ( | x | ) | ((x)-1) |
#define CLK_CLKDIV_UART | ( | x | ) | (((x)-1) << 8) |
#define CLK_CLKSEL0_HCLK_S_HIRC 0x07UL |
#define CLK_CLKSEL0_HCLK_S_IRC10K 0x03UL |
#define CLK_CLKSEL0_HCLK_S_IRC22M 0x07UL |
#define CLK_CLKSEL0_HCLK_S_LIRC 0x03UL |
#define CLK_CLKSEL0_HCLK_S_XTAL 0x00UL |
#define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL |
#define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL |
#define CLK_CLKSEL0_STCLK_S_IRC22M_DIV2 0x38UL |
#define CLK_CLKSEL0_STCLK_S_XTAL 0x00UL |
#define CLK_CLKSEL0_STCLK_S_XTAL_DIV2 0x10UL |
#define CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL |
#define CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL |
#define CLK_CLKSEL1_ADC_S_IRC22M 0x0000000CUL |
#define CLK_CLKSEL1_ADC_S_XTAL 0x00000000UL |
#define CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL |
#define CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL |
#define CLK_CLKSEL1_SPI_S_HCLK 0x00000010UL |
#define CLK_CLKSEL1_SPI_S_HXTorLXT 0x00000000UL |
#define CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL |
#define CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL |
#define CLK_CLKSEL1_TMR0_S_IRC10K 0x00000100UL |
#define CLK_CLKSEL1_TMR0_S_IRC22M 0x00000700UL |
#define CLK_CLKSEL1_TMR0_S_LIRC 0x00000100UL |
#define CLK_CLKSEL1_TMR0_S_XTAL 0x00000000UL |
#define CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL |
#define CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL |
#define CLK_CLKSEL1_TMR1_S_IRC10K 0x00001000UL |
#define CLK_CLKSEL1_TMR1_S_IRC22M 0x00007000UL |
#define CLK_CLKSEL1_TMR1_S_LIRC 0x00001000UL |
#define CLK_CLKSEL1_TMR1_S_XTAL 0x00000000UL |
#define CLK_CLKSEL1_UART_S_HIRC 0x02000000UL |
#define CLK_CLKSEL1_UART_S_IRC22M 0x02000000UL |
#define CLK_CLKSEL1_UART_S_XTAL 0x00000000UL |
#define CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL |
#define CLK_CLKSEL1_WDT_S_IRC10K 0x00000003UL |
#define CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL |
#define CLK_CLKSEL1_WDT_S_XTAL 0x00000000UL |
#define CLK_CLKSEL2_FRQDIV_HCLK 0x00000008UL |
#define CLK_CLKSEL2_FRQDIV_HIRC 0x0000000CUL |
#define CLK_CLKSEL2_FRQDIV_HXT 0x00000000UL |
#define CLK_CLKSEL2_FRQDIV_IRC22M 0x0000000CUL |
#define CLK_CLKSEL2_FRQDIV_LXT 0x00000000UL |
#define CLK_CLKSEL2_FRQDIV_XTAL 0x00000000UL |
#define CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL |
#define CLK_PWRCON_HXT 0x01UL |
#define CLK_PWRCON_LXT 0x02UL |
#define CLK_PWRCON_XTL12M 0x01UL |
#define CLK_PWRCON_XTL32K 0x02UL |
#define FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_FDIV_EN_Pos) |
#define I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2C_EN_Pos) |
#define MODULE_APBCLK | ( | x | ) | ((x >>31) & 0x1) |
#define MODULE_CLKDIV | ( | x | ) | ((x >>18) & 0x3) |
#define MODULE_CLKDIV_Msk | ( | x | ) | ((x >>10) & 0xff) |
#define MODULE_CLKDIV_Pos | ( | x | ) | ((x >>5 ) & 0x1f) |
#define MODULE_CLKSEL | ( | x | ) | ((x >>29) & 0x3) |
#define MODULE_CLKSEL_Msk | ( | x | ) | ((x >>25) & 0xf) |
#define MODULE_CLKSEL_Pos | ( | x | ) | ((x >>20) & 0x1f) |
#define MODULE_IP_EN_Pos | ( | x | ) | ((x >>0 ) & 0x1f) |
#define PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM01_EN_Pos) |
#define PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM23_EN_Pos) |
#define PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM45_EN_Pos) |
#define SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPI_EN_Pos) |
#define TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0_EN_Pos) |
#define TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1_EN_Pos) |
#define UART_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART_EN_Pos) |
#define WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDT_EN_Pos ) |