MINI58_BSP V3.01.005
The Board Support Package for Mini58 Series MCU
Macros | Enumerator | Variables
Collaboration diagram for Mini58 Legacy Constants:

Macros

#define NULL   (0)
 NULL pointer. More...
 
#define TRUE   (1)
 Boolean true, define to use in API parameters or return value. More...
 
#define FALSE   (0)
 Boolean false, define to use in API parameters or return value. More...
 
#define ENABLE   (1)
 Enable, define to use in API parameters. More...
 
#define DISABLE   (0)
 Disable, define to use in API parameters. More...
 
#define BIT0   (0x00000001)
 Bit 0 mask of an 32 bit integer. More...
 
#define BIT1   (0x00000002)
 Bit 1 mask of an 32 bit integer. More...
 
#define BIT2   (0x00000004)
 Bit 2 mask of an 32 bit integer. More...
 
#define BIT3   (0x00000008)
 Bit 3 mask of an 32 bit integer. More...
 
#define BIT4   (0x00000010)
 Bit 4 mask of an 32 bit integer. More...
 
#define BIT5   (0x00000020)
 Bit 5 mask of an 32 bit integer. More...
 
#define BIT6   (0x00000040)
 Bit 6 mask of an 32 bit integer. More...
 
#define BIT7   (0x00000080)
 Bit 7 mask of an 32 bit integer. More...
 
#define BIT8   (0x00000100)
 Bit 8 mask of an 32 bit integer. More...
 
#define BIT9   (0x00000200)
 Bit 9 mask of an 32 bit integer. More...
 
#define BIT10   (0x00000400)
 Bit 10 mask of an 32 bit integer. More...
 
#define BIT11   (0x00000800)
 Bit 11 mask of an 32 bit integer. More...
 
#define BIT12   (0x00001000)
 Bit 12 mask of an 32 bit integer. More...
 
#define BIT13   (0x00002000)
 Bit 13 mask of an 32 bit integer. More...
 
#define BIT14   (0x00004000)
 Bit 14 mask of an 32 bit integer. More...
 
#define BIT15   (0x00008000)
 Bit 15 mask of an 32 bit integer. More...
 
#define BIT16   (0x00010000)
 Bit 16 mask of an 32 bit integer. More...
 
#define BIT17   (0x00020000)
 Bit 17 mask of an 32 bit integer. More...
 
#define BIT18   (0x00040000)
 Bit 18 mask of an 32 bit integer. More...
 
#define BIT19   (0x00080000)
 Bit 19 mask of an 32 bit integer. More...
 
#define BIT20   (0x00100000)
 Bit 20 mask of an 32 bit integer. More...
 
#define BIT21   (0x00200000)
 Bit 21 mask of an 32 bit integer. More...
 
#define BIT22   (0x00400000)
 Bit 22 mask of an 32 bit integer. More...
 
#define BIT23   (0x00800000)
 Bit 23 mask of an 32 bit integer. More...
 
#define BIT24   (0x01000000)
 Bit 24 mask of an 32 bit integer. More...
 
#define BIT25   (0x02000000)
 Bit 25 mask of an 32 bit integer. More...
 
#define BIT26   (0x04000000)
 Bit 26 mask of an 32 bit integer. More...
 
#define BIT27   (0x08000000)
 Bit 27 mask of an 32 bit integer. More...
 
#define BIT28   (0x10000000)
 Bit 28 mask of an 32 bit integer. More...
 
#define BIT29   (0x20000000)
 Bit 29 mask of an 32 bit integer. More...
 
#define BIT30   (0x40000000)
 Bit 30 mask of an 32 bit integer. More...
 
#define BIT31   (0x80000000)
 Bit 31 mask of an 32 bit integer. More...
 
#define BYTE0_Msk   (0x000000FF)
 Mask to get bit0~bit7 from a 32 bit integer. More...
 
#define BYTE1_Msk   (0x0000FF00)
 Mask to get bit8~bit15 from a 32 bit integer. More...
 
#define BYTE2_Msk   (0x00FF0000)
 Mask to get bit16~bit23 from a 32 bit integer. More...
 
#define BYTE3_Msk   (0xFF000000)
 Mask to get bit24~bit31 from a 32 bit integer. More...
 
#define GET_BYTE0(u32Param)   ((u32Param & BYTE0_Msk) )
 
#define GET_BYTE1(u32Param)   ((u32Param & BYTE1_Msk) >> 8)
 
#define GET_BYTE2(u32Param)   ((u32Param & BYTE2_Msk) >> 16)
 
#define GET_BYTE3(u32Param)   ((u32Param & BYTE3_Msk) >> 24)
 

Variables

__IO uint32_t ACMP_T::CTL [2]
 
__IO uint32_t ACMP_T::STATUS
 
__IO uint32_t ACMP_T::VREF
 
__I uint32_t ADC_T::DAT
 
__IO uint32_t ADC_T::CTL
 
__IO uint32_t ADC_T::CHEN
 
__IO uint32_t ADC_T::CMP0
 
__IO uint32_t ADC_T::CMP1
 
__IO uint32_t ADC_T::STATUS
 
__IO uint32_t ADC_T::TRGDLY
 
__IO uint32_t ADC_T::EXTSMPT
 
__IO uint32_t ADC_T::SEQCTL
 
__I uint32_t ADC_T::SEQDAT1
 
__I uint32_t ADC_T::SEQDAT2
 
__IO uint32_t CLK_T::PWRCTL
 
__IO uint32_t CLK_T::AHBCLK
 
__IO uint32_t CLK_T::APBCLK
 
__IO uint32_t CLK_T::STATUS
 
__IO uint32_t CLK_T::CLKSEL0
 
__IO uint32_t CLK_T::CLKSEL1
 
__IO uint32_t CLK_T::CLKDIV
 
__IO uint32_t CLK_T::CLKSEL2
 
__IO uint32_t CLK_T::PLLCTL
 
__IO uint32_t CLK_T::CLKOCTL
 
__IO uint32_t FMC_T::ISPCTL
 
__IO uint32_t FMC_T::ISPADDR
 
__IO uint32_t FMC_T::ISPDAT
 
__IO uint32_t FMC_T::ISPCMD
 
__IO uint32_t FMC_T::ISPTRG
 
__I uint32_t FMC_T::DFBA
 
__IO uint32_t FMC_T::FATCTL
 
__I uint32_t FMC_T::ISPSTS
 
__IO uint32_t GPIO_T::MODE
 
__IO uint32_t GPIO_T::DINOFF
 
__IO uint32_t GPIO_T::DOUT
 
__IO uint32_t GPIO_T::DATMSK
 
__I uint32_t GPIO_T::PIN
 
__IO uint32_t GPIO_T::DBEN
 
__IO uint32_t GPIO_T::INTTYPE
 
__IO uint32_t GPIO_T::INTEN
 
__IO uint32_t GPIO_T::INTSRC
 
__IO uint32_t GPIO_DB_T::DBCTL
 
__IO uint32_t I2C_T::CTL
 
__IO uint32_t I2C_T::ADDR0
 
__IO uint32_t I2C_T::DAT
 
__I uint32_t I2C_T::STATUS
 
__IO uint32_t I2C_T::CLKDIV
 
__IO uint32_t I2C_T::TOCTL
 
__IO uint32_t I2C_T::ADDR1
 
__IO uint32_t I2C_T::ADDR2
 
__IO uint32_t I2C_T::ADDR3
 
__IO uint32_t I2C_T::ADDRMSK0
 
__IO uint32_t I2C_T::ADDRMSK1
 
__IO uint32_t I2C_T::ADDRMSK2
 
__IO uint32_t I2C_T::ADDRMSK3
 
__IO uint32_t I2C_T::CTL1
 
__IO uint32_t I2C_T::STATUS1
 
__I uint32_t INTR_T::IRQ0_SRC
 
__I uint32_t INTR_T::IRQ1_SRC
 
__I uint32_t INTR_T::IRQ2_SRC
 
__I uint32_t INTR_T::IRQ3_SRC
 
__I uint32_t INTR_T::IRQ4_SRC
 
__I uint32_t INTR_T::IRQ5_SRC
 
__I uint32_t INTR_T::IRQ6_SRC
 
__I uint32_t INTR_T::IRQ7_SRC
 
__I uint32_t INTR_T::IRQ8_SRC
 
__I uint32_t INTR_T::IRQ9_SRC
 
__I uint32_t INTR_T::IRQ12_SRC
 
__I uint32_t INTR_T::IRQ13_SRC
 
__I uint32_t INTR_T::IRQ14_SRC
 
__I uint32_t INTR_T::IRQ16_SRC
 
__I uint32_t INTR_T::IRQ17_SRC
 
__I uint32_t INTR_T::IRQ18_SRC
 
__I uint32_t INTR_T::IRQ19_SRC
 
__I uint32_t INTR_T::IRQ25_SRC
 
__I uint32_t INTR_T::IRQ28_SRC
 
__I uint32_t INTR_T::IRQ29_SRC
 
__IO uint32_t INTR_T::CON
 
__IO uint32_t INTR_T::IRQ
 
__IO uint32_t PWM_T::CLKPSC
 
__IO uint32_t PWM_T::CLKDIV
 
__IO uint32_t PWM_T::CTL
 
__IO uint32_t PWM_T::PERIOD0
 
__IO uint32_t PWM_T::PERIOD1
 
__IO uint32_t PWM_T::PERIOD2
 
__IO uint32_t PWM_T::PERIOD3
 
__IO uint32_t PWM_T::PERIOD4
 
__IO uint32_t PWM_T::PERIOD5
 
__IO uint32_t PWM_T::CMPDAT0
 
__IO uint32_t PWM_T::CMPDAT1
 
__IO uint32_t PWM_T::CMPDAT2
 
__IO uint32_t PWM_T::CMPDAT3
 
__IO uint32_t PWM_T::CMPDAT4
 
__IO uint32_t PWM_T::CMPDAT5
 
__IO uint32_t PWM_T::INTEN
 
__IO uint32_t PWM_T::INTSTS
 
__IO uint32_t PWM_T::POEN
 
__IO uint32_t PWM_T::BRKCTL
 
__IO uint32_t PWM_T::DTCTL
 
__IO uint32_t PWM_T::ADCTCTL0
 
__IO uint32_t PWM_T::ADCTCTL1
 
__IO uint32_t PWM_T::ADCTSTS0
 
__IO uint32_t PWM_T::ADCTSTS1
 
__IO uint32_t PWM_T::PHCHG
 
__IO uint32_t PWM_T::PHCHGNXT
 
__IO uint32_t PWM_T::PHCHGMSK
 
__IO uint32_t PWM_T::IFA
 
__IO uint32_t PWM_T::PCACTL
 
__IO uint32_t PWM_T::MSKALIGN
 
__IO uint32_t SPI_T::CTL
 
__IO uint32_t SPI_T::CLKDIV
 
__IO uint32_t SPI_T::SSCTL
 
__I uint32_t SPI_T::RX
 
__O uint32_t SPI_T::TX
 
__IO uint32_t SPI_T::SLVCTL
 
__IO uint32_t SPI_T::FIFOCTL
 
__IO uint32_t SPI_T::STATUS
 
__I uint32_t SYS_T::PDID
 
__IO uint32_t SYS_T::RSTSTS
 
__IO uint32_t SYS_T::IPRST0
 
__IO uint32_t SYS_T::IPRST1
 
__IO uint32_t SYS_T::BODCTL
 
__IO uint32_t SYS_T::P0_MFP
 
__IO uint32_t SYS_T::P1_MFP
 
__IO uint32_t SYS_T::P2_MFP
 
__IO uint32_t SYS_T::P3_MFP
 
__IO uint32_t SYS_T::P4_MFP
 
__IO uint32_t SYS_T::P5_MFP
 
__IO uint32_t SYS_T::IRCTCTL
 
__IO uint32_t SYS_T::IRCTIEN
 
__IO uint32_t SYS_T::IRCTISTS
 
__O uint32_t SYS_T::REGLCTL
 
__IO uint32_t TIMER_T::CTL
 
__IO uint32_t TIMER_T::CMP
 
__IO uint32_t TIMER_T::INTSTS
 
__I uint32_t TIMER_T::CNT
 
__I uint32_t TIMER_T::CAP
 
__IO uint32_t TIMER_T::EXTCTL
 
__IO uint32_t TIMER_T::EINTSTS
 
__IO uint32_t UART_T::DAT
 
__IO uint32_t UART_T::INTEN
 
__IO uint32_t UART_T::FIFO
 
__IO uint32_t UART_T::LINE
 
__IO uint32_t UART_T::MODEM
 
__IO uint32_t UART_T::MODEMSTS
 
__IO uint32_t UART_T::FIFOSTS
 
__IO uint32_t UART_T::INTSTS
 
__IO uint32_t UART_T::TOUT
 
__IO uint32_t UART_T::BAUD
 
__IO uint32_t UART_T::IRDA
 
__IO uint32_t UART_T::ALTCTL
 
__IO uint32_t UART_T::FUNSEL
 
__IO uint32_t WDT_T::CTL
 
__IO uint32_t WDT_T::ALTCTL
 
__O uint32_t WWDT_T::RLDCNT
 
__IO uint32_t WWDT_T::CTL
 
__IO uint32_t WWDT_T::STATUS
 
__I uint32_t WWDT_T::CNT
 

Detailed Description

Mini58 Legacy Constants

Macro Definition Documentation

◆ BIT0

#define BIT0   (0x00000001)

Bit 0 mask of an 32 bit integer.

Definition at line 11896 of file Mini58Series.h.

◆ BIT1

#define BIT1   (0x00000002)

Bit 1 mask of an 32 bit integer.

Definition at line 11897 of file Mini58Series.h.

◆ BIT10

#define BIT10   (0x00000400)

Bit 10 mask of an 32 bit integer.

Definition at line 11906 of file Mini58Series.h.

◆ BIT11

#define BIT11   (0x00000800)

Bit 11 mask of an 32 bit integer.

Definition at line 11907 of file Mini58Series.h.

◆ BIT12

#define BIT12   (0x00001000)

Bit 12 mask of an 32 bit integer.

Definition at line 11908 of file Mini58Series.h.

◆ BIT13

#define BIT13   (0x00002000)

Bit 13 mask of an 32 bit integer.

Definition at line 11909 of file Mini58Series.h.

◆ BIT14

#define BIT14   (0x00004000)

Bit 14 mask of an 32 bit integer.

Definition at line 11910 of file Mini58Series.h.

◆ BIT15

#define BIT15   (0x00008000)

Bit 15 mask of an 32 bit integer.

Definition at line 11911 of file Mini58Series.h.

◆ BIT16

#define BIT16   (0x00010000)

Bit 16 mask of an 32 bit integer.

Definition at line 11912 of file Mini58Series.h.

◆ BIT17

#define BIT17   (0x00020000)

Bit 17 mask of an 32 bit integer.

Definition at line 11913 of file Mini58Series.h.

◆ BIT18

#define BIT18   (0x00040000)

Bit 18 mask of an 32 bit integer.

Definition at line 11914 of file Mini58Series.h.

◆ BIT19

#define BIT19   (0x00080000)

Bit 19 mask of an 32 bit integer.

Definition at line 11915 of file Mini58Series.h.

◆ BIT2

#define BIT2   (0x00000004)

Bit 2 mask of an 32 bit integer.

Definition at line 11898 of file Mini58Series.h.

◆ BIT20

#define BIT20   (0x00100000)

Bit 20 mask of an 32 bit integer.

Definition at line 11916 of file Mini58Series.h.

◆ BIT21

#define BIT21   (0x00200000)

Bit 21 mask of an 32 bit integer.

Definition at line 11917 of file Mini58Series.h.

◆ BIT22

#define BIT22   (0x00400000)

Bit 22 mask of an 32 bit integer.

Definition at line 11918 of file Mini58Series.h.

◆ BIT23

#define BIT23   (0x00800000)

Bit 23 mask of an 32 bit integer.

Definition at line 11919 of file Mini58Series.h.

◆ BIT24

#define BIT24   (0x01000000)

Bit 24 mask of an 32 bit integer.

Definition at line 11920 of file Mini58Series.h.

◆ BIT25

#define BIT25   (0x02000000)

Bit 25 mask of an 32 bit integer.

Definition at line 11921 of file Mini58Series.h.

◆ BIT26

#define BIT26   (0x04000000)

Bit 26 mask of an 32 bit integer.

Definition at line 11922 of file Mini58Series.h.

◆ BIT27

#define BIT27   (0x08000000)

Bit 27 mask of an 32 bit integer.

Definition at line 11923 of file Mini58Series.h.

◆ BIT28

#define BIT28   (0x10000000)

Bit 28 mask of an 32 bit integer.

Definition at line 11924 of file Mini58Series.h.

◆ BIT29

#define BIT29   (0x20000000)

Bit 29 mask of an 32 bit integer.

Definition at line 11925 of file Mini58Series.h.

◆ BIT3

#define BIT3   (0x00000008)

Bit 3 mask of an 32 bit integer.

Definition at line 11899 of file Mini58Series.h.

◆ BIT30

#define BIT30   (0x40000000)

Bit 30 mask of an 32 bit integer.

Definition at line 11926 of file Mini58Series.h.

◆ BIT31

#define BIT31   (0x80000000)

Bit 31 mask of an 32 bit integer.

Definition at line 11927 of file Mini58Series.h.

◆ BIT4

#define BIT4   (0x00000010)

Bit 4 mask of an 32 bit integer.

Definition at line 11900 of file Mini58Series.h.

◆ BIT5

#define BIT5   (0x00000020)

Bit 5 mask of an 32 bit integer.

Definition at line 11901 of file Mini58Series.h.

◆ BIT6

#define BIT6   (0x00000040)

Bit 6 mask of an 32 bit integer.

Definition at line 11902 of file Mini58Series.h.

◆ BIT7

#define BIT7   (0x00000080)

Bit 7 mask of an 32 bit integer.

Definition at line 11903 of file Mini58Series.h.

◆ BIT8

#define BIT8   (0x00000100)

Bit 8 mask of an 32 bit integer.

Definition at line 11904 of file Mini58Series.h.

◆ BIT9

#define BIT9   (0x00000200)

Bit 9 mask of an 32 bit integer.

Definition at line 11905 of file Mini58Series.h.

◆ BYTE0_Msk

#define BYTE0_Msk   (0x000000FF)

Mask to get bit0~bit7 from a 32 bit integer.

Definition at line 11930 of file Mini58Series.h.

◆ BYTE1_Msk

#define BYTE1_Msk   (0x0000FF00)

Mask to get bit8~bit15 from a 32 bit integer.

Definition at line 11931 of file Mini58Series.h.

◆ BYTE2_Msk

#define BYTE2_Msk   (0x00FF0000)

Mask to get bit16~bit23 from a 32 bit integer.

Definition at line 11932 of file Mini58Series.h.

◆ BYTE3_Msk

#define BYTE3_Msk   (0xFF000000)

Mask to get bit24~bit31 from a 32 bit integer.

Definition at line 11933 of file Mini58Series.h.

◆ DISABLE

#define DISABLE   (0)

Disable, define to use in API parameters.

Definition at line 11893 of file Mini58Series.h.

◆ ENABLE

#define ENABLE   (1)

Enable, define to use in API parameters.

Definition at line 11892 of file Mini58Series.h.

◆ FALSE

#define FALSE   (0)

Boolean false, define to use in API parameters or return value.

Definition at line 11890 of file Mini58Series.h.

◆ GET_BYTE0

#define GET_BYTE0 (   u32Param)    ((u32Param & BYTE0_Msk) )

Extract Byte 0 (Bit 0~ 7) from parameter u32Param

Definition at line 11935 of file Mini58Series.h.

◆ GET_BYTE1

#define GET_BYTE1 (   u32Param)    ((u32Param & BYTE1_Msk) >> 8)

Extract Byte 1 (Bit 8~15) from parameter u32Param

Definition at line 11936 of file Mini58Series.h.

◆ GET_BYTE2

#define GET_BYTE2 (   u32Param)    ((u32Param & BYTE2_Msk) >> 16)

Extract Byte 2 (Bit 16~23) from parameter u32Param

Definition at line 11937 of file Mini58Series.h.

◆ GET_BYTE3

#define GET_BYTE3 (   u32Param)    ((u32Param & BYTE3_Msk) >> 24)

Extract Byte 3 (Bit 24~31) from parameter u32Param

Definition at line 11938 of file Mini58Series.h.

◆ NULL

#define NULL   (0)

NULL pointer.

Definition at line 11886 of file Mini58Series.h.

◆ TRUE

#define TRUE   (1)

Boolean true, define to use in API parameters or return value.

Definition at line 11889 of file Mini58Series.h.

Variable Documentation

◆ ADCTCTL0

__IO uint32_t PWM_T::ADCTCTL0

ADCTCTL0

Offset: 0x68 PWM Trigger Control Register 0

Bits Field Descriptions
[0] CUTRGEN0 Channel 0 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel0's counter matching CMP0 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[1] CPTRGEN0 Channel 0 Center Point Trigger ADC Enable Bit
Enable PWM Trigger ADC Function While channel0's Counter Matching PERIOD0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[2] CDTRGEN0 Channel 0 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel0's counter matching CMP0 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[3] ZPTRGEN0 Channel 0 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel0's counter matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[8] CUTRGEN1 Channel 1 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel1's counter matching CMP1 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[9] CPTRGEN1 Channel 1 Center Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel1's counter matching PERIOD1
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[10] CDTRGEN1 Channel 1 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel1's counter matching CMP1 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[11] ZPTRGEN1 Channel 1 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function While channel1's Counter Matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[16] CUTRGEN2 Channel 2 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel2's counter matching CMP2 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[17] CPTRGEN2 Channel 2 Center Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel2's counter matching PERIOD2
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[18] CDTRGEN2 Channel 2 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel2's counter matching CMP2 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[19] ZPTRGEN2 Channel 2 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel2's counter matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[24] CUTRGEN3 Channel 3 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel3's counter matching CMP3 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
[25] CPTRGEN3 Channel 3 Center Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel3's counter matching PERIOD3
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
[26] CDTRGEN3 Channel 3 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel3's counter matching CMP3 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged aligned type.
[27] ZPTRGEN3 Channel 3 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel3's counter matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged aligned type.

Definition at line 7373 of file Mini58Series.h.

◆ ADCTCTL1

__IO uint32_t PWM_T::ADCTCTL1

ADCTCTL1

Offset: 0x6C PWM Trigger Control Register 1

Bits Field Descriptions
[0] CUTRGEN4 Channel 4 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel4's counter matching CMP4 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[1] CPTRGEN4 Channel 4 Center Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel4's counter matching PERIOD4
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[2] CDTRGEN4 Channel 4 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel4's counter matching CMP4 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[3] ZPTRGEN4 Channel 4 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel4's counter matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[8] CUTRGEN5 Channel 5 Compare Up Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel5's counter matching CMP5 in up-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[9] CPTRGEN5 Channel 5 Center Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel5's counter matching PERIOD5
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is only valid for PWM in center-aligned type.
When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
[10] CDTRGEN5 Channel 5 Compare Down Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel5's counter matching CMP5 in down-count direction
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.
[11] ZPTRGEN5 Channel 5 Zero Point Trigger ADC Enable Bit
Enable PWM trigger ADC function while channel5's counter matching 0
0 = PWM condition trigger ADC function Disabled.
1 = PWM condition trigger ADC function Enabled.
Note: This bit is valid for both center-aligned type and edged-aligned type.

Definition at line 7427 of file Mini58Series.h.

◆ ADCTSTS0

__IO uint32_t PWM_T::ADCTSTS0

ADCTSTS0

Offset: 0x70 PWM Trigger Status Register 0

Bits Field Descriptions
[0] CUTRGF0 Channel 0 Compare Up Trigger ADC Flag
When the channel0's counter is counting up to CMP0, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[1] CPTRGF0 Channel 0 Center Point Trigger ADC Flag
When the channel0's counter is counting to PERIOD0, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[2] CDTRGF0 Channel 0 Compare Down Trigger ADC Flag
When the channel0's counter is counting down to CMP0, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[3] ZPTRGF0 Channel 0 Zero Point Trigger ADC Flag
When the channel0's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[8] CUTRGF1 Channel 1 Compare Up Trigger ADC Flag
When the channel1's counter is counting up to CMP1, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[9] CPTRGF1 Channel 1 Center Point Trigger ADC Flag
When the channel1's counter is counting to PERIOD1, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[10] CDTRGF1 Channel 1 Compare Down Trigger ADC Flag
When the channel1's counter is counting down to CMP1, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[11] ZPTRGF1 Channel 1 Zero Point Trigger ADC Flag
When the channel1's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[16] CUTRGF2 Channel 2 Compare Up Trigger ADC Flag
When the channel2's counter is counting up to CMP2, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[17] CPTRGF2 Channel 2 Center Point Trigger ADC Flag
When the channel2's counter is counting to PERIOD2, this bit will be set for trigger ADC. Note:
This bit can be cleared by software writing 1.
[18] CDTRGF2 Channel 2 Compare Down Trigger ADC Flag
When the channel2's counter is counting down to CMP2, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[19] ZPTRGF2 Channel 2 Zero Point Trigger ADC Enable Bit
When the channel2's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[24] CUTRGF3 Channel 3 Compare Up Trigger ADC Flag
When the channel3's counter is counting up to CMP3, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[25] CPTRGF3 Channel 3 Center Point Trigger ADC Flag
When the channel3's counter is counting to PERIOD3, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[26] CDTRGF3 Channel 3 Compare Down Trigger ADC Flag
When the channel3's counter is counting down to CMP3, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[27] ZPTRGF3 Channel 3 Zero Point Trigger ADC Flag
When the channel3's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.

Definition at line 7485 of file Mini58Series.h.

◆ ADCTSTS1

__IO uint32_t PWM_T::ADCTSTS1

ADCTSTS1

Offset: 0x74 PWM Trigger Status Register 1

Bits Field Descriptions
[0] CUTRGF4 Channel 4 Compare Up Trigger ADC Flag
When the channel4's counter is counting up to CMP4, this bit will be set for trigger ADC. Note:
This bit can be cleared by software writing 1.
[1] CPTRGF4 Channel 4 Center Point Trigger ADC Flag
When the channel4's counter is counting to PERIOD4, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[2] CDTRGF4 Channel 4 Compare Down Trigger ADC Flag
When the channel4's counter is counting down to CMP4, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[3] ZPTRGF4 Channel 4 Zero Point Trigger ADC Flag
When the channel4's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[8] CUTRGF5 Channel 5 Compare Up Trigger ADC Flag
When the channel5's counter is counting up to CMP5, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[9] CPTRGF5 Channel 5 Center Point Trigger ADC Flag
When the channel5's counter is counting to PERIOD5, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[10] CDTRGF5 Channel 5 Compare Down Trigger ADC Flag
When the channel5's counter is counting down to CMP5, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.
[11] ZPTRGF5 Channel 5 Zero Point Trigger ADC Flag
When the channel5's counter is counting to zero point, this bit will be set for trigger ADC.
Note: This bit can be cleared by software writing 1.

Definition at line 7519 of file Mini58Series.h.

◆ ADDR0

__IO uint32_t I2C_T::ADDR0

ADDR0

Offset: 0x04 I2C Slave Address Register 0

Bits Field Descriptions
[0] GC General Call Function Control
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In Slave mode, the seven most significant bits must be loaded with the MCU's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 4603 of file Mini58Series.h.

◆ ADDR1

__IO uint32_t I2C_T::ADDR1

ADDR1

Offset: 0x18 I2C Slave Address Register 1

Bits Field Descriptions
[0] GC General Call Function Control
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In Slave mode, the seven most significant bits must be loaded with the MCU's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 4688 of file Mini58Series.h.

◆ ADDR2

__IO uint32_t I2C_T::ADDR2

ADDR2

Offset: 0x1C I2C Slave Address Register 2

Bits Field Descriptions
[0] GC General Call Function Control
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In Slave mode, the seven most significant bits must be loaded with the MCU's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 4705 of file Mini58Series.h.

◆ ADDR3

__IO uint32_t I2C_T::ADDR3

ADDR3

Offset: 0x20 I2C Slave Address Register 3

Bits Field Descriptions
[0] GC General Call Function Control
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In Slave mode, the seven most significant bits must be loaded with the MCU's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 4722 of file Mini58Series.h.

◆ ADDRMSK0

__IO uint32_t I2C_T::ADDRMSK0

ADDRMSK0

Offset: 0x24 I2C Slave Address Mask Register 0

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask Bits
0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register).
1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4735 of file Mini58Series.h.

◆ ADDRMSK1

__IO uint32_t I2C_T::ADDRMSK1

ADDRMSK1

Offset: 0x28 I2C Slave Address Mask Register 1

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask Bits
0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register).
1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4748 of file Mini58Series.h.

◆ ADDRMSK2

__IO uint32_t I2C_T::ADDRMSK2

ADDRMSK2

Offset: 0x2C I2C Slave Address Mask Register 2

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask Bits
0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register).
1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4761 of file Mini58Series.h.

◆ ADDRMSK3

__IO uint32_t I2C_T::ADDRMSK3

ADDRMSK3

Offset: 0x30 I2C Slave Address Mask Register 3

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask Bits
0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register).
1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4774 of file Mini58Series.h.

◆ AHBCLK

__IO uint32_t CLK_T::AHBCLK

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[2] ISPCKEN Flash ISP Controller Clock Enable Bit
0 = Flash ISP peripheral clock Disabled.
1 = Flash ISP peripheral clock Enabled.

Definition at line 889 of file Mini58Series.h.

◆ ALTCTL [1/2]

__IO uint32_t UART_T::ALTCTL

ALTCTL

Offset: 0x2C UART Alternate Control/Status Register

Bits Field Descriptions
[8] RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) Control
0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled.
1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled.
Note: It cannot be active with RS485_AAD operation mode.
[9] RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD)
0 = RS-485 Auto Address Detection Operation Mode (AAD) Disabled.
1 = RS-485 Auto Address Detection Operation Mode (AAD) Enabled.
Note: It cannot be active with RS485_NMM operation mode.
[10] RS485_AUD RS-485 Auto Direction Mode (AUD) Control
0 = RS-485 Auto Direction Function Mode (AUD) Disabled.
1 = RS-485 Auto Direction Function Mode (AUD) Enabled.
Note: It cannot be active with RS485_NMM operation mode.
[15] ADDRDEN RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
0 = RS-485 address detection mode Disabled.
1 = RS-485 address detection mode Enabled.
Note: This field is used for RS-485 any operation mode.
[31:24] ADDRMV Address Match Values
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.

Definition at line 11141 of file Mini58Series.h.

◆ ALTCTL [2/2]

__IO uint32_t WDT_T::ALTCTL

ALTCTL

Offset: 0x04 WDT Alternative Control Register

Bits Field Descriptions
[1:0] RSTDSEL WDT Reset Delay Selection (Write Protect)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
00 = WDT Reset Delay Period is 1026 * WDT_CLK.
01 = WDT Reset Delay Period is 130 * WDT_CLK.
10 = WDT Reset Delay Period is 18 * WDT_CLK.
11 = WDT Reset Delay Period is 3 * WDT_CLK.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This register will be reset to 0 if WDT time-out reset happened.

Definition at line 11473 of file Mini58Series.h.

◆ APBCLK

__IO uint32_t CLK_T::APBCLK

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits Field Descriptions
[0] WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)
0 = Watchdog Timer clock Disabled.
1 = Watchdog Timer clock Enabled.
Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection.
Refer to the register SYS_REGLCTL at address SYS_BA + 0x10.
[2] TMR0CKEN Timer0 Clock Enable Bit
0 = Timer0 clock Disabled.
1 = Timer0 clock Enabled.
[3] TMR1CKEN Timer1 Clock Enable Bit
0 = Timer1 clock Disabled.
1 = Timer1 clock Enabled.
[6] CLKOCKEN Frequency Divider Output Clock Enable Bit
0 = CLKO clock Disabled.
1 = CLKO clock Enabled.
[8] I2C0CKEN I2C0 Clock Enable Bit
0 = I2C0 clock Disabled.
1 = I2C0 clock Enabled.
[9] I2C1CKEN I2C1 Clock Enable Bit
0 = I2C1 clock Disabled.
1 = I2C1 clock Enabled.
[12] SPICKEN SPI Clock Enable Bit
0 = SPI peripheral clock Disabled.
1 = SPI peripheral clock Enabled.
[16] UART0CKEN UART0 Clock Enable Bit
0 = UART0 clock Disabled.
1 = UART0 clock Enabled.
[17] UART1CKEN UART1 Clock Enable Bit
0 = UART1 clock Disabled.
1 = UART1 clock Enabled.
[20] PWMCH01CKEN PWM_01 Clock Enable Bit
0 = PWM01 clock Disabled.
1 = PWM01 clock Enabled.
[21] PWMCH23CKEN PWM_23 Clock Enable Bit
0 = PWM23 clock Disabled.
1 = PWM23 clock Enabled.
[22] PWMCH45CKEN PWM_45 Clock Enable Bit
0 = PWM45 clock Disabled.
1 = PWM45 clock Enabled.
[28] ADCCKEN Analog-digital-converter (ADC) Clock Enable Bit
0 = ADC peripheral clock Disabled.
1 = ADC peripheral clock Enabled.
[30] ACMPCKEN Analog Comparator Clock Enable Bit
0 = Analog Comparator clock Disabled.
1 = Analog Comparator clock Enabled.

Definition at line 943 of file Mini58Series.h.

◆ BAUD

__IO uint32_t UART_T::BAUD

BAUD

Offset: 0x24 UART Baud Rate Divisor Register

Bits Field Descriptions
[15:0] BRD Baud Rate Divider
The field indicates the baud rate divider.
[27:24] EDIVM1 Divider X
The baud rate divider M = X+1.
[28] BAUDM0 Divider X Equal 1
0 = Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must >= 8).
1 = Divider M = 1 (the equation of M = 1, but BRD [15:0] must >= 8).
Note: Refer to section "UART Controller Baud Rate Generator" for more information.
[29] BAUDM1 Divider X Enable Bit
The BRD = Baud Rate Divider, and the baud rate equation is:
Baud Rate = Clock / [M * (BRD + 2)], The default value of M is 16.
0 = Divider X Disabled (the equation of M = 16).
1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must >= 8).
Note: In IrDA mode, this bit must be disabled.

Definition at line 11092 of file Mini58Series.h.

◆ BODCTL

__IO uint32_t SYS_T::BODCTL

BODCTL

Offset: 0x18 Brown-out Detector Control Register

Bits Field Descriptions
[0] BODEN Brown-out Detector Selection Extension (Initiated & Write-protected Bit)
The default value is set by flash controller user configuration register config0 bit[23].
If config0 bit[23] is set to 1, default value of BODEN is 0.
If config0 bit[23] is set to 0, default value of BODEN is 1.
0 = Brown-out detector threshold voltage is selected by the table defined in BODVL.
1 = Brown-out detector threshold voltage is selected by the table defined as below.
BODVL = 00 = Brown-out Detector threshold voltage is 2.2V.
BODVL = 01 = Brown-out Detector threshold voltage is 2.7V.
BODVL = 10 = Brown-out Detector threshold voltage is 3.7V.
BODVL = 11 = Brown-out Detector threshold voltage is 4.4V.
[2:1] BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register CBOV (CONFIG0[22:21]).
00 = Reserved.
01 = Brown-out Detector threshold voltage is 2.7V.
10 = Brown-out Detector threshold voltage is 3.7V.
11 = Brown-out Detector function Disabled.
[3] BODRSTEN Brown-out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.
0 = Brown-out "INTERRUPT" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU.
1 = Brown-out "RESET" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip.
Note: When the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0.
The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is require.
[4] BODIF Brown-out Detector Interrupt Flag
0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
1 = When Brown-out Detector detects the VDD is dropped through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled.
[5] BODLPM Brown-out Detector Low Power Mode (Write Protect)
0 = BOD operate in normal mode (default).
1 = BOD Low Power mode Enabled.
Note: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
[6] BODOUT Brown-out Detector Output Status
0 = Brown-out Detector status output is 0, the detected voltage is higher than BODVL setting.
1 = Brown-out Detector status output is 1, the detected voltage is lower than BODVL setting.

Definition at line 9634 of file Mini58Series.h.

◆ BRKCTL

__IO uint32_t PWM_T::BRKCTL

BRKCTL

Offset: 0x60 PWM Fault Brake Control Register

Bits Field Descriptions
[0] BRK0EN Enable BKP0 Pin Trigger Fault Brake Function 0
0 = Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1).
1 = Enabling a falling at BKP0 pin can trigger brake function 0.
[1] BRK1EN Enable BKP1 Pin Trigger Fault Brake Function 1
0 = Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0).
1 = Enabling a falling at BKP1 pin can trigger brake function 1.
[2] BRK0SEL BKP1 Fault Brake Function Source Select Bit
0 = EINT1 as one brake source in BKP1.
1 = CPO0 as one brake source in BKP1.
[3] BRK1SEL BKP0 Fault Brake Function Source Select Bit
0 = EINT0 as one brake source in BKP0.
1 = CPO1 as one brake source in BKP0.
[7] BRKSTS PWM Fault Brake Event Status Flag
0 = PWM output initial state when fault brake conditions asserted.
1 = PWM output fault brake state when fault brake conditions asserted.
Note: This bit can be cleared by software writing 1 and must be cleared before restarting the PWM counter.
[8] BRKACT PWM Brake Action Type
0 = PWM counter stop when brake is asserted.
1 = PWM counter keep going when brake is asserted.
[9] SWBRK Software Brake
0 = Disable PWM Software brake and back to normal PWM function.
1 = Assert PWM Brake immediately.
[29:24] BKOD0 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[29:24] BKOD1 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[29:24] BKOD2 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[29:24] BKOD3 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[29:24] BKOD4 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[29:24] BKOD5 PWM Brake Output Data Select Bits
0 = PWM channel n output low when fault brake conditions asserted.
1 = PWM channel n output high when fault brake conditions asserted.
[30] D6BKOD Channel 6 Brake Output Data Select Bit
0 = Channel 6 output low when fault brake conditions asserted.
1 = Channel 6 output high when fault brake conditions asserted.
[31] D7BKOD Channel 7 Brake Output Data Select Bit
0 = Channel 7 output low when fault brake conditions asserted.
1 = Channel 7 output high when fault brake conditions asserted.

Definition at line 7256 of file Mini58Series.h.

◆ CAP

__I uint32_t TIMER_T::CAP

CAP

Offset: 0x10 Timer0 Capture Data Register

Bits Field Descriptions
[23:0] CAPDAT Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.

Definition at line 10449 of file Mini58Series.h.

◆ CHEN

__IO uint32_t ADC_T::CHEN

CHEN

Offset: 0x24 A/D Channel Enable Register

Bits Field Descriptions
[0] CHEN0 Analog Input Channel 0 Enable Bit
0 = Channel 0 Disabled.
1 = Channel 0 Enabled.
Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
[1] CHEN1 Analog Input Channel 1 Enable Bit
0 = Channel 1 Disabled.
1 = Channel 1 Enabled.
[2] CHEN2 Analog Input Channel 2 Enable Bit
0 = Channel 2 Disabled.
1 = Channel 2 Enabled.
[3] CHEN3 Analog Input Channel 3 Enable Bit
0 = Channel 3 Disabled.
1 = Channel 3 Enabled.
[4] CHEN4 Analog Input Channel 4 Enable Bit
0 = Channel 4 Disabled.
1 = Channel 4 Enabled.
[5] CHEN5 Analog Input Channel 5 Enable Bit
0 = Channel 5 Disabled.
1 = Channel 5 Enabled.
[6] CHEN6 Analog Input Channel 6 Enable Bit
0 = Channel 6 Disabled.
1 = Channel 6 Enabled.
[7] CHEN7 Analog Input Channel 7 Enable Bit
0 = Channel 7 Disabled.
1 = Channel 7 Enabled.
[8] CH7SEL Analog Input Channel 7 Selection
0 = External analog input.
1 = Internal band-gap voltage (VBG).
Note: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.

Definition at line 426 of file Mini58Series.h.

◆ CLKDIV [1/4]

__IO uint32_t CLK_T::CLKDIV

CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits Field Descriptions
[3:0] HCLKDIV HCLK Clock Divide Number From HCLK Clock Source
HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
[11:8] UARTDIV UART Clock Divide Number From UART Clock Source
UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
[23:16] ADCDIV ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source
ADC peripheral clock frequency = (ADC peripheral clock source frequency) / (ADCDIV + 1).

Definition at line 1088 of file Mini58Series.h.

◆ CLKDIV [2/4]

__IO uint32_t I2C_T::CLKDIV

CLKDIV

Offset: 0x10 I2C Clock Divided Register

Bits Field Descriptions
[7:0] DIVIDER I2C Clock Divided Register
The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4 * (I2C_CLKDIV+1)).
Note: The minimum value of I2C_CLKDIV is 4.

Definition at line 4649 of file Mini58Series.h.

◆ CLKDIV [3/4]

__IO uint32_t PWM_T::CLKDIV

CLKDIV

Offset: 0x04 PWM Clock Select Register

Bits Field Descriptions
[2:0] CLKDIV0 Counter 0 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC01/2).
001 = Clock input / (CLKPSC01/4).
010 = Clock input / (CLKPSC01/8).
011 = Clock input / (CLKPSC01/16).
100 = Clock input / CLKPSC01.
Others = Clock input.
[6:4] CLKDIV1 Counter 1 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC01/2).
001 = Clock input / (CLKPSC01/4).
010 = Clock input / (CLKPSC01/8).
011 = Clock input / (CLKPSC01/16).
100 = Clock input / CLKPSC01.
Others = Clock input.
[10:8] CLKDIV2 Counter 2 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC23/2).
001 = Clock input / (CLKPSC23/4).
010 = Clock input / (CLKPSC23/8).
011 = Clock input / (CLKPSC23/16).
100 = Clock input / CLKPSC23.
Others = Clock input.
[14:12] CLKDIV3 Counter 3 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC23/2).
001 = Clock input / (CLKPSC23/4).
010 = Clock input / (CLKPSC23/8).
011 = Clock input / (CLKPSC23/16).
100 = Clock input / CLKPSC23.
Others = Clock input.
[18:16] CLKDIV4 Counter 4 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC45/2).
001 = Clock input / (CLKPSC45/4).
010 = Clock input / (CLKPSC45/8).
011 = Clock input / (CLKPSC45/16).
100 = Clock input / CLKPSC45.
Others = Clock input.
[22:20] CLKDIV5 Counter 5 Clock Divider Selection
Select clock input for PWM counter.
000 = Clock input / (CLKPSC45/2).
001 = Clock input / (CLKPSC45/4).
010 = Clock input / (CLKPSC45/8).
011 = Clock input / (CLKPSC45/16).
100 = Clock input / CLKPSC45.
Others = Clock input.

Definition at line 5460 of file Mini58Series.h.

◆ CLKDIV [4/4]

__IO uint32_t SPI_T::CLKDIV

CLKDIV

Offset: 0x04 SPI Clock Divider Register

Bits Field Descriptions
[7:0] DIVIDER Clock Divider Register (Master Only)
The value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPI_CLK output pin.
The frequency is obtained according to the following equation:
If the bit of DIVMOD, SPI_SLVCTL[31], is set to 0.
else if DIVMOD is set to 1,
where
is the SPI peripheral clock source which is defined in the CLK_CLKSEL1 register.

Definition at line 9078 of file Mini58Series.h.

◆ CLKOCTL

__IO uint32_t CLK_T::CLKOCTL

CLKOCTL

Offset: 0x24 Frequency Divider Control Register

Bits Field Descriptions
[3:0] FREQSEL Divider Output Frequency Selection
The formula of output frequency is
Fout = Fin/2(N+1).
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL(CLK_CLKOCTL[3:0]).
[4] CLKOEN Frequency Divider Enable Bit
0 = Frequency Divider Disabled.
1 = Frequency Divider Enabled.
[5] DIV1EN Frequency Divider One Enable Bit
0 = Divider output frequency is depended on FREQSEL value.
1 = Divider output frequency is the same as input clock frequency.

Definition at line 1166 of file Mini58Series.h.

◆ CLKPSC

__IO uint32_t PWM_T::CLKPSC

CLKPSC

Offset: 0x00 PWM Clock Pre-scale Register

Bits Field Descriptions
[7:0] CLKPSC01 Clock Prescaler 0 For PWM Counter 0 And 1
Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter.
If CLKPSC01 = 0, the clock prescaler 0 output clock will be stopped.
So the corresponding PWM counter will also be stopped.
[15:8] CLKPSC23 Clock Prescaler 2 For PWM Counter 2 And 3
Clock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter.
If CLKPSC23 = 0, the clock prescaler 2 output clock will be stopped.
So the corresponding PWM counter will also be stopped.
[23:16] CLKPSC45 Clock Prescaler 4 For PWM Counter 4 And 5
Clock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter.
If CLKPSC45 = 0, the clock prescaler 4 output clock will be stopped.
So the corresponding PWM counter will also be stopped.

Definition at line 5402 of file Mini58Series.h.

◆ CLKSEL0

__IO uint32_t CLK_T::CLKSEL0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLKSEL HCLK Clock Source Selection (Write Protect)
000 = Clock source is from HXT or LXT.
001 = Reserved.
010 = Clock source is from PLL.
011 = Clock source is from LIRC.
111 = Clock source is from HIRC.
Others = Reserved.
Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.
Note2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection.
Refer to the register SYS_REGLCTL at address SYS_BA + 0x10.
Note3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock.
[5:3] STCLKSEL Cortex-M0 SysTick Clock Source Selection (Write Protect)
If CLKSRC (SYST_CSR[2]) = 1, SysTick clock source is from HCLK.
If CLKSRC (SYST_CSR[2]) = 0, SysTick clock source is defined by below settings.
000 = Clock source is from HXT or LXT.
001 = Reserved.
010 = Clock source is from HXT/2 or LXT/2.
011 = Clock source is from HCLK/2.
111 = Clock source is from HIRC/2.
Others = Reserved.
Note1: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection.
Refer to the register SYS_REGLCTL at address SYS_BA + 0x10.
Note2: If the SysTick clock source is not from HCLK (i.e.
CLKSRC(SYST_CSR[2]) = 0), SysTick clock source must less than or equal to HCLK/.
Note3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.

Definition at line 1008 of file Mini58Series.h.

◆ CLKSEL1

__IO uint32_t CLK_T::CLKSEL1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] WDTSEL WDT CLK Clock Source Selection (Write Protect)
00 = Clock source is from HXT or LXT.
01 = Reserved.
10 = Clock source is from HCLK/2048 clock.
11 = Clock source is from LIRC.
Note1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection.
Refer to the register SYS_REGLCTL at address SYS_BA + 0x10.
Note2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[3:2] ADCSEL ADC Peripheral Clock Source Selection
00 = Clock source is from HXT or LXT.
01 = Clock source is from PLL.
10 = Clock source is from HCLK.
11 = Clock source is from HIRC.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[5:4] SPISEL SPI Clock Source Selection
00 = Clock source is from HXT or LXT.
01 = Clock source is from HCLK.
10 = Clock source is from PLL.
11 = Reserved.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[10:8] TMR0SEL TIMER0 Clock Source Selection
000 = Clock source is from HXT or LXT.
001 = Clock source is from LIRC.
010 = Clock source is from HCLK.
011 = Clock source is from external trigger.
111 = Clock source is from HIRC.
Others = Reserved.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[14:12] TMR1SEL TIMER1 Clock Source Selection
000 = Clock source is from HXT or LXT.
001 = Clock source is from LIRC.
010 = Clock source is from HCLK.
011 = Clock source is from external trigger.
111 = Clock source is from HIRC.
Others = Reserved.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[25:24] UARTSEL UART Clock Source Selection
00 = Clock source is from HXT or LXT.
01 = Clock source is from PLL.
10 = Clock source is from HIRC.
11 = Clock source is from HIRC.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[29:28] PWMCH01SEL PWM0 And PWM1 Clock Source Selection
PWM0 and PWM1 use the same peripheral clock source. Both of them use the same prescaler.
00 = Reserved.
01 = Reserved.
10 = Clock source is from HCLK.
11 = Reserved.
[31:30] PWMCH23SEL PWM2 And PWM3 Clock Source Selection
PWM2 and PWM3 use the same peripheral clock source; Both of them use the same prescaler.
00 = Reserved.
01 = Reserved.
10 = Clock source is from HCLK.
11 = Reserved.

Definition at line 1072 of file Mini58Series.h.

◆ CLKSEL2

__IO uint32_t CLK_T::CLKSEL2

CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits Field Descriptions
[3:2] CLKOSEL Clock Divider Clock Source Selection
00 = Clock source is from HXT or LXT.
01 = Clock source is from LIRC.
10 = Clock source is from HCLK.
11 = Clock source is from HIRC.
Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
[5:4] PWMCH45SEL PWM4 And PWM5 Clock Source Selection
PWM4 and PWM5 use the same peripheral clock source; Both of them use the same prescaler.
00 = Reserved.
01 = Reserved.
10 = Clock source is from HCLK.
11 = Reserved.
[17:16] WWDTSEL Window Watchdog Timer Clock Source Selection
00 = Reserved.
01 = Reserved.
10 = Clock source from HCLK/2048 clock.
11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).

Definition at line 1115 of file Mini58Series.h.

◆ CMP

__IO uint32_t TIMER_T::CMP

CMP

Offset: 0x04 Timer0 Compare Register

Bits Field Descriptions
[23:0] CMPDAT Timer Compared Value
CMPDAT is a 24-bit compared value register.
When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to .
Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into the CMPDAT fiel.

Definition at line 10403 of file Mini58Series.h.

◆ CMP0

__IO uint32_t ADC_T::CMP0

CMP0

Offset: 0x28 A/D Compare Register 0

Bits Field Descriptions
[0] ADCMPEN A/D Compare Enable Bit
Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.
0 = Compare function Disabled.
1 = Compare function Enabled.
[1] ADCMPIE A/D Compare Interrupt Enable Bit
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
0 = Compare function interrupt Disabled.
1 = Compare function interrupt Enabled.
[2] CMPCOND Compare Condition
0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one.
1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one.
Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
[5:3] CMPCH Compare Channel Selection
Set this field to select which channel's result to be compared.
Note: Valid setting of this field is channel 0~7.
[11:8] CMPMCNT Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
[25:16] CMPDAT Comparison Data
The 10-bit data is used to compare with conversion result of specified channel.

Definition at line 456 of file Mini58Series.h.

◆ CMP1

__IO uint32_t ADC_T::CMP1

CMP1

Offset: 0x2C A/D Compare Register 1

Bits Field Descriptions
[0] ADCMPEN A/D Compare Enable Bit
Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.
0 = Compare function Disabled.
1 = Compare function Enabled.
[1] ADCMPIE A/D Compare Interrupt Enable Bit
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
0 = Compare function interrupt Disabled.
1 = Compare function interrupt Enabled.
[2] CMPCOND Compare Condition
0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one.
1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one.
Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
[5:3] CMPCH Compare Channel Selection
Set this field to select which channel's result to be compared.
Note: Valid setting of this field is channel 0~7.
[11:8] CMPMCNT Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
[25:16] CMPDAT Comparison Data
The 10-bit data is used to compare with conversion result of specified channel.

Definition at line 486 of file Mini58Series.h.

◆ CMPDAT0

__IO uint32_t PWM_T::CMPDAT0

CMPDAT0

Offset: 0x24 PWM Comparator Register 0

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6333 of file Mini58Series.h.

◆ CMPDAT1

__IO uint32_t PWM_T::CMPDAT1

CMPDAT1

Offset: 0x28 PWM Comparator Register 1

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6463 of file Mini58Series.h.

◆ CMPDAT2

__IO uint32_t PWM_T::CMPDAT2

CMPDAT2

Offset: 0x2C PWM Comparator Register 2

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6593 of file Mini58Series.h.

◆ CMPDAT3

__IO uint32_t PWM_T::CMPDAT3

CMPDAT3

Offset: 0x30 PWM Comparator Register 3

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6723 of file Mini58Series.h.

◆ CMPDAT4

__IO uint32_t PWM_T::CMPDAT4

CMPDAT4

Offset: 0x34 PWM Comparator Register 4

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6853 of file Mini58Series.h.

◆ CMPDAT5

__IO uint32_t PWM_T::CMPDAT5

CMPDAT5

Offset: 0x38 PWM Comparator Register 5

Bits Field Descriptions
[15:0] CMP0 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP1 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP2 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP3 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP4 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[15:0] CMP5 PWM Comparator Register
CMP determines the PWM duty.
Edge-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/(PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMPn will take effect in the next PWM cycle.
[31:16] CMPD0 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD1 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD2 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD3 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD4 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.
[31:16] CMPD5 PWM Comparator Register For Down Counter In Asymmetric Mode
CMPn >= PERIODn: up counter PWM output is always low.
CMPDn >= PERIODn: down counter PWM output is always low.
Others: PWM output is always high.

Definition at line 6983 of file Mini58Series.h.

◆ CNT [1/2]

__I uint32_t TIMER_T::CNT

CNT

Offset: 0x0C Timer0 Data Register

Bits Field Descriptions
[23:0] CNT Timer Data Register
This field can be reflected the internal 24-bit timer counter value or external event input counter value from TMx (x=0~1) pin.
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24- bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24- bit event input counter value.

Definition at line 10437 of file Mini58Series.h.

◆ CNT [2/2]

__I uint32_t WWDT_T::CNT

CNT

Offset: 0x0C WWDT Counter Value Register

Bits Field Descriptions
[5:0] CNTDAT WWDT Counter Value
CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.

Definition at line 11617 of file Mini58Series.h.

◆ CON

__IO uint32_t INTR_T::CON

CON

Offset: 0x80 NMI Source Interrupt Select Control Register

Bits Field Descriptions
[4:0] NMI_SEL NMI Interrupt Source Select Bit
The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
[8] NMI_SEL_EN NMI Interrupt Enable Bit (Write Protected)
0 = NMI interrupt Disabled.
1 = NMI interrupt Enabled.
Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection.
Refer to the register SYS_REGLCTL at address SYS_BA+0x10.

Definition at line 5262 of file Mini58Series.h.

◆ CTL [1/8]

__IO uint32_t ACMP_T::CTL[2]

CTL0, 1

Offset: 0x00, 0x04 Analog Comparator 0, 1 Control Register

Bits Field Descriptions
[0] ACMPEN Analog Comparator x Enable Bit
0 = Analog Comparator x Disabled.
1 = Analog Comparator x Enabled.
Note: Analog comparator output needs to wait 2 us stable time after this bit is set.
[1] ACMPIE Analog Comparator x Interrupt Enable Bit
0 = Interrupt function Disabled.
1 = Interrupt function Enabled.
[2] HYSSEL Analog Comparator x Hysteresis Select Bit
0 = Hysteresis function Disabled.
1 = Hysteresis function Enabled.
[4] NEGSEL Analog Comparator x Negative Input Select Bit
0 = The source of the negative comparator input is from CPNx pin.
1 = The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage.
[8] RTRGEN Analog Comparator x Rising Edge Trigger Enable Bit
0 = Analog comparator rising edge trigger PWM or Timer enabled.
1 = Analog comparator rising edge trigger disabled.
Note: The bit is only effective while analog comparator x triggers PWM or Timer.
[9] FTRGEN Analog Comparator x Falling Edge Trigger Enable
0 = Analog comparator falling edge trigger PWM or Timer enabled.
1 = Analog comparator falling edge trigger disabled.
Note: The bit is only effective while analog comparator x triggers PWM or Timer.
[23:20] FILTSEL Comparator Output Filter Count Selection
0000 = Filter function is Disabled.
0001 = ACMP0 output is sampled 1 consecutive PCLK.
0010 = ACMP0 output is sampled 2 consecutive PCLKs.
0011 = ACMP0 output is sampled 4 consecutive PCLKs.
0100 = ACMP0 output is sampled 8 consecutive PCLKs.
0101 = ACMP0 output is sampled 16 consecutive PCLKs.
0110 = ACMP0 output is sampled 32 consecutive PCLKs.
0111 = ACMP0 output is sampled 64 consecutive PCLKs.
1000 = ACMP0 output is sampled 128 consecutive PCLKs.
1001 = ACMP0 output is sampled 256 consecutive PCLKs.
1010 = ACMP0 output is sampled 512 consecutive PCLKs.
Others = Reserved.
[30:29] POSSEL Analog Comparator Positive Input Selection
00 = ACMP0_Px is from ACMPx_P0 pin.
01 = ACMP0_Px is from ACMPx_P1 pin.
10 = ACMP0_Px is from ACMPx_P2 pin.
11 = ACMP0_Px is from ACMPx_P3 pin.

Definition at line 213 of file Mini58Series.h.

◆ CTL [2/8]

__IO uint32_t ADC_T::CTL

CTL

Offset: 0x20 A/D Control Register

Bits Field Descriptions
[0] ADCEN A/D Converter Enable Bit
0 = A/D Converter Disabled.
1 = A/D Converter Enabled.
Note: Before starting A/D conversion function, this bit should be set to 1.
Clear it to 0 to disable A/D converter analog circuit to save power consumption.
[1] ADCIEN A/D Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADCIEN bit is set to 1.
0 = A/D interrupt function Disabled.
1 = A/D interrupt function Enabled.
[5:4] HWTRGSEL Hardware Trigger Source Select Bit
00 = A/D conversion is started by external STADC pin.
11 = A/D conversion is started by PWM trigger.
Others = Reserved.
Note: Software should disable TRGEN and SWTRG before change TRGS.
[6] HWTRGCOND Hardware External Trigger Condition
This bit decides whether the external pin STADC trigger event is falling or raising edge.
The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigge.
0 = Falling edge.
1 = Raising edge.
[8] HWTRGEN Hardware External Trigger Enable Bit
Enable or disable triggering of A/D conversion by external STADC pin.
If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger sourc.
0= External trigger Disabled.
1= External trigger Enabled.
[11] SWTRG Software Trigger A/D Conversion Start
SWTRG bit can be set to 1 from two sources: software and external pin STADC.
SWTRG will be cleared to 0 by hardware automatically after conversion complet.
0 = Conversion stopped and A/D converter entered idle state.
1 = Conversion start.

Definition at line 387 of file Mini58Series.h.

◆ CTL [3/8]

__IO uint32_t I2C_T::CTL

CTL

Offset: 0x00 I2C Control Register

Bits Field Descriptions
[2] AA Assert Acknowledge Control Bit
When AA=1 is prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
[3] SI I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested.
SI must be cleared by software.
This bit can be cleared by software writing '1'.
[4] STO I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
In Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode.
This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
[5] STA I2C START Control Bit
Set STA to logic 1 to enter Master mode.
I2C hardware sends a START or repeats the START condition to bus when the bus is free.
[6] I2CEN I2C Controller Enable Bit
0 = I2C Controller Disabled.
1 = I2C Controller Enabled.
Set to enable I2C serial function controller.
When I2CEN=1 the I2C serial function enables.
The function of multi-function pin must be set to I2C firs.
[7] INTEN Interrupt Enable Bit
0 = I2C interrupt Disabled.
1 = I2C interrupt Enabled.

Definition at line 4586 of file Mini58Series.h.

◆ CTL [4/8]

__IO uint32_t PWM_T::CTL

CTL

Offset: 0x08 PWM Control Register

Bits Field Descriptions
[0] CNTEN0 PWM Counter 0 Enable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[1] DBGTRIOFF Disable PWM Output Tri-state Under Debug Mode (Available In DEBUG Mode Only)
0 = Safe mode: The counter is frozen and PWM outputs are shut down Safe state for the inverter.
The counter can still be re-started from where it stop.
1 = Normal mode: The counter continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced).
[2] PINV0 PWM0_CH0 Output Inverter Enable Bit
0 = PWM0_CH0 output inverter Disabled.
1 = PWM0_CH0 output inverter Enabled.
[3] CNTMODE0 PWM Counter 0 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD0 and CMP0 cleared.
[4] CNTEN1 PWM Counter 1 Enable/Disable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[5] HCUPDT Half Cycle Update Enable for Center-aligned Type
0 = Disable half cycle update PERIOD & CMP.
1 = Enable half cycle update PERIOD & CMP.
[6] PINV1 PWM0_CH1 Output Inverter Enable Bit
0 = PWM0_CH1 output inverter Disable.
1 = PWM0_CH1 output inverter Enable.
[7] CNTMODE1 PWM Counter 1 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD1 and CMP1 cleared.
[8] CNTEN2 PWM Counter 2 Enable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[10] PINV2 PWM0_CH2 Output Inverter Enable Bit
0 = PWM0_CH2 output inverter Disabled.
1 = PWM0_CH2 output inverter Enabled.
[11] CNTMODE2 PWM Counter 2 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD2 and CMP2 cleared.
[12] CNTEN3 PWM Counter 3 Enable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[14] PINV3 PWM0_CH 3 Output Inverter Enable Bit
0 = PWM0_CH3 output inverter Disabled.
1 = PWM0_CH3 output inverter Enabled.
[15] CNTMODE3 PWM Counter 3 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD3 and CMP3 cleared.
[16] CNTEN4 PWM Counter 4 Enable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[18] PINV4 PWM0_CH4 Output Inverter Enable Bit
0 = PWM0_CH4 output inverter Disabled.
1 = PWM0_CH4 output inverter Enabled.
[19] CNTMODE4 PWM Counter 4 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD4 and CMP4 cleared.
[20] CNTEN5 PWM Counter 5 Enable Start Run
0 = Corresponding PWM counter running Stopped.
1 = Corresponding PWM counter start run Enabled.
[21] ASYMEN Asymmetric Mode In Center-aligned Type
0 = Symmetric mode in center-aligned type.
1 = Asymmetric mode in center-aligned type.
[22] PINV5 PWM0_CH5 Output Inverter Enable Bit
0 = PWM0_CH5 output inverter Disabled.
1 = PWM0_CH5 output inverter Enabled.
[23] CNTMODE5 PWM Counter 5 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause PERIOD5 and CMP5 cleared.
[24] DTCNT01 Dead-time 0 Counter Enable Bit (PWM0_CH0 And PWM0_CH1 Pair For PWMA Group)
0 = Dead-time 0 generator Disabled.
1 = Dead-time 0 generator Enabled.
Note: When the dead-time generator is enabled, the pair of PWM0_CH0 and PWM0_CH1 becomes a complementary pair for PWMA group.
[25] DTCNT23 Dead-time 2 Counter Enable Bit (PWM0_CH2 And PWM0_CH3 Pair For PWMB Group)
0 = Dead-time 2 generator Disabled.
1 = Dead-time 2 generator Enabled.
Note: When the dead-time generator is enabled, the pair of PWM0_CH2 and PWM0_CH3 becomes a complementary pair for PWMB group.
[26] DTCNT45 Dead-time 4 Counter Enable Bit (PWM0_CH4 And PWM0_CH5 Pair For PWMC Group)
0 = Dead-time 4 generator Disabled.
1 = Dead-time 4 generator Enabled.
Note: When the dead-time generator is enabled, the pair of PWM0_CH4 and PWM0_CH5 becomes a complementary pair for PWMC group.
[27] CNTCLR Clear PWM Counter Control Bit
0 = Do not clear PWM counter.
1 = All 16-bit PWM counters cleared to 0x0000.
Note: It is automatically cleared by hardware.
[29:28] MODE PWM Operating Mode Select Bit
00 = Independent mode.
01 = Complementary mode.
10 = Synchronized mode.
11 = Reserved.
[30] GROUPEN Group Function Enable Bit
0 = The signals timing of all PWM channels are independent.
1 = Unify the signals timing of PWM0_CH0, PWM0_CH2 and PWM0_CH4 in the same phase which is controlled by PWM0_CH0 and also unify the signals timing of PWM0_CH1, PWM0_CH3 and PWM0_CH5 in the same phase which is controlled by PWM0_CH1.
[31] CNTTYPE PWM Counter-aligned Type Select Bit
0 = Edge-aligned type.
1 = Center-aligned type.

Definition at line 5567 of file Mini58Series.h.

◆ CTL [5/8]

__IO uint32_t SPI_T::CTL

CTL

Offset: 0x00 SPI Control and Status Register

Bits Field Descriptions
[0] SPIEN SPI Transfer Control Bit And Busy Status
If FIFO mode is enabled, this bit will be controlled by hardware and it's read only.
If FIFO mode is disabled, during the data transfer, this bit keeps the value of 1.
As the transfer is finished, this bit will be cleared automatically.
0 = Writing 0 to this bit to stop data transfer if SPI is transferring.
1 = In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master.
Note 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the SPIEN bit.
Note 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the SPIEN bit will not be cleared to 0 when slave select signal goes to inactive state.
[1] RXNEG Receive On Negative Edge
0 = The received data input signal latched on the rising-edge of SPI_CLK.
1 = The received data input signal latched on the falling-edge of SPI_CLK.
[2] TXNEG Transmit On Negative Edge
0 = The transmitted data output signal is driven on the rising-edge of SPI_CLK.
1 = The transmitted data output signal is driven on the falling-edge of SPI_CLK.
[7:3] DWIDTH Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive.
The minimum bit length is 8 bits and can up to 32 bit.
DWIDTH = 0x01~0x07 .... reserved (can't use).
DWIDTH = 0x08 .... 8 bits.
DWIDTH = 0x09 .... 9 bits.
......
DWIDTH = 0x1F .... 31 bits.
DWIDTH = 0x00 .... 32 bits.
[10] LSB LSB First
0 = The MSB is transmitted/received first.
1 = The LSB is transmitted/received first.
[11] CLKPOL Clock Polarity
0 = SPI_CLK idle low.
1 = SPI_CLK idle high.
[15:12] SUSPITV Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transactions in a transfer.
The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
The default value is 0x3.
The period of the suspend interval is obtained according to the following equation:
(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
Example:
SUSPITV = 0x0 .... 0.5 SPI_CLK clock cycle.
SUSPITV = 0x1 .... 1.5 SPI_CLK clock cycle.
......
SUSPITV = 0xE .... 14.5 SPI_CLK clock cycle.
SUSPITV = 0xF .... 15.5 SPI_CLK clock cycle.
[16] UNITIF Unit-transfer Interrupt Flag
0 = The transfer does not finish yet.
1 = The SPI controller has finished one unit transfer.
Note 1: This bit will be cleared by writing 1 to itself.
Note 2: It's a mutual mirror bit of SPI_STATUS[16].
[17] UNITIEN Unit-transfer Interrupt Enable Bit
0 = SPI unit-transfer interrupt Disabled.
1 = SPI unit-transfer interrupt Enabled.
[18] SLAVE Slave Mode Control
0 = Master mode.
1 = Slave mode.
[19] REORDER Byte Reorder Function
0 = Byte reorder function Disabled.
1 = Byte reorder function Enabled.
Note: This setting is only available if DWIDTH is defined as 16, 24, or 32 bits.
[21] FIFOEN FIFO Mode Enable Bit
0 = FIFO Mode Disabled.
1 = FIFO Mode Enabled.
Note 1: Before enabling FIFO mode, the other related settings should be set in advance.
Note 2: In Master mode, if the FIFO mode is enabled, the SPIEN bit will be set to 1 automatically after writing data into the 4-layer depth transmit FIFO.
When all data stored in transmit FIFO buffer are transferred, the SPIEN bit will back to .
[24] RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)
0 = The receive FIFO buffer is not empty.
1 = The receive FIFO buffer is empty.
Note: It's a mutual mirror bit of SPI_STATUS[24].
[25] RXFULL Receive FIFO Buffer Full Indicator (Read Only)
0 = The receive FIFO buffer is not full.
1 = The receive FIFO buffer is full.
Note: It's a mutual mirror bit of SPI_STATUS[25]
[26] TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)
0 = The transmit FIFO buffer is not empty.
1 = The transmit FIFO buffer is empty.
Note: It's a mutual mirror bit of SPI_STAUTS[26].
[27] TXFULL Transmit FIFO Buffer Full Indicator (Read Only)
0 = The transmit FIFO buffer is not full.
1 = The transmit FIFO buffer is full.
Note: It's a mutual mirror bit of SPI_STATUS[27].

Definition at line 9061 of file Mini58Series.h.

◆ CTL [6/8]

__IO uint32_t TIMER_T::CTL

CTL

Offset: 0x00 Timer0 Control and Status Register

Bits Field Descriptions
[7:0] PSC Prescale Counter
Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
If this field is 0 (PSC = 0), then there is no scaling.
[17] CMPCTL Timer Compared Mode Select Bit
0 = The behavior selection in one-shot or periodic mode Disabled.
When user updates CMPDAT while timer is running in one-shot or periodic mode,
CNT will be reset to default value.
1 = The behavior selection in one-shot or periodic mode Enabled.
When user updates CMPDAT while timer is running in one-shot or periodic mode, the limitations as bellows list,
If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
If updated CMPDAT value < CNT, CNT will be reset to default value.
[18] TGLPINSEL Toggle-output Pin Select Bit
0 = Toggle mode output to TMx (Timer Event Counter Pin).
1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
[19] CAPSRC Capture Pin Source Select Bit
0 = Capture Function source is from TMx_EXT (x= 0~1)
pin.
1 = Capture Function source is from internal ACMP output signal.
User can set CAPSRCMP (TIMERx_EXTCTL[9]) to decide which ACMP output signal as timer capture source.
[23] WKEN Wake-up Function Enable Bit
If this bit is set to 1, while the timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
0 = Wake-up function Disabled if timer interrupt signal generated.
1 = Wake-up function Enabled if timer interrupt signal generated.
[24] EXTCNTEN Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
0 = Event counter mode Disabled.
1 = Event counter mode Enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source
[25] ACTSTS Timer Active Status (Read Only)
This bit indicates the 24-bit up counter status.
0 = 24-bit up counter is not active.
1 = 24-bit up counter is active.
[26] RSTCNT Timer Counter Reset
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
0 = No effect.
1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
[28:27] OPMODE Timer Counting Mode Selection
00 = The Timer controller is operated in one-shot mode.
01 = The Timer controller is operated in periodic mode.
10 = The Timer controller is operated in toggle-output mode.
11 = The Timer controller is operated in continuous counting mode.
[29] INTEN Timer Interrupt Enable Bit
0 = Timer Interrupt Disabled.
1 = Timer Interrupt Enabled.
Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal will be generated and inform CPU.
[30] CNTEN Timer Counting Enable Bit
0 = Stops/Suspends counting.
1 = Starts counting.
Note1: In stop status, and then setting CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERx_CTL[28:27] = 2'b00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)
0 = ICE debug mode acknowledgement effects TIMER counting.
TIMER counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10386 of file Mini58Series.h.

◆ CTL [7/8]

__IO uint32_t WDT_T::CTL

CTL

Offset: 0x00 WDT Control Register

Bits Field Descriptions
[0] RSTCNT Reset WDT Up Counter (Write Protect)
0 = No effect.
1 = Reset the internal 18-bit WDT up counter value.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit will be automatically cleared by hardware.
[1] RSTEN WDT Time-out Reset Enable Bit (Write Protect)
Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
0 = WDT time-out reset function Disabled.
1 = WDT time-out reset function Enabled.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
[2] RSTF WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
0 = WDT time-out reset did not occur.
1 = WDT time-out reset occurred.
Note: This bit is cleared by writing 1 to it.
[3] IF WDT Time-out Interrupt Flag
This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval
0 = WDT time-out interrupt did not occur.
1 = WDT time-out interrupt occurred.
Note: This bit is cleared by writing 1 to it.
[4] WKEN WDT Time-out Wake-up Function Control (Write Protect)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT.
[5] WKF WDT Time-out Wake-up Flag (Write Protect)
This bit indicates the interrupt wake-up flag status of WDT
0 = WDT does not cause chip wake-up.
1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit is cleared by writing 1 to it.
[6] INTEN WDT Time-out Interrupt Enable Bit (Write Protect)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
0 = WDT time-out interrupt Disabled.
1 = WDT time-out interrupt Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] WDTEN WDT Enable Bit (Write Protect)
0 = WDT Disabled (This action will reset the internal up counter value).
1 = WDT Enabled.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
[10:8] TOUTSEL WDT Time-out Interval Selection (Write Protect)
These three bits select the time-out interval period for the WDT.
000 = 2^4 * WDT_CLK.
001 = 2^6 * WDT_CLK.
010 = 2^8 * WDT_CLK.
011 = 2^10 * WDT_CLK.
100 = 2^12 * WDT_CLK.
101 = 2^14 * WDT_CLK.
110 = 2^16 * WDT_CLK.
111 = 2^18 * WDT_CLK.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)
0 = ICE debug mode acknowledgement affects WDT counting.
WDT up counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 11454 of file Mini58Series.h.

◆ CTL [8/8]

__IO uint32_t WWDT_T::CTL

CTL

Offset: 0x04 WWDT Control Register

Bits Field Descriptions
[0] WWDTEN WWDT Enable Bit
Set this bit to enable WWDT counter counting.
0 = WWDT counter is stopped.
1 = WWDT counter is starting counting.
[1] INTEN WWDT Interrupt Enable Bit
If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
0 = WWDT counter compare match interrupt Disabled.
1 = WWDT counter compare match interrupt Enabled.
[11:8] PSCSEL WWDT Counter Prescale Period Select Bits
0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
[21:16] CMPDAT WWDT Window Compare Bits
Set this register to adjust the valid reload window.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Bit
0 = ICE debug mode acknowledgement effects WWDT counting.
WWDT down counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
WWDT down counter will keep going no matter CPU is held by ICE or not.

Definition at line 11585 of file Mini58Series.h.

◆ CTL1

__IO uint32_t I2C_T::CTL1

CTL1

Offset: 0x3C I2C Control Register 1

Bits Field Descriptions
[0] WKEN Wake-up Enable Bit
0 = I2C wake-up function Disabled.
1 = I2C wake-up function Enabled.
The system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.
Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
[1] TWOLVFIFO Two-level Buffer Enable Bit
0 = Two-level buffer Disabled.
1 = Two-level buffer Enabled.
Set to enable the two-level buffer for I2C transmitted or received buffer.
It is used to improve the performance of the I2C bus.
If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is clear.
For example: if there are 4 data shall be transmitted and then stop it.
The STO bit shall be set after the 3rd data's SI event being clear.
In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission don.
[2] NSTRETCH No Stretch On The I2C Bus
0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode.
1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode.
[3] OVIEN I2C Overrun Interrupt Control
Setting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.
0 = Overrun Interrupt Disabled.
1 = Overrun Interrupt Enabled.
[4] URIEN I2C Under Run Interrupt Control
Setting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.
0 = Under run Interrupt Disabled.
1 = Under run Interrupt Enabled.

Definition at line 4812 of file Mini58Series.h.

◆ DAT [1/3]

__I uint32_t ADC_T::DAT

DAT

Offset: 0x00 A/D Data Register

Bits Field Descriptions
[9:0] RESULT A/D Conversion Result
This field contains conversion result of ADC.
[16] OV Over Run Flag
If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1.
It is cleared by hardware after the ADC_DAT register is rea.
0 = Data in RESULT[9:0] is recent conversion result.
1 = Data in RESULT[9:0] overwrote.
[17] VALID Valid Flag
This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
0 = Data in RESULT[9:0] bits not valid.
1 = Data in RESULT[9:0] bits valid.

Definition at line 344 of file Mini58Series.h.

◆ DAT [2/3]

__IO uint32_t I2C_T::DAT

DAT

Offset: 0x08 I2C DATA Register

Bits Field Descriptions
[7:0] DAT I2C Data Register
Bit [7:0] is located with the 8-bit transferred data of the I2C serial port.

Definition at line 4615 of file Mini58Series.h.

◆ DAT [3/3]

__IO uint32_t UART_T::DAT

DAT

Offset: 0x00 UART Receive/Transmit Buffer Register

Bits Field Descriptions
[7:0] DAT Receiving/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO.
The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TX.
Read Operation:
By reading this register, the UART will return an 8-bit data received from receiving FIFO.

Definition at line 10719 of file Mini58Series.h.

◆ DATMSK

__IO uint32_t GPIO_T::DATMSK

DATMSK

Offset: 0x0C P0 Data Output Write Mask

Bits Field Descriptions
[0] DATMSK0 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] DATMSK1 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] DATMSK2 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] DATMSK3 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] DATMSK4 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] DATMSK5 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] DATMSK6 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] DATMSK7 Port 0-5 Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignore.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2077 of file Mini58Series.h.

◆ DBCTL

__IO uint32_t GPIO_DB_T::DBCTL

DBCTL

Offset: 0x180 De-bounce Cycle Control

Bits Field Descriptions
[3:0] DBCLKSEL De-bounce Sampling Cycle Selection
0000 = Sample interrupt input once per 1 clock.
0001 = Sample interrupt input once per 2 clocks.
0010 = Sample interrupt input once per 4 clocks.
0011 = Sample interrupt input once per 8 clocks.
0100 = Sample interrupt input once per 16 clocks.
0101 = Sample interrupt input once per 32 clocks.
0110 = Sample interrupt input once per 64 clocks.
0111 = Sample interrupt input once per 128 clocks.
1000 = Sample interrupt input once per 256 clocks.
1001 = Sample interrupt input once per 2*256 clocks.
1010 = Sample interrupt input once per 4*256 clocks.
1011 = Sample interrupt input once per 8*256 clocks.
1100 = Sample interrupt input once per 16*256 clocks.
1101 = Sample interrupt input once per 32*256 clocks.
1110 = Sample interrupt input once per 64*256 clocks.
1111 = Sample interrupt input once per 128*256 clocks.
[4] DBCLKSRC De-bounce Counter Clock Source Selection
0 = De-bounce counter clock source is HCLK.
1 = De-bounce counter clock source is 10 kHz internal low speed RC oscillator (LIRC).
[5] ICLKON Interrupt Clock On Mode
0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
1 = All I/O pins edge detection circuit is always active after reset.
Note: It is recommended to disable this bit to save system power if no special application concern.

Definition at line 2974 of file Mini58Series.h.

◆ DBEN

__IO uint32_t GPIO_T::DBEN

DBEN

Offset: 0x14 P0 De-bounce Enable Control

Bits Field Descriptions
[0] DBEN0 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] DBEN1 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] DBEN2 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] DBEN3 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] DBEN4 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] DBEN5 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] DBEN6 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] DBEN7 Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2305 of file Mini58Series.h.

◆ DFBA

__I uint32_t FMC_T::DFBA

DFBA

Offset: 0x14 Data Flash Base Address

Bits Field Descriptions
[31:0] DFBA Data Flash Base Address
This register indicates Data Flash start address. It is a read only register.
The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
This register is valid when DFEN (CONFIG0[0]) =0 .

Definition at line 1475 of file Mini58Series.h.

◆ DINOFF

__IO uint32_t GPIO_T::DINOFF

DINOFF

Offset: 0x04 P0 Digital Input Path Disable Control

Bits Field Descriptions
[16] DINOFF0 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[17] DINOFF1 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[18] DINOFF2 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[19] DINOFF3 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[20] DINOFF4 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[21] DINOFF5 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[22] DINOFF6 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[23] DINOFF7 Port 0-5 Pin[N] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 1857 of file Mini58Series.h.

◆ DOUT

__IO uint32_t GPIO_T::DOUT

DOUT

Offset: 0x08 P0 Data Output Value

Bits Field Descriptions
[0] DOUT0 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] DOUT1 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] DOUT2 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] DOUT3 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] DOUT4 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] DOUT5 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] DOUT6 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] DOUT7 Port 0-5 Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 1955 of file Mini58Series.h.

◆ DTCTL

__IO uint32_t PWM_T::DTCTL

DTCTL

Offset: 0x64 PWM Dead-time Control Register

Bits Field Descriptions
[7:0] DTI01 Dead-time Interval Register For Pair Of Channel0 And Channel1 (PWM0_CH0 And PWM0_CH1 Pair)
These 8 bits determine dead-time length.
The unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
[15:8] DTI23 Dead-time Interval Register For Pair Of Channel2 And Channel3 (PWM0_CH2 And PWM0_CH3 Pair)
These 8 bits determine dead-time length.
The unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
[23:16] DTI45 Dead-time Interval Register For Pair Of Channel4 And Channel5 (PWM0_CH4 And PWM0_CH5 Pair)
These 8 bits determine dead-time length.
The unit time of dead-time length is received from corresponding PWM_CLKDIV bits.

Definition at line 7275 of file Mini58Series.h.

◆ EINTSTS

__IO uint32_t TIMER_T::EINTSTS

EINTSTS

Offset: 0x18 Timer0 External Interrupt Status Register

Bits Field Descriptions
[0] CAPIF Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
0 = TMx_EXT (x= 0~1) pin interrupt did not occur.
1 = TMx_EXT (x= 0~1) pin interrupt occurred.
Note1: This bit is cleared by writing 1 to it.
Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~1) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.

Definition at line 10520 of file Mini58Series.h.

◆ EXTCTL

__IO uint32_t TIMER_T::EXTCTL

EXTCTL

Offset: 0x14 Timer0 External Control Register

Bits Field Descriptions
[0] CNTPHASE Timer External Count Phase
This bit indicates the detection phase of external counting pin TMx (x= 0~1).
0 = A falling edge of external counting pin will be counted.
1 = A rising edge of external counting pin will be counted.
[2:1] CAPEDGE Timer External Capture Pin Edge Detection
00 = A falling edge on TMx_EXT (x= 0~1) pin will be detected.
01 = A rising edge on TMx_EXT (x= 0~1) pin will be detected.
10 = Either rising or falling edge on TMx_EXT (x= 0~1) pin will be detected.
11 = Reserved.
[3] CAPEN Timer External Capture Pin Enable Bit
This bit enables the TMx_EXT pin.
0 = TMx_EXT (x= 0~1) pin Disabled.
1 = TMx_EXT (x= 0~1) pin Enabled.
[4] CAPFUNCS Capture Function Select Bit
0 = External Capture Mode Enabled.
1 = External Reset Mode Enabled.
Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~1) pin is using to save the 24-bit timer counter value to CAPDAT register.
Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~1) pin is using to reset the 24-bit timer counter value.
[5] CAPIEN Timer External Capture Interrupt Enable Bit
0 = TMx_EXT (x= 0~1) pin detection Interrupt Disabled.
1 = TMx_EXT (x= 0~1) pin detection Interrupt Enabled.
Note: CAPIEN is used to enable timer external interrupt.
If CAPIEN enabled, timer will generate an interrupt when CAPIF (TIMERx_EINTSTS[0]) is .
For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, an 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
[6] CAPDBEN Timer External Capture Pin De-bounce Enable Bit
0 = TMx_EXT (x= 0~1) pin de-bounce Disabled.
1 = TMx_EXT (x= 0~1) pin de-bounce Enabled.
Note1: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
Note2: The de-bounce circuit doesn't support ACMP output.
[7] CNTDBEN Timer Counter Pin De-bounce Enable Bit
0 = TMx (x= 0~1) pin de-bounce Disabled.
1 = TMx (x= 0~1) pin de-bounce Enabled.
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
[8] CAPSEL Capture Mode Select Bit
0 = Timer counter reset function or free-counting mode of timer capture function.
1 = Trigger-counting mode of timer capture function.
[9] ACMPSSEL ACMP Source Selection to Trigger Capture Function
For Timer 0:
0 = Capture Function source is from ACMP0 output signal for TIMER0.
1 = Capture Function source is from ACMP1 output signal for TIMER0.
For Timer 1:
0 = Capture Function source is from ACMP1 output signal for TIMER1.
1 = Capture Function source is from ACMP0 output signal for TIMER1.

Definition at line 10502 of file Mini58Series.h.

◆ EXTSMPT

__IO uint32_t ADC_T::EXTSMPT

EXTSMPT

Offset: 0x48 A/D Sampling Time Counter Register

Bits Field Descriptions
[3:0] EXTSMPT Additional ADC Sample Clock
If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal.
The default sampling time is 1 ADC clocks.
The additional clock number will be inserted to lengthen the sampling clock.
0 = Number of additional clock cycles is 0.
1 = Number of additional clock cycles is 1.
2 = Number of additional clock cycles is 2.
3 = Number of additional clock cycles is 4.
4 = Number of additional clock cycles is 8.
5 = Number of additional clock cycles is 16.
6 = Number of additional clock cycles is 32.
7 = Number of additional clock cycles is 64.
8 = Number of additional clock cycles is 128.
9 = Number of additional clock cycles is 256.
10 = Number of additional clock cycles is 512.
11 = Number of additional clock cycles is 1024.
12 = Number of additional clock cycles is 1024.
13 = Number of additional clock cycles is 1024.
14 = Number of additional clock cycles is 1024.
15 = Number of additional clock cycles is 1024.

Definition at line 567 of file Mini58Series.h.

◆ FATCTL

__IO uint32_t FMC_T::FATCTL

FATCTL

Offset: 0x18 Flash Access Time Control Register

Bits Field Descriptions
[6:4] FOM Frequency Optimization Mode (Write Protect)
The Mini58 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.
0x1 = Frequency <= 24MHz.
Others = Frequency <= 50MHz.

Definition at line 1489 of file Mini58Series.h.

◆ FIFO

__IO uint32_t UART_T::FIFO

FIFO

Offset: 0x08 UART FIFO Control Register

Bits Field Descriptions
[1] RXRST RX Field Software Reset
When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
0 = No effect.
1 = Reset RX internal state machine and pointers reset.
Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
[2] TXRST TX Field Software Reset
When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
0 = No effect.
1 = Reset TX internal state machine and pointers reset.
Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
[7:4] RFITL RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0)
When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated).
0000 = RX FIFO Interrupt Trigger Level is 1 byte.
0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
Other = Reserved.
[8] RXOFF Receiver Disable Register (Only Available In UART0)
The receiver is disabled or not (setting 1 to disable the receiver).
0 = Receiver Enabled.
1 = Receiver Disabled.
Note: This field is used for RS-485 Normal Multi-drop mode.
It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programme.
[19:16] RTSTRGLV RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0)
0000 = RTS Trigger Level is 1 byte.
0001 = RTS Trigger Level is 4 bytes.
0010 = RTS Trigger Level is 8 bytes.
0011 = RTS Trigger Level is 14 bytes.
Other = Reserved.
Note: This field is used for RTS auto-flow control.

Definition at line 10802 of file Mini58Series.h.

◆ FIFOCTL

__IO uint32_t SPI_T::FIFOCTL

FIFOCTL

Offset: 0x40 SPI FIFO Control Register

Bits Field Descriptions
[0] RXRST Clear Receive FIFO Buffer
0 = No effect.
1 = Clear receive FIFO buffer.
Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared.
[1] TXRST Clear Transmit FIFO Buffer
0 = No effect.
1 = Clear transmit FIFO buffer.
Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared.
[2] RXTHIEN Receive Threshold Interrupt Enable Bit
0 = Receive threshold interrupt Disabled.
1 = Receive threshold interrupt Enabled.
[3] TXTHIEN Transmit Threshold Interrupt Enable Bit
0 = Transmit threshold interrupt Disabled.
1 = Transmit threshold interrupt Enabled.
[6] RXOVIEN Receive FIFO Overrun Interrupt Enable Bit
0 = Receive
FIFO overrun interrupt Disabled.
1 = Receive
FIFO overrun interrupt Enabled.
[21] RXTOIEN Receive FIFO Time-out Interrupt Enable Bit
0 = Time-out interrupt Disabled.
1 = Time-out interrupt Enabled.
[25:24] RXTH Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
[29:28] TXTH Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.

Definition at line 9235 of file Mini58Series.h.

◆ FIFOSTS

__IO uint32_t UART_T::FIFOSTS

FIFOSTS

Offset: 0x18 UART FIFO Status Register

Bits Field Descriptions
[0] RXOVIF RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
0 = RX FIFO did not overflow.
1 = RX FIFO overflowed.
Note: This bit is cleared by writing 1 to it.
[3] ADDRDETF RS-485 Address Byte Detection Flag (Only Available In UART0)
This bit is set to 1 while ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode and receive detect a data with an address bit (bit 9 = 1).
Note1: This field is used for RS-485 function mode.
Note2: This bit is cleared by writing 1 to it.
[4] PEF Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
0 = No parity error is generated.
1 = Parity error is generate.
Note: This bit is read only, but can be cleared by writing '1' to it.
[5] FEF Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit follows the last data bit or parity bit is detected as logic 0).
0 = No framing error is generated.
1 = Framing error is generated.
Note: This bit is read only, but can be cleared by writing '1' to it .
[6] BIF Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
0 = No Break interrupt is generated.
1 = Break interrupt is generated.
Note: This bit is read only, but software can write 1 to clear it.
[13:8] RXPTR RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer.
When UART receives one byte from external device, RXPTR increases one.
When one byte of RX FIFO is read by CPU, RXPTR decreases on.
The Maximum value shown in RXPTR is 15.
When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 1.
[14] RXEMPTY Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
0 = RX FIFO is not empty.
1 = RX FIFO is empty.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
It will be cleared when UART receives any new data.
[15] RXFULL Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
0 = RX FIFO is not full.
1 = RX FIFO is full.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[21:16] TXPTR TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer.
When CPU writes one byte into UART_DAT, TXPTR increases one.
When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases on.
The Maximum value shown in TXPTR is 15.
When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 1.
[22] TXEMPTY Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
0 = TX FIFO is not empty.
1 = TX FIFO is empty.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
It will be cleared when writing data into THR (TX FIFO not empty).
[23] TXFULL Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
0 = TX FIFO is not full.
1 = TX FIFO is full.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[24] TXOVIF TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to
logic 1.
0 = TX FIFO did not overflow.
1 = TX FIFO overflowed.
Note: This bit is cleared by writing 1 to it.
[28] TXEMPTYF Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
0 = TX FIFO is not empty.
1 = TX FIFO is empty.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.

Definition at line 10969 of file Mini58Series.h.

◆ FUNSEL

__IO uint32_t UART_T::FUNSEL

FUNSEL

Offset: 0x30 UART Function Select Register

Bits Field Descriptions
[1:0] FUN_SEL Function Selection
00 = UART function mode.
01 = Reserved.
10 = IrDA function mode. (Only Available in UART0)
11 = RS-485 function mode. (Only Available in UART0)

Definition at line 11156 of file Mini58Series.h.

◆ IFA

__IO uint32_t PWM_T::IFA

IFA

Offset: 0x84 PWM Period Interrupt Accumulation Control Register

Bits Field Descriptions
[0] IFAEN Interrupt Accumulation Function Enable Bit
0 = Interrupt accumulation function Disabled.
1 = Interrupt accumulation function Enabled.
[7:4] IFCNT Interrupt Accumulation Counter
When IFAEN is set, IFCNT will decrease when every ZIFn flag is set and when IFCNT reach to zero, the PWMn interrupt will occurred and IFCNT will reload itself.

Definition at line 7822 of file Mini58Series.h.

◆ INTEN [1/3]

__IO uint32_t GPIO_T::INTEN

INTEN

Offset: 0x1C P0 Interrupt Enable Control

Bits Field Descriptions
[0] FLIEN0 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] FLIEN1 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] FLIEN2 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] FLIEN3 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] FLIEN4 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] FLIEN5 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] FLIEN6 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] FLIEN7 Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1function
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[16] RHIEN0 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[17] RHIEN1 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[18] RHIEN2 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[19] RHIEN3 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[20] RHIEN4 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[21] RHIEN5 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[22] RHIEN6 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[23] RHIEN7 Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2701 of file Mini58Series.h.

◆ INTEN [2/3]

__IO uint32_t PWM_T::INTEN

INTEN

Offset: 0x54 PWM Interrupt Enable Register

Bits Field Descriptions
[5:0] ZIEN0 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[5:0] ZIEN1 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[5:0] ZIEN2 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[5:0] ZIEN3 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[5:0] ZIEN4 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[5:0] ZIEN5 PWM Zero Point Interrupt Enable Bit
0 = PWM0_CHn zero point interrupt Disabled.
1 = PWM0_CHn zero point interrupt Enabled.
[13:8] CMPDIEN0 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[13:8] CMPDIEN1 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[13:8] CMPDIEN2 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[13:8] CMPDIEN3 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[13:8] CMPDIEN4 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[13:8] CMPDIEN5 PWM Compare Down Interrupt Enable Bit
0 = PWM0_CHn compare down interrupt Disabled.
1 = PWM0_CHn compare down interrupt Enabled.
[16] BRKIEN Fault Brake0 And Fault Brake1 Interrupt Enable Bit
0 = BRKIF0 and BRKIF1 trigger PWM interrupt Disabled.
1 = BRKIF0 and BRKIF1 trigger PWM interrupt Enabled.
[17] PINTTYPE PWM Interrupt Type Selection
0 = ZIFn will be set if PWM counter underflows.
1 = ZIFn will be set if PWM counter matches PERIODn register.
Note: This bit is effective when PWM is in center-aligned type only.
[23:18] PIEN0 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[23:18] PIEN1 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[23:18] PIEN2 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[23:18] PIEN3 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[23:18] PIEN4 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[23:18] PIEN5 PWM Period Interrupt Enable Bit
0 = PWM0_CHn period interrupt Disabled.
1 = PWM0_CHn period interrupt Enabled.
[29:24] CMPUIEN0 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.
[29:24] CMPUIEN1 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.
[29:24] CMPUIEN2 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.
[29:24] CMPUIEN3 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.
[29:24] CMPUIEN4 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.
[29:24] CMPUIEN5 PWM Compare Up Interrupt Enable Bit
0 = PWM0_CHn compare up interrupt Disabled.
1 = PWM0_CHn compare up interrupt Enabled.

Definition at line 7076 of file Mini58Series.h.

◆ INTEN [3/3]

__IO uint32_t UART_T::INTEN

INTEN

Offset: 0x04 UART Interrupt Enable Register

Bits Field Descriptions
[0] RDAIEN Receive Data Available Interrupt Enable Bit
0 = RDAINT Masked off.
1 = RDAINT Enabled.
[1] THREIEN Transmit Holding Register Empty Interrupt Enable Bit
0 = THREINT Masked off.
1 = THREINT Enabled.
[2] RLSIEN Receive Line Status Interrupt Enable Bit
0 = RLSINT Masked off.
1 = RLSINT Enabled.
[3] MODEMIEN Modem Status Interrupt Enable Bit
0 = MODEMINT Masked off.
1 = MODEMINT Enabled.
[4] RXTOIEN RX Time-out Interrupt Enable Bit
0 = RXTOINT Masked off.
1 = RXTOINT Enabled.
[5] BUFERRIEN Buffer Error Interrupt Enable Bit
0 = Buffer Error Interrupt Masked Disabled.
1 = Buffer Error Interrupt Masked Enabled.
[9] WKCTSIEN Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0)
0 = UART wake-up function Disabled.
1 = UART Wake-up function Enabled.
Note: When the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
[11] TOCNTEN Time-out Counter Enable Bit
0 = Time-out counter Disabled.
1 = Time-out counter Enabled.
[12] ATORTSEN RTS Auto Flow Control Enable Bit (Only Available In UART0)
0 = RTS auto flow control Disabled.
1 = RTS auto flow control Enabled.
Note: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal.
[13] ATOCTSEN CTS Auto Flow Control Enable Bit (Only Available In UART0)
0 = CTS auto flow control Disabled.
1 = CTS auto flow control Enabled.
Note: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).

Definition at line 10762 of file Mini58Series.h.

◆ INTSRC

__IO uint32_t GPIO_T::INTSRC

INTSRC

Offset: 0x20 P0 Interrupt Source Flag

Bits Field Descriptions
[0] INTSRC0 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] INTSRC1 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] INTSRC2 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] INTSRC3 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] INTSRC4 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] INTSRC5 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] INTSRC6 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] INTSRC7 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[8] INTSRC8 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[9] INTSRC9 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[10] INTSRC10 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[11] INTSRC11 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[12] INTSRC12 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[13] INTSRC13 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[14] INTSRC14 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[15] INTSRC15 Port 0-5 Pin[N] Interrupt Source Flag
Write Operation:
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation:
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2935 of file Mini58Series.h.

◆ INTSTS [1/3]

__IO uint32_t PWM_T::INTSTS

INTSTS

Offset: 0x58 PWM Interrupt Status Register

Bits Field Descriptions
[5:0] ZIF0 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[5:0] ZIF1 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[5:0] ZIF2 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[5:0] ZIF3 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[5:0] ZIF4 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[5:0] ZIF5 PWM Zero Point Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches zero point.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF0 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF1 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF2 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF3 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF4 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[13:8] CMPDIF5 PWM Compare Down Interrupt Flag
Flag is set by hardware when PWMn counter down count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[16] BRKIF0 PWM Brake0 Flag
0 = PWM Brake does not recognize a falling signal at BKP0.
1 = When PWM Brake detects a falling signal at pin BKP0; this flag will be set to high.
Note: This bit can be cleared by software writing 1.
[17] BRKIF1 PWM Brake1 Flag
0 = PWM Brake does not recognize a falling signal at BKP1.
1 = When PWM Brake detects a falling signal at pin BKP1; this flag will be set to high.
Note: This bit can be cleared by software writing 1.
[23:18] PIF0 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[23:18] PIF1 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[23:18] PIF2 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[23:18] PIF3 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[23:18] PIF4 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[23:18] PIF5 PWM Period Interrupt Flag
Flag is set by hardware when PWM0_CHn counter reaches PERIODn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF0 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF1 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF2 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF3 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF4 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.
[29:24] CMPUIF5 PWM Compare Up Interrupt Flag
Flag is set by hardware when PWM0_CHn counter up count reaches CMPn.
Note: This bit can be cleared by software writing 1.

Definition at line 7166 of file Mini58Series.h.

◆ INTSTS [2/3]

__IO uint32_t TIMER_T::INTSTS

INTSTS

Offset: 0x08 Timer0 Interrupt Status Register

Bits Field Descriptions
[0] TIF Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
0 = No effect.
1 = CNT value matches the CMPDAT value.
Note: This bit is cleared by writing 1 to it.
[1] TWKF Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
0 = Timer does not cause CPU wake-up.
1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
Note: This bit is cleared by writing 1 to it.

Definition at line 10423 of file Mini58Series.h.

◆ INTSTS [3/3]

__IO uint32_t UART_T::INTSTS

INTSTS

Offset: 0x1C UART Interrupt Status Register

Bits Field Descriptions
[0] RDAIF Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set.
If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generate.
0 = No RDA interrupt flag is generated.
1 = RDA interrupt flag is generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4])).
[1] THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generate.
0 = No THRE interrupt flag is generated.
1 = THRE interrupt flag is generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
[2] RLSIF Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generate.
0 = No RLS interrupt flag is generated.
1 = RLS interrupt flag is generated.
Note1: In RS-485 function mode, this field is set including "receiver detects and receives address byte character (bit 9 = 1) bit".
At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
(Only Available in UART0).
Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
(Only Available in UART0).
[3] MODEMIF MODEM Interrupt Flag (Read Only) (Only Available In UART0)
This bit is set when the CTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1).
If MODEMIEN (UART_INTEN[3]) is enabled, the Modem interrupt will be generate.
0 = No Modem interrupt flag is generated.
1 = Modem interrupt flag is generated.
Note: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]).
[4] RXTOIF Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]).
If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generate.
0 = No Time-out interrupt flag is generated.
1 = Time-out interrupt flag is generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
[5] BUFERRIF Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24]) or RXOVIF(UART_FIFOSTS[0])) is set.
When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct.
If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generate.
0 = No buffer error interrupt flag is generated.
1 = Buffer error interrupt flag is generated.
Note: This bit is read only and reset to 0 when all bits of TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
[8] RDAINT Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
0 = No RDA interrupt is generated.
1 = RDA interrupt is generated.
[9] THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.
0 = No THRE interrupt is generated.
1 = THRE interrupt is generated.
[10] RLSINT Receive Line Status Interrupt (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.
0 = No RLS interrupt is generated.
1 = RLS interrupt is generated.
[11] MODEMINT MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1.
0 = No Modem interrupt is generated.
1 = Modem interrupt is generated.
[12] RXTOINT Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.
0 = No Time-out interrupt is generated.
1 = Time-out interrupt is generated.
[13] BUFERRINT Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1.
0 = No buffer error interrupt is generated.
1 = buffer error interrupt is generated.
[16] CTSWKIF NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0)
0 = Chip stays in power-down state.
1 = Chip wake-up from power-down state by nCTS wake-up.
Note1: If WKCTSIEN (UART_IER[9])is enabled, the wake-up interrupt is generated.
Note2: This bit is read only, but can be cleared by writing '1' to it.

Definition at line 11049 of file Mini58Series.h.

◆ INTTYPE

__IO uint32_t GPIO_T::INTTYPE

INTTYPE

Offset: 0x18 P0 Interrupt Mode Control

Bits Field Descriptions
[0] TYPE0 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] TYPE1 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] TYPE2 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] TYPE3 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] TYPE4 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] TYPE5 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] TYPE6 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] TYPE7 Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignore.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2451 of file Mini58Series.h.

◆ IPRST0

__IO uint32_t SYS_T::IPRST0

IPRST0

Offset: 0x08 Peripheral Reset Control Register 0

Bits Field Descriptions
[0] CHIPRST CHIP One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is the same as the POR reset, all the chip controllers is reset and the chip settings from flash are also reload.
0 = Chip normal operation.
1 = CHIP one-shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] CPURST Processor Core One-shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles.
0 = Processor core normal operation.
1 = Processor core one-shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 9545 of file Mini58Series.h.

◆ IPRST1

__IO uint32_t SYS_T::IPRST1

IPRST1

Offset: 0x0C Peripheral Reset Control Register 1

Bits Field Descriptions
[1] GPIORST GPIO (P0~P5) Controller Reset
0 = GPIO controller normal operation.
1 = GPIO controller reset.
[2] TMR0RST Timer0 Controller Reset
0 = Timer0 controller normal operation.
1 = Timer0 controller reset.
[3] TMR1RST Timer1 Controller Reset
0 = Timer1 controller normal operation.
1 = Timer1 controller reset.
[8] I2C0RST I2C0 Controller Reset
0 = I2C0 controller normal operation.
1 = I2C0 controller reset.
[9] I2C1RST I2C1 Controller Reset
0 = I2C1 controller normal operation.
1 = I2C1 controller reset.
[12] SPI0RST SPI0 Controller Reset
0 = SPI controller normal operation.
1 = SPI controller reset.
[16] UART0RST UART0 Controller Reset
0 = UART0 controller normal operation.
1 = UART0 controller reset.
[17] UART1RST UART1 Controller Reset
0 = UART1 controller normal operation.
1 = UART1 controller reset.
[20] PWM0RST PWM0 Controller Reset
0 = PWM0 controller normal operation.
1 = PWM0 controller reset.
[22] ACMPRST ACMP Controller Reset
0 = ACMP controller normal operation.
1 = ACMP controller reset.
[28] ADCRST ADC Controller Reset
0 = ADC controller normal operation.
1 = ADC controller reset.

Definition at line 9588 of file Mini58Series.h.

◆ IRCTCTL

__IO uint32_t SYS_T::IRCTCTL

IRCTCTL

Offset: 0x80 HIRC Trim Control Register

Bits Field Descriptions
[0] FREQSEL Trim Frequency Select Bit
This bit is to enable the HIRC auto trim.
When setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.
During auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.
0 = HIRC auto trim function Disabled.
1 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz.
[5:4] LOOPSEL Trim Calculation Loop
This field defines trim value calculation based on the number of LXT clock.
For example, if LOOPSEL is set as "00", auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clocks.
This field also defines how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC is locked.
Once the HIRC is locked, the internal trim value update counter will be reset.
If the trim value update counter reaches this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0.
00 = Trim value calculation is based on average difference in 4 LXT clock and trim retry count limitation is 64.
01 = Trim value calculation is based on average difference in 8 LXT clock and trim retry count limitation is 128.
10 = Trim value calculation is based on average difference in 16 LXT clock and trim retry count limitation is 256.
11 = Trim value calculation is based on average difference in 32 LXT clock and trim retry count limitation is 512.

Definition at line 9974 of file Mini58Series.h.

◆ IRCTIEN

__IO uint32_t SYS_T::IRCTIEN

IRCTIEN

Offset: 0x84 HIRC Trim Interrupt Enable Register

Bits Field Descriptions
[1] TFAILIEN Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by FREQSEL (SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF (SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached.
0 = TFAILIF (SYS_IRCTISTS[1]) status Disabled to trigger an interrupt to CPU.
1 = TFAILIF (SYS_IRCTISTS[1]) status Enabled to trigger an interrupt to CPU.
[2] CLKEIEN LXT Clock Error Interrupt Enable Bit
This bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.
If this bit is high, and CLKERRIF (SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.
0 = CLKERRIF (SYS_IRCTISTS[2]) status Disabled to trigger an interrupt to CPU.
1 = CLKERRIF (SYS_IRCTISTS[2]) status Enabled to trigger an interrupt to CPU.

Definition at line 9994 of file Mini58Series.h.

◆ IRCTISTS

__IO uint32_t SYS_T::IRCTISTS

IRCTISTS

Offset: 0x88 HIRC Trim Interrupt Status Register

Bits Field Descriptions
[0] FREQLOCK HIRC Frequency Lock Status
This bit indicates the HIRC frequency locked in 22.1184 MHz.
This is a read only status bit and doesn't trigger any interrupt.
[1] TFAILIF Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock.
Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[1:0]) will be cleared to 0 by hardware automatically.
If this bit is set and TFAILIEN (SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
Software can write 1 to clear this bit to .
0 = Trim value update limitation count is not reached.
1 = Trim value update limitation count is reached and HIRC frequency is still not locked.
[2] CLKERRIF LXT Clock Error Interrupt Status
This bit indicates that LXT clock frequency is inaccuracy.
Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[0]) will be cleared to 0 by hardware automatically.
If this bit is set and CLKEIEN (SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy.
Software can write 1 to clear this bit to .
0 = LXT clock frequency is accuracy.
1 = LXT clock frequency is inaccuracy.

Definition at line 10021 of file Mini58Series.h.

◆ IRDA

__IO uint32_t UART_T::IRDA

IRDA

Offset: 0x28 UART IrDA Control Register

Bits Field Descriptions
[1] TXEN IrDA Receiver/Transmitter Selection Enable Bit
0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
1 = IrDA Transmitter Enabled and Receiver Disabled.
[5] TXINV IrDA Inverse Transmitting Output Signal
0 = None inverse transmitting signal. (Default)
1 = Inverse transmitting output signal.
[6] RXINV IrDA Inverse Receive Input Signal
0 = None inverse receiving input signal.
1 = Inverse receiving input signal. (Default)

Definition at line 11111 of file Mini58Series.h.

◆ IRQ

__IO uint32_t INTR_T::IRQ

IRQ

Offset: 0x84 MCU IRQ Number Identity Register

Bits Field Descriptions
[31:0] MCU_IRQ MCU IRQ Source Bits
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core.
There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mod.
The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.
When the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].
When the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.

Definition at line 5278 of file Mini58Series.h.

◆ IRQ0_SRC

__I uint32_t INTR_T::IRQ0_SRC

IRQ0_SRC

Offset: 0x00 IRQ0 (BOD) Interrupt Source Identity

Bits Field Descriptions
[0] BOD_INT IRQ0 Source Identity
0 = IRQ0 source is not from BOD interrupt (BOD_INT).
1 = IRQ0 source is from BOD interrupt (BOD_INT).

Definition at line 4970 of file Mini58Series.h.

◆ IRQ12_SRC

__I uint32_t INTR_T::IRQ12_SRC

IRQ12_SRC

Offset: 0x30 IRQ12 (UART0) Interrupt Source Identity

Bits Field Descriptions
[0] UART0_INT IRQ12 Source Identity
0 = IRQ12 source is not from UART0 interrupt (UART0_INT).
1 = IRQ12 source is from UART0 interrupt (UART0_INT).

Definition at line 5116 of file Mini58Series.h.

◆ IRQ13_SRC

__I uint32_t INTR_T::IRQ13_SRC

IRQ13_SRC

Offset: 0x34 IRQ13 (UART1) Interrupt Source Identity

Bits Field Descriptions
[0] UART1_INT IRQ13 Source Identity
0 = IRQ13 source is not from UART1 interrupt (UART1_INT).
1 = IRQ13 source is from UART1 interrupt (UART1_INT).

Definition at line 5129 of file Mini58Series.h.

◆ IRQ14_SRC

__I uint32_t INTR_T::IRQ14_SRC

IRQ14_SRC

Offset: 0x38 IRQ14 (SPI) Interrupt Source Identity

Bits Field Descriptions
[0] SPI_INT IRQ14 Source Identity
0 = IRQ14 source is not from SPI interrupt (SPI_INT).
1 = IRQ14 source is from SPI interrupt (SPI_INT).

Definition at line 5142 of file Mini58Series.h.

◆ IRQ16_SRC

__I uint32_t INTR_T::IRQ16_SRC

IRQ16_SRC

Offset: 0x40 IRQ16 (GP5) Interrupt Source Identity

Bits Field Descriptions
[0] GP5_INT IRQ16 Source Identity
0 = IRQ16 source is not from GP5 interrupt (GP5_INT).
1 = IRQ16 source is from GP5 interrupt (GP5_INT).

Definition at line 5159 of file Mini58Series.h.

◆ IRQ17_SRC

__I uint32_t INTR_T::IRQ17_SRC

IRQ17_SRC

Offset: 0x44 IRQ17 (HIRC trim) Interrupt Source Identity

Bits Field Descriptions
[0] HIRC_TRIM_INT IRQ17 Source Identity
0 = IRQ17 source is not from HIRC trim interrupt (HIRC_TRIM_INT).
1 = IRQ17 source is from HIRC trim interrupt (HIRC_TRIM_INT).

Definition at line 5172 of file Mini58Series.h.

◆ IRQ18_SRC

__I uint32_t INTR_T::IRQ18_SRC

IRQ18_SRC

Offset: 0x48 IRQ18 (I2C0) Interrupt Source Identity

Bits Field Descriptions
[0] I2C0_INT IRQ18 Source Identity
0 = IRQ18 source is not from I2C0 interrupt (I2C0_INT).
1 = IRQ18 source is from I2C0 interrupt (I2C0_INT).

Definition at line 5185 of file Mini58Series.h.

◆ IRQ19_SRC

__I uint32_t INTR_T::IRQ19_SRC

IRQ19_SRC

Offset: 0x4C IRQ19 (I2C1) Interrupt Source Identity

Bits Field Descriptions
[0] I2C1_INT IRQ19 Source Identity
0 = IRQ19 source is not from I2C1 interrupt (I2C1_INT).
1 = IRQ19 source is from I2C1 interrupt (I2C1_INT).

Definition at line 5198 of file Mini58Series.h.

◆ IRQ1_SRC

__I uint32_t INTR_T::IRQ1_SRC

IRQ1_SRC

Offset: 0x04 IRQ1 (WDT) Interrupt Source Identity

Bits Field Descriptions
[0] WDT_INT IRQ1 Source Identity
0 = IRQ1 source is not from watchdog interrupt (WDT _INT).
1 = IRQ1 source is from watchdog interrupt (WDT_INT).
[1] WWDT_INT IRQ1 Source Identity
0 = IRQ1 source is not from window watchdog interrupt (WWDT _INT).
1 = IRQ1 source is from window watchdog interrupt (WWDT_INT).

Definition at line 4986 of file Mini58Series.h.

◆ IRQ25_SRC

__I uint32_t INTR_T::IRQ25_SRC

IRQ25_SRC

Offset: 0x64 IRQ25 (ACMP) Interrupt Source Identity

Bits Field Descriptions
[0] ACMP_INT IRQ25 Source Identity
0 = IRQ25 source is not from ACMP interrupt (ACMP_INT).
1 = IRQ25 source is from ACMP interrupt (ACMP_INT).

Definition at line 5215 of file Mini58Series.h.

◆ IRQ28_SRC

__I uint32_t INTR_T::IRQ28_SRC

IRQ28_SRC

Offset: 0x70 IRQ28 (PWRWU) Interrupt Source Identity

Bits Field Descriptions
[0] PWRWU_INT IRQ28 Source Identity
0 = IRQ28 source is not from PWRWU interrupt (PWRWU_INT).
1 = IRQ28 source is from PWREU interrupt (PWRWU_INT).

Definition at line 5232 of file Mini58Series.h.

◆ IRQ29_SRC

__I uint32_t INTR_T::IRQ29_SRC

IRQ29_SRC

Offset: 0x74 IRQ29 (ADC) Interrupt Source Identity

Bits Field Descriptions
[0] ADC_INT IRQ29 Source Identity
0 = IRQ29 source is not from ADC interrupt (ADC_INT).
1 = IRQ29 source is from ADC interrupt (ADC_INT).

Definition at line 5245 of file Mini58Series.h.

◆ IRQ2_SRC

__I uint32_t INTR_T::IRQ2_SRC

IRQ2_SRC

Offset: 0x08 IRQ2 (EINT0) Interrupt Source Identity

Bits Field Descriptions
[0] EINT0 IRQ2 Source Identity
0 = IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0).
1 = IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0).

Definition at line 4999 of file Mini58Series.h.

◆ IRQ3_SRC

__I uint32_t INTR_T::IRQ3_SRC

IRQ3_SRC

Offset: 0x0C IRQ3 (EINT1) Interrupt Source Identity

Bits Field Descriptions
[0] EINT1 IRQ3 Source Identity
0 = IRQ3 source is not from external signal interrupt 1 from P5.2 (EINT1).
1 = IRQ3 source is from external signal interrupt 1 from P5.2 (EINT1).

Definition at line 5012 of file Mini58Series.h.

◆ IRQ4_SRC

__I uint32_t INTR_T::IRQ4_SRC

IRQ4_SRC

Offset: 0x10 IRQ4 (GP0/1) Interrupt Source Identity

Bits Field Descriptions
[0] GP0_INT IRQ4 Source Identity
0 = IRQ4 source is not from GP0 interrupt (GP0_INT).
1 = IRQ4 source is from GP0 interrupt (GP0_INT).
[1] GP1_INT IRQ4 Source Identity
0 = IRQ4 source is not from GP1 interrupt (GP1_INT).
1 = IRQ4 source is from GP1 interrupt (GP1_INT).

Definition at line 5028 of file Mini58Series.h.

◆ IRQ5_SRC

__I uint32_t INTR_T::IRQ5_SRC

IRQ5_SRC

Offset: 0x14 IRQ5 (GP2/3/4) Interrupt Source Identity

Bits Field Descriptions
[0] GP2_INT IRQ5 Source Identity
0 = IRQ5 source is not from GP2 interrupt (GP2_INT).
1 = IRQ5 source is from GP2 interrupt (GP2_INT).
[1] GP3_INT IRQ5 Source Identity
0 = IRQ5 source is not from GP3 interrupt (GP3_INT).
1 = IRQ5 source is from GP3 interrupt (GP3_INT).
[2] GP4_INT IRQ5 Source Identity
0 = IRQ5 source is not from GP4 interrupt (GP4_INT).
1 = IRQ5 source is from GP4 interrupt (GP4_INT).

Definition at line 5047 of file Mini58Series.h.

◆ IRQ6_SRC

__I uint32_t INTR_T::IRQ6_SRC

IRQ6_SRC

Offset: 0x18 IRQ6 (PWM) Interrupt Source Identity

Bits Field Descriptions
[0] PWM_INT IRQ6 Source Identity
0 = IRQ6 source is not from PWM interrupt (PWM_INT).
1 = IRQ6 source is from PWM interrupt (PWM_INT).

Definition at line 5060 of file Mini58Series.h.

◆ IRQ7_SRC

__I uint32_t INTR_T::IRQ7_SRC

IRQ7_SRC

Offset: 0x1C IRQ7 (BRAKE) Interrupt Source Identity

Bits Field Descriptions
[0] BRAKE_INT IRQ7 Source Identity
0 = IRQ7 source is not from Brake interrupt (BRAKE_INT).
1 = IRQ7 source is from Brake interrupt (BRAKE_INT).

Definition at line 5073 of file Mini58Series.h.

◆ IRQ8_SRC

__I uint32_t INTR_T::IRQ8_SRC

IRQ8_SRC

Offset: 0x20 IRQ8 (TMR0) Interrupt Source Identity

Bits Field Descriptions
[0] TMR0_INT IRQ8 Source Identity
0 = IRQ8 source is not from Timer0 interrupt (TMR0_INT).
1 = IRQ8 source is from Timer0 interrupt (TMR0_INT).

Definition at line 5086 of file Mini58Series.h.

◆ IRQ9_SRC

__I uint32_t INTR_T::IRQ9_SRC

IRQ9_SRC

Offset: 0x24 IRQ9 (TMR1) Interrupt Source Identity

Bits Field Descriptions
[0] TMR1_INT IRQ9 Source Identity
0 = IRQ9 source is not from Timer1 interrupt (TMR1_INT).
1 = IRQ9 source is from Timer1 interrupt (TMR1_INT).

Definition at line 5099 of file Mini58Series.h.

◆ ISPADDR

__IO uint32_t FMC_T::ISPADDR

ISPADDR

Offset: 0x04 ISP Address Register

Bits Field Descriptions
[31:0] ISPADDR ISP Address
The Mini58 series is equipped with embedded flash.
ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.

Definition at line 1409 of file Mini58Series.h.

◆ ISPCMD

__IO uint32_t FMC_T::ISPCMD

ISPCMD

Offset: 0x0C ISP Command Register

Bits Field Descriptions
[6:0] CMD ISP CMD
ISP command table is shown below:
0x00= FLASH Read.
0x04= Read Unique ID.
0x0B= Read Company ID.
0x0C= Read Device ID.
0x0D= Read CRC32 Checksum.
0x21= FLASH 32-bit Program.
0x22= FLASH Page Erase.
0x2D= Run CRC32 Checksum Calculation.
0x2E= Vector Remap.
The other commands are invalid.

Definition at line 1447 of file Mini58Series.h.

◆ ISPCTL

__IO uint32_t FMC_T::ISPCTL

ISPCTL

Offset: 0x00 ISP Control Register

Bits Field Descriptions
[0] ISPEN ISP Enable Bit (Write Protect)
Set this bit to enable the ISP function.
0 = ISP function Disabled.
1 = ISP function Enabled.
[1] BS Boot Select (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively.
This bit also functions as chip booting status flag, which can be used to check where chip booted from.
This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
0 = Booting from APROM.
1 = Booting from LDROM.
[2] SPUEN SPROM Update Enable Bit (Write Protect)
0 = SPROM cannot be updated.
1 = SPROM can be updated.
[3] APUEN APROM Update Enable Bit (Write Protect)
0 = APROM cannot be updated when the chip runs in APROM.
1 = APROM can be updated when the chip runs in APROM.
[4] CFGUEN CONFIG Update Enable Bit (Write Protect)
0 = CONFIG cannot be updated.
1 = CONFIG can be updated.
[5] LDUEN LDROM Update Enable (Write Protect)
LDROM update enable bit.
0 = LDROM cannot be updated.
1 = LDROM can be updated.
[6] ISPFF ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0.
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection.
(7) Erase or Program command at brown-out detected.
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands.

Definition at line 1394 of file Mini58Series.h.

◆ ISPDAT

__IO uint32_t FMC_T::ISPDAT

ISPDAT

Offset: 0x08 ISP Data Register

Bits Field Descriptions
[31:0] ISPDAT ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment.
For ISP Read Checksum command, ISPDAT is the checksum result.
If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect.

Definition at line 1425 of file Mini58Series.h.

◆ ISPSTS

__I uint32_t FMC_T::ISPSTS

ISPSTS

Offset: 0x40 ISP Status Register

Bits Field Descriptions
[0] ISPBUSY ISP BUSY (Read Only)
0 = ISP operation is finished.
1 = ISP operation is busy.
[2:1] CBS Boot Selection Of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
00 = LDROM with IAP mode.
01 = LDROM without IAP mode.
10 = APROM with IAP mode.
11 = APROM without IAP mode.
[6] ISPFF ISP Fail Flag (Write Protect)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0.
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection.
(7) Erase or Program command at brown-out detected.
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands.
[20:9] VECMAP Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
[31] SCODE Security Code Active Flag
This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation.
0 = SPROM secured code is inactive.
1 = SPROM secured code is active.

Definition at line 1530 of file Mini58Series.h.

◆ ISPTRG

__IO uint32_t FMC_T::ISPTRG

ISPTRG

Offset: 0x10 ISP Trigger Control Register

Bits Field Descriptions
[0] ISPGO ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0 = ISP operation is finished.
1 = ISP is progressed.

Definition at line 1461 of file Mini58Series.h.

◆ LINE

__IO uint32_t UART_T::LINE

LINE

Offset: 0x0C UART Line Control Register

Bits Field Descriptions
[1:0] WLS Word Length Select Bit
00 = Word length is 5-bit.
01 = Word length is 6-bit.
10 = Word length is 7-bit.
11 = Word length is 8-bit.
[2] NSB Number of "STOP Bit"
0 = One "STOP bit" is generated in the transmitted data.
1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
[3] PBE Parity Bit Enable Bit
0 = No parity bit.
1 = Parity bit is generated on each outgoing character and is checked on each incoming data.
[4] EPE Even Parity Enable Bit
0 = Odd number of logic 1's is transmitted and checked in each word.
1 = Even number of logic 1's is transmitted and checked in each word.
This bit has effect only when PBE (UART_LINE[3]) is set.
[5] SPE Stick Parity Enable Bit
0 = Stick parity Disabled.
1 = If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as .
[6] BCB Break Control Bit
When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
This bit acts only on TX and has no effect on the transmitter logic.
0 = Break control Disabled.
1 = Break control Enabled.

Definition at line 10837 of file Mini58Series.h.

◆ MODE

__IO uint32_t GPIO_T::MODE

MODE

Offset: 0x00 P0 I/O Mode Control

Bits Field Descriptions
[1:0] MODE0 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3:2] MODE1 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5:4] MODE2 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7:6] MODE3 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[9:8] MODE4 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[11:10] MODE5 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[13:12] MODE6 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[15:14] MODE7 Port 0-5 I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (Config0[10]).
If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 1751 of file Mini58Series.h.

◆ MODEM

__IO uint32_t UART_T::MODEM

MODEM

Offset: 0x10 UART Modem Control Register

Bits Field Descriptions
[1] RTS RTS (Request-to-send) Signal Control
This bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration.
0 = RTS signal is active.
1 = RTS signal is inactive.
Note1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.
Note2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
[9] RTSACTLV RTS Pin Active Level
This bit defines the active level state of RTS pin output.
0 = RTS pin output is high level active.
1 = RTS pin output is low level active. (Default)
Note1: Refer to Figure 6.10-13 and Figure 6.10-14 UART function mode.
Note2: Refer to Figure 6.10-17 and Figure 6.10-18 for RS-485 function mode.
[13] RTSSTS RTS Pin State (Read Only)
This bit mirror from RTS pin output of voltage logic status.
0 = RTS pin output is low level voltage logic state.
1 = RTS pin output is high level voltage logic state.

Definition at line 10863 of file Mini58Series.h.

◆ MODEMSTS

__IO uint32_t UART_T::MODEMSTS

MODEMSTS

Offset: 0x14 UART Modem Status Register

Bits Field Descriptions
[0] CTSDETF Detect CTS State Change Flag
This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
0 = CTS input has not change state.
1 = CTS input has change state.
Note: This bit is cleared by writing 1 to it.
[4] CTSSTS CTS Pin Status (Read Only)
This bit mirror from CTS pin input of voltage logic status.
0 = CTS pin input is low level voltage logic state.
1 = CTS pin input is high level voltage logic state.
Note: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
[8] CTSACTLV CTS Pin Active Level
This bit defines the active level state of CTS pin input.
0 = CTS pin input is high level active.
1 = CTS pin input is low level active. (Default)

Definition at line 10887 of file Mini58Series.h.

◆ MSKALIGN

__IO uint32_t PWM_T::MSKALIGN

MSKALIGN

Offset: 0x8C PWM Phase Change Mask Aligned Register

Bits Field Descriptions
[5:0] MSKDAT0 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT1 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT2 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT3 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT4 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT5 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[13:8] MSKEN0 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN1 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN2 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN3 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN4 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN5 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[21:16] ALIGNn PWM0_CHn Output Mask Aligned Enable Bit
0 = PWM0_CHn output will mask immediately when mask function enabled.
1 = PWM0_CHn output will mask when output aligned to PWM period.

Definition at line 7890 of file Mini58Series.h.

◆ P0_MFP

__IO uint32_t SYS_T::P0_MFP

P0_MFP

Offset: 0x30 P0 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P0 Multiple Function Select Bit
The pin function of P0 depends on MFP and ALT.
Refer to ALT Description for details.
[8] ALT0 P0.0 Alternate Function Select Bit
Bits ALT[0] (SYS_P0_MFP[8]), and MFP[0] (SYS_P0_MFP[0]) determine the P0.0 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = UART0_nCTS function is selected.
(1, 1) = UART0_TXD function is selected.
[9] ALT1 P0.1 Alternate Function Select Bit
Bits ALT[1] (SYS_P0_MFP[9]), and MFP[1] (SYS_P0_MFP[1]) determine the P0.1 function.
(0, 0) = GPIO function is selected.
(0, 1) = SPI0_SS function is selected.
(1, 0) = UART0_nRTS function is selected.
(1, 1) = UART0_RXD function is selected.
[12] ALT4 P0.4 Alternate Function Select Bit
Bits ALT[4] (SYS_P0_MFP[12]), and MFP[4] (SYS_P0_MFP[4]) determine the P0.4 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = SPI0_SS function is selected.
(1, 1) = PWM0_CH5 function is selected.
[13] ALT5 P0.5 Alternate Function Select Bit
Bits ALT[5] (SYS_P0_MFP[13]), and MFP[5] (SYS_P0_MFP[5]) determine the P0.5 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = SPI0_MOSI function is selected.
(1, 1) = PWM0_CH4 function is selected.
[14] ALT6 P0.6 Alternate Function Select Bit
Bits ALT[6] (SYS_P0_MFP[14]), and MFP[6] (SYS_P0_MFP[6]) determine the P0.6 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = SPI0_MISO function is selected.
(1, 1) = PWM0_CH1 function is selected.
[15] ALT7 P0.7 Alternate Function Select Bit
Bits ALT[7] (SYS_P0_MFP[15]), and MFP[7] (SYS_P0_MFP[7]) determine the P0.7 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = SPI0_CLK function is selected.
(1, 1) = PWM0_CH0 function is selected.
[23:16] TYPE P0[7:0] Input Schmitt Trigger Function Enable Bits
0 = P0[7:0] I/O input Schmitt Trigger function Disabled.
1 = P0[7:0] I/O input Schmitt Trigger function Enabled.

Definition at line 9690 of file Mini58Series.h.

◆ P1_MFP

__IO uint32_t SYS_T::P1_MFP

P1_MFP

Offset: 0x34 P1 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P1 Multiple Function Select Bit
The pin function of P1 depends on MFP and ALT.
Refer to ALT Description for details.
[8] ALT0 P1.0 Alternate Function Select Bit
Bits ALT[0] (SYS_P1_MFP[8]), and MFP[0] (SYS_P1_MFP[0]) determine the P1.0 function.
(0, 0) = GPIO function is selected.
(0, 1) = ADC_CH1 function is selected.
(1, 0) = Reserved.
(1, 1) = ACMP0_P1 function is selected.
[10] ALT2 P1.2 Alternate Function Select Bit
Bits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH2 function is selected.
(0, 1, 0) = UART0_RXD function is selected.
(0, 1, 1) = ACMP0_P2 function is selected.
(1, 0, 0) = PWM0_CH0 function is selected.
[11] ALT3 P1.3 Alternate Function Select Bit
Bits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH3 function is selected.
(0, 1, 0) = UART0_TXD function is selected.
(0, 1, 1) = ACMP0_P3 function is selected.
(1, 0, 0) = PWM0_CH1 function is selected.
[12] ALT4 P1.4 Alternate Function Select Bit
Bits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH4 function is selected.
(0, 1, 0) = UART1_RXD function is selected.
(0, 1, 1) = ACMP0_N function is selected.
(1, 0, 0) = PWM0_CH4 function is selected.
[13] ALT5 P1.5 Alternate Function Select Bit
Bits ALT[5] (SYS_P1_MFP[13]), and MFP[5] (SYS_P1_MFP[5]) determine the P1.5 function.
(0, 0) = GPIO function is selected.
(0, 1) = ADC_CH5 function is selected.
(1, 0) = UART1_TXD function is selected.
(1, 1) = ACMP0_P0 function is selected.
[23:16] TYPE P1[7:0] Input Schmitt Trigger Function Enable Bit
0 = P1[7:0] I/O input Schmitt Trigger function Disabled.
1 = P1[7:0] I/O input Schmitt Trigger function Enabled.
[26] P12EXT P1.2 Alternate Function Selection Extension
Bits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH2 function is selected.
(0, 1, 0) = UART0_RXD function is selected.
(0, 1, 1) = ACMP0_P2 function is selected.
(1, 0, 0) = PWM0_CH0 function is selected.
[27] P13EXT P1.3 Alternate Function Selection Extension
Bits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH3 function is selected.
(0, 1, 0) = UART0_TXD function is selected.
(0, 1, 1) = ACMP0_P3 function is selected.
(1, 0, 0) = PWM0_CH1 function is selected.
[28] P14EXT P1.4 Alternate Function Selection Extension
Bits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = ADC_CH4 function is selected.
(0, 1, 0) = UART1_RXD function is selected.
(0, 1, 1) = ACMP0_N function is selected.
(1, 0, 0) = PWM0_CH4 function is selected.

Definition at line 9760 of file Mini58Series.h.

◆ P2_MFP

__IO uint32_t SYS_T::P2_MFP

P2_MFP

Offset: 0x38 P2 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P2 Multiple Function Select Bit
The pin function of P2 depends on MFP and ALT.
Refer to ALT Description for details.
[10] ALT2 P2.2 Alternate Function Select Bit
Bits ALT[2] (SYS_P2_MFP[10]), and MFP[2] (SYS_P2_MFP[2]) determine the P2.2 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = PWM0_CH0 function is selected.
(1, 1) = I2C1_SCL function is selected.
[11] ALT3 P2.3 Alternate Function Select Bit
Bits ALT[3] (SYS_P2_MFP[11]), and MFP[3] (SYS_P2_MFP[3]) determine the P2.3 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = PWM0_CH1 function is selected.
(1, 1) = I2C1_SDA1 function is selected.
[12] ALT4 P2.4 Alternate Function Select Bit
Bits ALT[4] (SYS_P2_MFP[12]), and MFP[4] (SYS_P2_MFP[4]) determine the P2.4 function.
(0, 0) = GPIO function is selected.
(0, 1) = UART1_RXD function is selected.
(1, 0) = PWM0_CH2 function is selected.
(1, 1) = Reserved.
[13] ALT5 P2.5 Alternate Function Select Bit
Bits ALT[5] (SYS_P2_MFP[13]), and MFP[5] (SYS_P2_MFP[5]) determine the P2.5 function.
(0, 0) = GPIO function is selected.
(0, 1) = UART1_TXD function is selected.
(1, 0) = PWM0_CH3 function is selected.
(1, 1) = Reserved.
[14] ALT6 P2.6 Alternate Function Select Bit
Bits ALT[6] (SYS_P2_MFP[14]), and MFP[6] (SYS_P2_MFP[6]) determine the P2.6 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = PWM0_CH4 function is selected.
(1, 1) = ACMP1_O0 function is selected.
[23:16] TYPE P2[7:0] Input Schmitt Trigger Function Enable Bits
0 = P2[7:0] I/O input Schmitt Trigger function Disabled.
1 = P2[7:0] I/O input Schmitt Trigger function Enabled.

Definition at line 9806 of file Mini58Series.h.

◆ P3_MFP

__IO uint32_t SYS_T::P3_MFP

P3_MFP

Offset: 0x3C P3 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P3 Multiple Function Select Bits
The pin function of P3 depends on MFP and ALT.
Refer to ALT Description for details.
[8] ALT0 P3.0 Alternate Function Select Bit
Bits ALT[0] (SYS_P3_MFP[8]), and MFP[0] (SYS_P3_MFP[0]) determine the P3.0 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = ACMP1_N function is selected.
(1, 1) = ADC_CH6 function is selected.
[9] ALT1 P3.1 Alternate Function Select Bit
The pin function of P3.1 depends on P3_MFP[1] and P3_ALT[1].
Bits ALT[1] (SYS_P3_MFP[9]), and MFP[1] (SYS_P3_MFP[1]) determine the P3.1 function.
(0, 0) = GPIO function is selected.
(0, 1) = Reserved.
(1, 0) = ACMP1_P0 function is selected.
(1, 1) = ADC_CH7 function is selected.
[10] ALT2 P3.2 Alternate Function Select Bit
Bits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = INT1 function is selected.
(0, 1, 0) = TM0_EXT function is selected.
(0, 1, 1) = STADC function is selected.
(1, 0, 0) = ACMP1_P1 function is selected.
[12] ALT4 P3.4 Alternate Function Select Bit
Bits ALT[4] (SYS_P3_MFP[12]), and MFP[4] (SYS_P3_MFP[4]) determine the P3.4 function.
(0, 0) = GPIO function is selected.
(0, 1) = TM0_CNT_OUT function is selected.
(1, 0) = I2C0_SDA function is selected.
(1, 1) = ACMP1_P2 function is selected.
[13] ALT5 P3.5 Alternate Function Select Bit
Bits ALT[5] (SYS_P3_MFP[13]), and MFP[5] (SYS_P3_MFP[5]) determine the P3.5 function.
(0, 0) = GPIO function is selected.
(0, 1) = TM1_CNT_OUTfunction is selected.
(1, 0) = I2C0_SCL function is selected.
(1, 1) = ACMP1_P3 function is selected.
[14] ALT6 P3.6 Alternate Function Select Bit
Bits ALT[6] (SYS_P3_MFP[14]), and MFP[6] (SYS_P3_MFP[6]) determine the P3.6 function.
(0, 0) = GPIO function is selected.
(0, 1) = TM1_EXT function is selected.
(1, 0) = CLKO function is selected.
(1, 1) = ACMP0_O function is selected.
[23:16] TYPE P3[7:0] Input Schmitt Trigger Function Enable Bits
0 = P3[7:0] I/O input Schmitt Trigger function Disabled.
1 = P3[7:0] I/O input Schmitt Trigger function Enabled.
[26] P32EXT P3.2 Alternate Function Selection Extension
Bits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.
(0, 0, 0) = GPIO function is selected.
(0, 0, 1) = INT1 function is selected.
(0, 1, 0) = TM0_EXT function is selected.
(0, 1, 1) = STADC function is selected.
(1, 0, 0) = ACMP1_P1 function is selected.

Definition at line 9867 of file Mini58Series.h.

◆ P4_MFP

__IO uint32_t SYS_T::P4_MFP

P4_MFP

Offset: 0x40 P4 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P4 Multiple Function Select Bits
The pin function of P4 depends on MFP and ALT.
Refer to ALT Description for details.
[14] ALT6 P4.6 Alternate Function Select Bit
Bits ALT[6] (SYS_P4_MFP[6]), and MFP[6] (SYS_P4_MFP[6]) determine the P4.6 function.
(0, 0) = GPIO function is selected.
(0, 1) = ICE_CLK function is selected.
(1, 0) = UART1_RXD function is selected.
(1, 1) = Reserved.
[15] ALT7 P4.7 Alternate Function Select Bit
Bits ALT[7] (SYS_P4_MFP[15]), and MFP[7] (SYS_P4_MFP[7]) determine the P4.7 function.
(0, 0) = GPIO function is selected.
(0, 1) = ICE_DAT function is selected.
(1, 0) = UART1_TXD function is selected.
(1, 1) = Reserved.
[23:16] TYPE P4[7:0] Input Schmitt Trigger Function Enable Bits
0 = P4[7:0] I/O input Schmitt Trigger function Disabled.
1 = P4[7:0] I/O input Schmitt Trigger function Enabled.

Definition at line 9895 of file Mini58Series.h.

◆ P5_MFP

__IO uint32_t SYS_T::P5_MFP

P5_MFP

Offset: 0x44 P5 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] MFP P5 Multiple Function Select Bits
The pin function of P5 depends on MFP and ALT.
Refer to ALT Description for details.
[8] ALT0 P5.0 Alternate Function Select Bit
The pin function of P5.0 depends on MFP[0] and ALT[0].
Bits ALT[0] (SYS_P5_MFP[8]), and MFP[0] (SYS_P5_MFP[0]) determine the P5.0 function.
(0, 0) = GPIO function is selected.
(0, 1) = XT1_IN function is selected.
(1, 0) = I2C1_SDA1 function is selected.
(1, 1) = UART0_TXD function is selected.
Note: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
[9] ALT1 P5.1 Alternate Function Select Bit
Bits ALT[1] (SYS_P5_MFP[9]), and MFP[1] (SYS_P5_MFP[1]) determine the P5.1 function.
(0, 0) = GPIO function is selected.
(0, 1) = XT1_OUT function is selected.
(1, 0) = I2C1_SCL1 function is selected.
(1, 1) = UART0_RXD function is selected.
Note: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
[10] ALT2 P5.2 Alternate Function Select Bit
Bits ALT[2] (SYS_P5_MFP[10]), and MFP[2] (SYS_P5_MFP[2]) determine the P5.2 function.
(0, 0) = GPIO function is selected.
(0, 1) = INT1 function is selected.
Others = Reserved.
[11] ALT3 P5.3 Alternate Function Select Bit
Bits ALT[3] (SYS_P5_MFP[11]), and MFP[3] (SYS_P5_MFP[3]) determine the P5.3 function.
(0, 0) = GPIO function is selected.
(0, 1) = ADC_CH0 function is selected.
Others = Reserved.
[12] ALT4 P5.4 Alternate Function Select Bit
Bits ALT[4] (SYS_P5_MFP[12]), and MFP[4] (SYS_P5_MFP[4]) determine the P5.4 function.
(0, 0) = GPIO function is selected.
Others = Reserved.
[13] ALT5 P5.5 Alternate Function Select Bit
Bits ALT[5] (SYS_P5_MFP[13]), and MFP[5] (SYS_P5_MFP[5]) determine the P5.5 function.
(0, 0) = GPIO function is selected.
Others = Reserved.
[23:16] TYPE P5[7:0] Input Schmitt Trigger Function Enable Bits
0 = P5[7:0] I/O input Schmitt Trigger function Disabled.
1 = P5[7:0] I/O input Schmitt Trigger function Enabled.

Definition at line 9944 of file Mini58Series.h.

◆ PCACTL

__IO uint32_t PWM_T::PCACTL

PCACTL

Offset: 0x88 PWM Precise Center-Aligned Type Control Register

Bits Field Descriptions
[0] PCAEN PWM Precise Center-aligned Type Enable Bit
0 = Precise center-aligned type Disabled.
1 = Precise center-aligned type Enabled.

Definition at line 7835 of file Mini58Series.h.

◆ PDID

__I uint32_t SYS_T::PDID

PDID

Offset: 0x00 Part Device Identification Number Register

Bits Field Descriptions
[31:0] PDID Product Device Identification Number (Read Only)
This register reflects the device part number code.
Software can read this register to identify which device is use.
For example, the MINI58LDE PDID code is "0x00A05800".

Definition at line 9480 of file Mini58Series.h.

◆ PERIOD0

__IO uint32_t PWM_T::PERIOD0

PERIOD0

Offset: 0x0C PWM Counter Period Register 0

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 5673 of file Mini58Series.h.

◆ PERIOD1

__IO uint32_t PWM_T::PERIOD1

PERIOD1

Offset: 0x10 PWM Counter Period Register 1

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 5779 of file Mini58Series.h.

◆ PERIOD2

__IO uint32_t PWM_T::PERIOD2

PERIOD2

Offset: 0x14 PWM Counter Period Register 2

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 5885 of file Mini58Series.h.

◆ PERIOD3

__IO uint32_t PWM_T::PERIOD3

PERIOD3

Offset: 0x18 PWM Counter Period Register 3

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 5991 of file Mini58Series.h.

◆ PERIOD4

__IO uint32_t PWM_T::PERIOD4

PERIOD4

Offset: 0x1C PWM Counter Period Register 4

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 6097 of file Mini58Series.h.

◆ PERIOD5

__IO uint32_t PWM_T::PERIOD5

PERIOD5

Offset: 0x20 PWM Counter Period Register 5

Bits Field Descriptions
[15:0] PERIOD0 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD1 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD2 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD3 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD4 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.
[15:0] PERIOD5 PWM Counter Period Value
PERIODn determines the PWM counter period.
Edge-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMPn+1)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always high.
CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit.
CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit.
Center-aligned type:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (PERIODn - CMPn)/( PERIODn+1).
CMPn >= PERIODn: PWM output is always low.
CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit.
CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to PERIODn will take effect in the next PWM cycle.

Definition at line 6203 of file Mini58Series.h.

◆ PHCHG

__IO uint32_t PWM_T::PHCHG

PHCHG

Offset: 0x78 PWM Phase Changed Register

Bits Field Descriptions
[5:0] MSKDAT0 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT1 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT2 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT3 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT4 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT5 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[6] MSKDAT6 PWM0_CH6 (GPIO P0.1) Mask Data
When MASKEND6 Is 1, channel 6's output level is MSKDAT6.
0 = PWM0_CH6 output low level.
1 = PWM0_CH6 output high level.
[7] MSKDAT7 PWM0_CH7 (GPIO P0.0) Mask Data
When MASKEND7 Is 1, channel 7's output level is MSKDAT7.
0 = PWM0_CH7 output low level.
1 = PWM0_CH7 output high level.
[13:8] MSKEN0 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN1 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN2 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN3 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN4 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN5 PWMn Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[14] AUTOCLR0 Hardware Auto Clear ACMP0TEN
0 = Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM.
1 = Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM.
[15] AUTOCLR1 Hardware Auto Clear ACMP1TEN
0 = Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM.
1 = Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM.
[16] AOFFEN01 ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH0 one period cycle output low Disabled.
1 = PWM0_CH0 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[17] AOFFEN11 ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH1 one period cycle output low Disabled.
1 = PWM0_CH1 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[18] AOFFEN21 ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH2 one period cycle output low Disabled.
1 = PWM0_CH2 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH 3.
[19] AOFFEN31 ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH3 one period cycle output low Disabled.
1 = PWM0_CH3 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[21:20] A1POSSEL ACMP1 Positive Input Source Select Bits
00 = Select P3.1 as the input of ACMP1.
01 = Select P3.2 as the input of ACMP1.
10 = Select P3.3 as the input of ACMP1.
11 = Select P3.4 as the input of ACMP1.
[22] TMR1TEN TIMER1 Trigger PWM Function Enable Bit
When this bit is set, TIMER1 time-out event will update PWM_PHCHG with PHCHG_NXT register.
0 = TIMER1 trigger PWM function Disabled.
1 = TIMER1 trigger PWM function Enabled.
[23] ACMP1TEN ACMP1 Trigger Function Enable Bit
0 = ACMP1 trigger PWM function Disabled.
1 = ACMP1 trigger PWM function Enabled.
Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
[24] AOFFEN00 ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH0 one period cycle output low Disabled.
1 = PWM0_CH0 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[25] AOFFEN10 ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH1 one period cycle output low Disabled.
1 = PWM0_CH1 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[26] AOFFEN20 ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH2 one period cycle output low Disabled.
1 = PWM0_CH2 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[27] AOFFEN30 ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH3 one period cycle output low Disabled.
1 = PWM0_CH3 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~ PWM0_CH3.
[29:28] A0POSSEL ACMP0 Positive Input Source Select Bits
00 = Select P1.5 as the input of ACMP0.
01 = Select P1.0 as the input of ACMP0.
10 = Select P1.2 as the input of ACMP0.
11 = Select P1.3 as the input of ACMP0.
[30] TMR0TEN TIMER0 Trigger PWM Function Enable Bit
When this bit is set, TIMER0 time-out event will update PWM_PHCHG with PHCHG_NXT register.
0 = TIMER0 trigger PWM function Disabled.
1 = TIMER0 trigger PWM function Enabled.
[31] ACMP0TEN ACMP0 Trigger PWM Function Enable Bit
0 = ACMP0 trigger PWM function Disabled.
1 = ACMP0 trigger PWM function Enabled.
Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.

Definition at line 7651 of file Mini58Series.h.

◆ PHCHGMSK

__IO uint32_t PWM_T::PHCHGMSK

PHCHGMSK

Offset: 0x80 PWM Phase Change Mask Register

Bits Field Descriptions
[6] MASKEND6 PWM0_CH6 (GPIO P0.1) Output Mask Enable Bit
0 = Output the original GPIO P0.1.
1 = Output MSKDAT6 specified in bit 6 of PWM_PHCHG register.
[7] MASKEND7 PWM0_CH7 (GPIO P0.0) Output Mask Enable Bit
0 = Output the original GPIO P0.0.
1 = Output MSKDAT7 specified in bit 7 of PWM_PHCHG register.
[8] POSCTL0 Positive Input Control For ACMP0
0 = The input of ACMP is controlled by CMP0CR.
1 = The input of ACMP is controlled by CMP0SEL of PWM_PHCHG register.
Note: Register CMP0CR is described in Comparator Controller chapter.
[9] POSCTL1 Positive Input Control For ACMP1
0 = The input of ACMP is controlled by CMP1CR.
1 = The input of ACMP is controlled by CMP1SEL of PWM_PHCHG register.
Note: Register CMP1CR is described in Comparator Controller chapter.

Definition at line 7807 of file Mini58Series.h.

◆ PHCHGNXT

__IO uint32_t PWM_T::PHCHGNXT

PHCHGNXT

Offset: 0x7C PWM Next Phase Change Register

Bits Field Descriptions
[5:0] MSKDAT0 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT1 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT2 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT3 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT4 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[5:0] MSKDAT5 PWM0_CHn Mask Data
When MSKENn is 0, channel n's output level is MSKDATn.
0 = PWM0_CHn output low level.
1 = PWM0_CHn output high level.
[6] MSKDAT6 PWM0_CH6 (GPIO P0.1) Mask Data
When MASKEND6 Is 1, channel 6's output level is MSKDAT6.
0 = PWM0_CH6 output low level.
1 = PWM0_CH6 output high level.
[7] MSKDAT7 PWM0_CH7 (GPIO P0.0) Mask Data
When MASKEND7 Is 1, channel 7's output level is MSKDAT7.
0 = PWM0_CH7 output low level.
1 = PWM0_CH7 output high level.
[13:8] MSKEN0 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN1 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN2 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN3 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN4 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[13:8] MSKEN5 PWM Output Mask Enable Bits
0 = Output MSKDATn specified in bit n of PWM_PHCHG register.
1 = Output the original channel n waveform.
[14] AUTOCLR0 Hardware Auto Clear ACMP0TEN
0 = Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM.
1 = Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM.
[15] AUTOCLR1 Hardware Auto Clear ACMP1TEN
0 = Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM.
1 = Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM.
[16] AOFFEN01 ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH0 one period cycle output low Disabled.
1 = PWM0_CH0 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[17] AOFFEN11 ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH1 one period cycle output low Disabled.
1 = PWM0_CH1 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[18] AOFFEN21 ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH2 one period cycle output low Disabled.
1 = PWM0_CH2 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[19] AOFFEN31 ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.
0 = PWM0_CH3 one period cycle output low Disabled.
1 = PWM0_CH3 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[21:20] A1POSSEL ACMP1 Positive Input Source Select Bits
00 = Select P3.1 as the input of ACMP1.
01 = Select P3.2 as the input of ACMP1.
10 = Select P3.3 as the input of ACMP1.
11 = Select P3.4 as the input of ACMP1.
[22] TMR1TEN TMR1 Trigger PWM Function Enable Bit
When this bit is set, TMR1 time-out event will update PWM_PHCHG with PHCHG_NXT register.
0 = TMR1 trigger PWM function Disabled.
1 = TMR1 trigger PWM function Enabled.
[23] ACMP1TEN ACMP1 Trigger Function Enable Bit
0 = ACMP1 trigger PWM function Disabled.
1 = ACMP1 trigger PWM function Enabled.
Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
[24] AOFFEN00 ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH0 one period cycle output low Disabled.
1 = PWM0_CH0 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[25] AOFFEN10 ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH1 one period cycle output low Disabled.
1 = PWM0_CH1 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[26] AOFFEN20 ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH2 one period cycle output low Disabled.
1 = PWM0_CH2 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[27] AOFFEN30 ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit
Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.
0 = PWM0_CH3 one period cycle output low Disabled.
1 = PWM0_CH3 one period cycle output low Enabled.
Note: This function is only available for PWM0_CH0~PWM0_CH3.
[29:28] A0POSSEL ACMP0 Positive Input Source Select Bits
00 = Select P1.5 as the input of ACMP0.
01 = Select P1.0 as the input of ACMP0.
10 = Select P1.2 as the input of ACMP0.
11 = Select P1.3 as the input of ACMP0.
[30] TMR0TEN TMR0 Trigger PWM Function Enable Bit
When this bit is set, TMR0 time-out event will update PWM_PHCHG with PHCHG_NXT register.
0 = TMR0 trigger PWM function Disabled.
1 = TMR0 trigger PWM function Enabled.
[31] ACMP0TEN ACMP0 Trigger Function Enable Bit
0 = ACMP0 trigger PWM function Disabled.
1 = ACMP0 trigger PWM function Enabled.
Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.

Definition at line 7783 of file Mini58Series.h.

◆ PIN

__I uint32_t GPIO_T::PIN

PIN

Offset: 0x10 P0 Pin Value

Bits Field Descriptions
[0] PIN0 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[1] PIN1 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[2] PIN2 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[3] PIN3 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[4] PIN4 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[5] PIN5 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[6] PIN6 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.
[7] PIN7 Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
Max. n=7 for port 0, n=2, n=3 are reserved.
Max. n=7 for port 1, n=1, n=6, n=7 are reserved.
Max. n=7 for port 2, n=0, n=1, n=7 are reserved.
Max. n=7 for port 3, n=3, n=7 are reserved.
Max. n=7 for port 4, n=0,.5 are reserved.
Max. n=7 for port 5, n=6, n=7 are reserved.

Definition at line 2167 of file Mini58Series.h.

◆ PLLCTL

__IO uint32_t CLK_T::PLLCTL

PLLCTL

Offset: 0x20 PLL Control Register

Bits Field Descriptions
[8:0] FBDIV PLL Feedback Divider Control
Refer to the formulas below the table.
[13:9] INDIV PLL Input Divider Control
Refer to the formulas below the table.
[15:14] OUTDIV PLL Output Divider Control
Refer to the formulas below the table.
[16] PD Power-down Mode
If the PDEN bit is set to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too.
0 = PLL is in Normal mode.
1 = PLL is in Power-down mode (default).
[17] BP PLL Bypass Control
0 = PLL is in Normal mode (default).
1 = PLL clock output is same as PLL source clock input.
[18] OE PLL OE (FOUT Enable) Pin Control
0 = PLL FOUT Enabled.
1 = PLL FOUT is fixed low.
[19] PLLSRC PLL Source Clock Selection
0 = PLL source clock from HXT.
1 = PLL source clock from HIRC.

Definition at line 1144 of file Mini58Series.h.

◆ POEN

__IO uint32_t PWM_T::POEN

POEN

Offset: 0x5C PWM Output Enable Register

Bits Field Descriptions
[5:0] POEN0 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5:0] POEN1 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5:0] POEN2 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5:0] POEN3 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5:0] POEN4 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5:0] POEN5 PWM Output Enable Bits
0 = PWM channel n output to pin Disabled.
1 = PWM channel n output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.

Definition at line 7200 of file Mini58Series.h.

◆ PWRCTL

__IO uint32_t CLK_T::PWRCTL

PWRCTL

Offset: 0x00 System Power-down Control Register

Bits Field Descriptions
[1:0] XTLEN External HXT Or LXT Crystal Oscillator Enable Bit (Write Protect)
The default clock source is from HIRC.
These two bits are default set to "00" and the XT1_IN and XT1_OUT pins are GPI.
00 = XT1_IN and XT1_OUT are GPIO, disable both LXT & HXT (default).
01 = HXT Enabled.
10 = LXT Enabled.
11 = XT1_IN is external clock input pin, XT1_OUT is GPIO.
Note: To enable external XTAL function, ALT[1:0] and MFP[1:0] bits must also be set in SYS_P5_MFP.
[2] HIRCEN HIRC Enable Bit (Write Protect)
0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled.
1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled.
Note: The default of HIRCEN bit is 1.
[3] LIRCEN LIRC Enable Bit (Write Protect)
0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
[4] PDWKDLY Wake-up Delay Counter Enable Bit (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
[5] PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
0 = Power-down mode wake-up interrupt Disabled.
1 = Power-down mode wake-up interrupt Enabled.
Note: The interrupt will occur when both PDWKIF and PDWKIEN are high.
[6] PDWKIF Power-down Mode Wake-up Interrupt Status
Set by "Power-down wake-up event", which indicates that resume from Power-down mode
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred.
Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0.
[7] PDEN System Power-down Enable Bit (Write Protect)
When chip wakes up from Power-down mode, this bit is cleared by hardware.
User needs to set this bit again for next Power-down.
In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.
0 = Chip operating normally or chip in Idle mode because of WFI command.
1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI.
[9] PDLXT Enable LXT In Power-down Mode
This bit controls the crystal oscillator active or not in Power-down mode.
0 = No effect to Power-down mode.
1 = If XTLEN[1:0] = 10, LXT is still active in Power-down mode.

Definition at line 876 of file Mini58Series.h.

◆ REGLCTL

__O uint32_t SYS_T::REGLCTL

REGLCTL

Offset: 0x100 Register Write-Protection Control Register

Bits Field Descriptions
[7:0] REGLCTL Register Write-protection Code (Write Only)
Some registers have write-protection function.
Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field.
After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal writ.
Register Write-protection Disable Index (Read Only)
0 = Write-protection Enabled for writing protected registers.
Any write to the protected register is ignore.
1 = Write-protection Disabled for writing protected registers.
Protected registers are listed below:
SYS_IPRST0 (0x5000_0008) : Peripheral Reset Control Resister 0
SYS_BODCTL (0x5000_0018) : Brown-out Detector Control Register
CLK_PWRCTL (0x5000_0200) : Bit[6] is not protected for power wake-up interrupt clear.
CLK_APBCLK bit[0] (0x5000_0208) : Bit[0] is watchdog clock enable.
CLK_CLKSEL0 (0x5000_0210) : HCLK and CPU STCLK clock source select.
CLK_CLKSEL1 bit[1:0] (0x5000_0214) : Watchdog clock source select.
NMI_SEL bit[8] (0x5000_0380) : NMI interrupt enable.
ISPCON (0x5000_C000) : Flash ISP Control.
ISPTRG (0x5000_C010) : ISP Trigger Control.
WTCR (0x4000_4000) : Watchdog Timer Control.
Note: The bits which are write-protected will be noted as" (Write Protect)" beside the description.

Definition at line 10055 of file Mini58Series.h.

◆ RLDCNT

__O uint32_t WWDT_T::RLDCNT

RLDCNT

Offset: 0x00 WWDT Reload Counter Register

Bits Field Descriptions
[31:0] RLDCNT WWDT Reload Counter Register
Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.

Definition at line 11541 of file Mini58Series.h.

◆ RSTSTS

__IO uint32_t SYS_T::RSTSTS

RSTSTS

Offset: 0x04 System Reset Status Register

Bits Field Descriptions
[0] PORF POR Reset Flag
The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
0 = No reset from POR or CHIPRST.
1 = Power-on-Reset (POR) or CHIPRST had issued the reset signal to reset the system.
Note: Software can write 1 to clear this bit to zero.
[1] PINRF NRESET Pin Reset Flag
The nRESET pin reset flag is set by the "Reset Signal" from the nRESET pin to indicate the previous reset source.
0 = No reset from nRESET pin.
1 = Pin nRESET had issued the reset signal to reset the system.
Note: Software can write 1 to clear this bit to zero.
[2] WDTRF WDT Reset Flag
The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
0 = No reset from watchdog timer or window watchdog timer.
1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
Note: Software can write 1 to clear this bit to zero.
[4] BODRF BOD Reset Flag
The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source.
0 = No reset from BOD.
1 = The BOD had issued the reset signal to reset the system.
Note: Software can write 1 to clear this bit to zero.
[5] SYSRF System Reset Flag
The system reset flag is set by the "Reset Signal" from the Cortex-M0 Core to indicate the previous reset source.
0 = No reset from Cortex-M0.
1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ (SCS_AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C in system control registers of Cortex-M0 core.
Note: Software can write 1 to clear this bit to zero.
[7] CPURF CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).
0 = No reset from CPU.
1 = The Cortex-M0 Core and FMC are reset by software setting CPURST to 1.
Note: Software can write 1 to clear this bit to zero.
[8] CPULKRF The Cortex-M0 LOCKUP Flag
0 = No reset from Cortex-M0 LOCKUP happened.
1 = The Cortex-M0 LOCKUP happened and chip is reset.
Note: Software can write 1 to clear this bit to zero.

Definition at line 9524 of file Mini58Series.h.

◆ RX

__I uint32_t SPI_T::RX

RX

Offset: 0x10 SPI Data Receive Register

Bits Field Descriptions
[31:0] RX Data Receive Register (Read Only)
The Data Receive Register holds the value of received data of the last executed transfer.
Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.
For example, if DWIDTH is set to 0x08, the bit field RX[7:0] holds the received data.
The values of the other bits are unknown.
The Data Receive Register is read-only register.

Definition at line 9134 of file Mini58Series.h.

◆ SEQCTL

__IO uint32_t ADC_T::SEQCTL

SEQCTL

Offset: 0x4C A/D PWM Sequential Mode Control Register

Bits Field Descriptions
[0] SEQEN ADC Sequential Mode Enable Bit
When ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by MODESEL (ADC_SEQCTL[3:2]).
0 = ADC sequential mode Disabled.
1 = ADC sequential mode Enabled.
[1] SEQTYPE ADC Sequential Mode Type
0 = ADC delay time is only inserted before the first conversion.
The second conversion starts immediately after the first conversion is completed.
(for 2/3-shunt type).
1 = ADC delay time is inserted before each conversion. (for 1-shunt type)
[3:2] MODESEL ADC Sequential Mode Selection
00 = Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1.
01 = Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1.
10 = Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1.
11 = Reserved.
[11:8] TRG1CTL PWM Trigger Source Selection For TRG1CTL[3:2]
00 = PWM Trigger source is PWM0.
01 = PWM Trigger source is PWM2.
10 = PWM Trigger source is PWM4.
11 = PWM Trigger source is reserved.
PWM Trigger Type Selection for TRG1CTL[1:0]
00 = Rising of the selected PWM.
01 = Center of the selected PWM.
10 = Falling of the selected PWM.
11 = Period of the selected PWM.
Note: PWM trigger source is valid for 1-shunt and 2/3-shunt type.
[19:16] TRG2CTL PWM Trigger Source Selection For TRG2CTL[3:2]
00 = PWM Trigger source is PWM0.
01 = PWM Trigger source is PWM2.
10 = PWM Trigger source is PWM4.
11 = PWM Trigger source is reserved.
PWM Trigger Type Selection for TRG2CTL[1:0]
00 = Rising of the selected PWM.
01 = Center of the selected PWM.
10 = Falling of the selected PWM.
11 = Period of the selected PWM.
Note: PWM trigger source is valid for 1-shunt type.

Definition at line 613 of file Mini58Series.h.

◆ SEQDAT1

__I uint32_t ADC_T::SEQDAT1

SEQDAT1

Offset: 0x50 A/D PWM Sequential Mode First Result Register1

Bits Field Descriptions
[9:0] RESULT A/D PWM Sequential Mode Conversion Result
This field contains conversion result of ADC.
[16] OV Over Run Flag
If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1.
It is cleared by hardware after the ADC_DAT register is read.
0 = Data in RESULT[9:0] is recent conversion result.
1 = Data in RESULT[9:0] overwritten.
[17] VALID Valid Flag
This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
0 = Data in RESULT[9:0] bits not valid.
1 = Data in RESULT[9:0] bits valid.

Definition at line 634 of file Mini58Series.h.

◆ SEQDAT2

__I uint32_t ADC_T::SEQDAT2

SEQDAT2

Offset: 0x54 A/D PWM Sequential Mode Second Result Register1

Bits Field Descriptions
[9:0] RESULT A/D PWM Sequential Mode Conversion Result
This field contains conversion result of ADC.
[16] OV Over Run Flag
If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1.
It is cleared by hardware after the ADC_DAT register is read.
0 = Data in RESULT[9:0] is recent conversion result.
1 = Data in RESULT[9:0] overwritten.
[17] VALID Valid Flag
This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
0 = Data in RESULT[9:0] bits not valid.
1 = Data in RESULT[9:0] bits valid.

Definition at line 655 of file Mini58Series.h.

◆ SLVCTL

__IO uint32_t SPI_T::SLVCTL

SLVCTL

Offset: 0x3C SPI Slave Control and Status Register

Bits Field Descriptions
[8] SLV3WIRE Slave 3-wire Mode Enable Bit (Slave Only)
The SPI controller work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.
0 = The controller is 4-wire bi-direction interface in Slave mode.
1 = The controller is 3-wire bi-direction interface in Slave mode.
The controller will be ready to transmit/receive data after the SPIEN bit is set to .
Note: In Slave 3-wire mode, the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1.
[9] SLVABT Slave 3-wire Mode Abort Control Bit (Slave Only)
In normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH.
If the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event.
0 = No force the transfer done when the SLV3WIRE bit is set to 1.
1 = Force the transfer done when the SLV3WIRE bit is set to 1.
Note: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
[10] SLVSTIEN Slave 3-wire Mode Start Interrupt Enable (Slave Only)
It is used to enable interrupt when the transfer has started in Slave 3-wire mode.
If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLVABT bit to force the transfer don.
0 = Transaction start interrupt Disabled.
1 = Transaction start interrupt Enabled.
Note: It will be cleared to 0 as the current transfer is done or the SLVSTIF bit is cleared to 0.
[11] SLVSTIF Slave 3-wire Mode Start Interrupt Status (Slave Only)
This bit dedicates if a transaction has started in Slave 3-wire mode.
0 = Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1.
1 = The transfer has started in Slave 3-wire mode.
Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.
Note 2: It is a mutual mirror bit of SPI_STATUS[11].
[16] SSINAIEN Slave Select Inactive Interrupt Option (Slave Only)
0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1.
1 = As the slave select signal goes to inactive level, the IF bit will be set to 1.
Note: This setting is only available if the SPI controller is configured as level trigger in slave device.
[31] DIVMOD Clock Configuration Backward Compatible Option
0 = The clock configuration is backward compatible.
1 = The clock configuration is not backward compatible.
Note:
Refer to the description of SPI_CLKDIV register for details.

Definition at line 9199 of file Mini58Series.h.

◆ SSCTL

__IO uint32_t SPI_T::SSCTL

SSCTL

Offset: 0x08 SPI Slave Select Register

Bits Field Descriptions
[0] SS Slave Select Control Bits (Master Only)
If AUTOSS bit is 0,
0 = Set the SPI_SS line to inactive state.
1 = Set the SPI_SS line to active state.
If AUTOSS bit is 1,
0 = Keep the SPI_SS line at inactive state.
1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time.
The active state of SPI_SS is specified in SSACTPOL bit.
[2] SSACTPOL Slave Select Active Level (Slave Only)
It defines the active status of slave select signal (SPI_SS).
If SSLTEN bit is 1:
0 = The slave select signal SPI_SS is active at low-level.
1 = The slave select signal SPI_SS is active at high-level.
If SSLTEN bit is 0:
0 = The slave select signal SPI_SS is active at falling-edge.
1 = The slave select signal SPI_SS is active at rising-edge.
[3] AUTOSS Automatic Slave Selection Function Enable Bit (Master Only)
0 = SPI_SS pin signal will be asserted/de-asserted by setting /clearing SS bit.
1 = SPI_SS pin signal will be generated automatically by hardware, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting SPIEN, and will be de-asserted after each transmit/receive is finished.
[4] SSLTEN Slave Select Level Trigger Enable Bit (Slave Only)
0 = The input slave select signal is edge-trigger.
1 = The input slave select signal is level-trigger.
[5] LTF Level Trigger Flag (Read Only, Slave Only)
When the SSLTEN bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
0 = The transaction number or the transferred bit length of one transaction does not meet the specified requirements.
1 = The transaction number and the transferred bit length meet the specified requirements which defined in DWIDTH.

Definition at line 9114 of file Mini58Series.h.

◆ STATUS [1/6]

__IO uint32_t ACMP_T::STATUS

STATUS

Offset: 0x08 Analog Comparator 0/1 Status Register

Bits Field Descriptions
[0] ACMPIF0 Analog Comparator 0 Flag
This bit is set by hardware whenever the comparator 0 output changes state.
This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) = 1.
0 = Analog comparator 0 output does not change.
1 = Analog comparator 0 output changed.
Note: This bit can be cleared to 0 by software writing 1.
[1] ACMPIF1 Analog Comparator 1 Flag
This bit is set by hardware whenever the comparator 1 output changes state.
This will generate an interrupt if ACMPIE (ACMP_CTL1[1]) = 1.
0 = Analog comparator 1 output does not change.
1 = Analog comparator 1 output changed.
Note: This bit can be cleared to 0 by software writing 1.
[2] ACMPO0 Analog Comparator 0 Output
Synchronized to the APB clock to allow reading by software.
Cleared when the comparator 0 is disabled ACMPEN (ACMP_CTL0[0]) = 0.
0 = Analog comparator 0 outputs 0.
1 = Analog comparator 0 outputs 1.
[3] ACMPO1 Analog Comparator 1 Output
Synchronized to the APB clock to allow reading by software.
Cleared when the comparator 1 is disabled ACMPEN (ACMP_CTL1[0]) = 0.
0 = Analog comparator 1 outputs 0.
1 = Analog comparator 1 outputs 1.

Definition at line 245 of file Mini58Series.h.

◆ STATUS [2/6]

__IO uint32_t ADC_T::STATUS

STATUS

Offset: 0x30 A/D Status Register

Bits Field Descriptions
[0] ADIF A/D Conversion End Flag
A status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.
Note: This bit can be cleared to 0 by software writing 1.
[1] ADCMPF0 A/D Compare Flag 0
When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1.
0 = Conversion result in ADC_DAT does not meet the ADC_CMP0 setting.
1 = Conversion result in ADC_DAT meets the ADC_CMP0 setting.
Note: This bit can be cleared to 0 by software writing 1.
[2] ADCMPF1 A/D Compare Flag 1
When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1.
0 = Conversion result in ADC_DAT does not meet the ADC_CMP1 setting.
1 = Conversion result in ADC_DAT meets the ADC_CMP1 setting.
Note: This bit can be cleared to 0 by software writing 1.
[3] BUSY BUSY/IDLE (Read Only)
This bit is mirror of as SWTRG bit in ADC_CTL
0 = A/D converter is in idle state.
1 = A/D converter is busy at conversion.
[6:4] CHANNEL Current Conversion Channel (Read Only)
This filed reflects the current conversion channel when BUSY=1.
When BUSY=0, it shows the number of the next converted channel.
[8] VALID Data Valid Flag (Read Only)
It is a mirror of VALID bit in ADC_DAT register.
[16] OV Overrun Flag (Read Only)
It is a mirror to OV bit in ADC_DAT register.

Definition at line 520 of file Mini58Series.h.

◆ STATUS [3/6]

__IO uint32_t CLK_T::STATUS

STATUS

Offset: 0x0C Clock Status Monitor Register

Bits Field Descriptions
[0] XTLSTB HXT Or LXT Clock Source Stable Flag
0 = HXT or LXT clock is not stable or disabled.
1 = HXT or LXT clock is stable and enabled.
[2] PLLSTB Internal PLL Clock Source Stable Flag (Read Only)
0 = Internal PLL clock is not stable or disabled.
1 = Internal PLL clock is stable and enabled.
[3] LIRCSTB LIRC Clock Source Stable Flag (Read Only)
0 = LIRC clock is not stable or disabled.
1 = LIRC clock is stable and enabled.
[4] HIRCSTB HIRC Clock Source Stable Flag (Read Only)
0 = HIRC clock is not stable or disabled.
1 = HIRC clock is stable and enabled.
[7] CLKSFAIL Clock Switch Fail Flag (Read Only)
This bit is updated when software switches system clock source.
If switch target clock is stable, this bit will be set to 0.
If switch target clock is not stable, this bit will be set to .
0 = Clock switching success.
1 = Clock switching failure.
Note: This bit is read only.
After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.

Definition at line 973 of file Mini58Series.h.

◆ STATUS [4/6]

__I uint32_t I2C_T::STATUS

STATUS

Offset: 0x0C I2C Status Register

Bits Field Descriptions
[7:0] STATUS I2C Status Register
The three least significant bits are always 0.
The five most significant bits contain the status code.
There are 26 possible status codes.
When I2C_STATUS contains F8H, no serial interrupt is requested.
All the other I2C_STATUS values correspond to defined I2C states.
When each of these states is entered, a status interrupt is requested (SI = 1).
A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
In addition, the states 00H stands for a Bus Error.
A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
Examples of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.

Definition at line 4636 of file Mini58Series.h.

◆ STATUS [5/6]

__IO uint32_t SPI_T::STATUS

STATUS

Offset: 0x44 SPI Status Register

Bits Field Descriptions
[0] RXTHIF Receive FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI controller will generate a SPI interrupt request.
[2] RXOVIF Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
0 = No overrun in receive FIFO.
1 = Overrun in receive FIFO.
Note: This bit will be cleared by writing 1 to itself.
[4] TXTHIF Transmit FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
[11] SLVSTIF Slave Start Interrupt Status (Slave Only)
It is used to dedicate that the transfer has started in slave 3-wire mode.
0 = Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1.
The transfer is not started.
1 = The transfer has started in Slave 3-wire mode.
Note 1: It will be cleared as transfer done or by writing one to this bit.
Note 2: It's a mutual mirror bit of SPI_SLVCTL[11].
[15:12] RXCNT Receive FIFO Data Count (Read Only)
Indicates the valid data count of receive FIFO buffer.
[16] UNITIF SPI Unit-transfer Interrupt Flag
0 = The transfer does not finish yet.
1 = The SPI controller has finished one unit transfer.
Note 1: This bit will be cleared by writing 1 to itself.
Note 2: It's a mutual mirror bit of SPI_CTL[16].
[20] SLVTOIF Time-out Interrupt Flag
0 = No receive FIFO time-out event.
1 = The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode.
When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
Note: This bit will be cleared by writing 1 to itself.
[24] RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)
0 = The receive FIFO buffer is not empty.
1 = The receive FIFO buffer is empty.
Note: It's a mutual mirror bit of SPI_CTL[24].
[25] RXFULL Receive FIFO Buffer Full Indicator (Read Only)
0 = The receive FIFO buffer is not full.
1 = The receive FIFO buffer is full.
Note: It's a mutual mirror bit of SPI_CTL[25].
[26] TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)
0 = The transmit FIFO buffer is not empty.
1 = The transmit FIFO buffer is empty.
Note: It's a mutual mirror bit of SPI_CTL[26].
[27] TXFULL Transmit FIFO Buffer Full Indicator (Read Only)
0 = The transmit FIFO buffer is not full.
1 = The transmit FIFO buffer is full.
Note: It's a mutual mirror bit of SPI_CTL[27].
[31:28] TXCNT Transmit FIFO Data Count (Read Only)
Indicates the valid data count of transmit FIFO buffer.

Definition at line 9295 of file Mini58Series.h.

◆ STATUS [6/6]

__IO uint32_t WWDT_T::STATUS

STATUS

Offset: 0x08 WWDT Status Register

Bits Field Descriptions
[0] WWDTIF WWDT Compare Match Interrupt Flag
This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
0 = No effect.
1 = WWDT counter value matches CMPDAT.
Note: This bit is cleared by writing 1 to it.
[1] WWDTRF WWDT Timer-out Reset Flag
This bit indicates the system has been reset by WWDT time-out reset or not.
0 = WWDT time-out reset did not occur.
1 = WWDT time-out reset occurred.
Note: This bit is cleared by writing 1 to it.

Definition at line 11605 of file Mini58Series.h.

◆ STATUS1

__IO uint32_t I2C_T::STATUS1

STATUS1

Offset: 0x40 I2C Status Register 1

Bits Field Descriptions
[0] WKIF I2C Wake-up Interrupt Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1.
This bit can be cleared by software writing "1".
Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
[1] FULL I2C Two-level Buffer Full
This bit indicates if the TX buffer is full or not when the TWOLVFIFO = 1.
[2] EMPTY I2C Two-level Buffer Empty
This bit indicates if the RX buffer is empty or not when the TWOLVFIFO = 1.
[3] OVIF I2C Overrun Status
This bit indicates the received buffer is overrun when the TWOLVFIFO = 1.
[4] URIF I2C Under Run Status
This bit indicates the transmitted buffer is under run when the TWOLVFIFO = 1.

Definition at line 4834 of file Mini58Series.h.

◆ TOCTL

__IO uint32_t I2C_T::TOCTL

TOCTL

Offset: 0x14 I2C Time-out Control Register

Bits Field Descriptions
[0] TOIF Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: This bit can be cleared by software writing '1'.
[1] TOCURIEN Time-out Counter Input Clock Divided By 4
0 = Time-out counter input clock divided by 4 Disabled.
1 = Time-out counter input clock divided by 4 Enabled.
Note: When enabled, the time-out period is extended 4 times.
[2] TOCEN Time-out Counter Enable Bit
0 = Time-out counter Disabled.
1 = Time-out counter Enabled.
Note: When the 14-bit time-out counter is enabled, it will start counting when SI is cleared.
Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared.

Definition at line 4671 of file Mini58Series.h.

◆ TOUT

__IO uint32_t UART_T::TOUT

TOUT

Offset: 0x20 UART Time-out Register

Bits Field Descriptions
[7:0] TOIC Time-out Interrupt Comparator
The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (RXTOINT) is generated if RXTOIEN (UART_INTEN[4]) is enabled.
A new incoming data word or RX FIFO empty clears RXTOINT.
In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfe.
[15:8] DLY TX Delay Time Value
This field is used to program the transfer delay time between the last stop bit and next start bit.
The Unit is bit tim.

Definition at line 11068 of file Mini58Series.h.

◆ TRGDLY

__IO uint32_t ADC_T::TRGDLY

TRGDLY

Offset: 0x44 A/D Trigger Delay Control Register

Bits Field Descriptions
[7:0] DELAY PWM Trigger Delay Timer
Set this field will delay ADC start conversion time after PWM trigger.
PWM trigger delay time is (4 * DELAY) * system clock.

Definition at line 537 of file Mini58Series.h.

◆ TX

__O uint32_t SPI_T::TX

TX

Offset: 0x20 SPI Data Transmit Register

Bits Field Descriptions
[31:0] TX Data Transmit Register
The Data Transmit Register holds the data to be transmitted in the next transfer.
Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.
For example, if DWIDTH is set to 0x08, the bit filed TX[7:0] will be transmitted in next transfer.

Definition at line 9152 of file Mini58Series.h.

◆ VREF

__IO uint32_t ACMP_T::VREF

VREF

Offset: 0x0C Analog Comparator Reference Voltage Control Register

Bits Field Descriptions
[3:0] CRVCTL Comparator Reference Voltage Control
Comparator reference voltage = AVDD * (1 / 6 + CRVCTL(ACMP_VREF[3:0]) / 24).
[7] IREFSEL CRV Internal Reference Selection
0 = Band-gap voltage.
1 = Internal comparator reference voltage.

Definition at line 260 of file Mini58Series.h.