53#ifndef __MINI58SERIES_H__
54#define __MINI58SERIES_H__
125#define __CM0_REV 0x0201
126#define __NVIC_PRIO_BITS 2
127#define __Vendor_SysTickConfig 0
128#define __MPU_PRESENT 0
129#define __FPU_PRESENT 0
146#if defined ( __CC_ARM )
213 __IO uint32_t CTL[2];
269#define ACMP_CTL_ACMPEN_Pos (0)
270#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
272#define ACMP_CTL_ACMPIE_Pos (1)
273#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
275#define ACMP_CTL_HYSSEL_Pos (2)
276#define ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
278#define ACMP_CTL_NEGSEL_Pos (4)
279#define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
281#define ACMP_CTL_RTRGEN_Pos (8)
282#define ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
284#define ACMP_CTL_FTRGEN_Pos (9)
285#define ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
287#define ACMP_CTL_FILTSEL_Pos (20)
288#define ACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
290#define ACMP_CTL_POSSEL_Pos (29)
291#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
293#define ACMP_STATUS_ACMPIF0_Pos (0)
294#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
296#define ACMP_STATUS_ACMPIF1_Pos (1)
297#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
299#define ACMP_STATUS_ACMPO0_Pos (2)
300#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
302#define ACMP_STATUS_ACMPO1_Pos (3)
303#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
305#define ACMP_VREF_CRVCTL_Pos (0)
306#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
308#define ACMP_VREF_IREFSEL_Pos (7)
309#define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
346 __I uint32_t RESERVED0[7];
522 __I uint32_t RESERVED1[4];
664#define ADC_DAT_RESULT_Pos (0)
665#define ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
667#define ADC_DAT_OV_Pos (16)
668#define ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
670#define ADC_DAT_VALID_Pos (17)
671#define ADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
673#define ADC_CTL_ADCEN_Pos (0)
674#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
676#define ADC_CTL_ADCIEN_Pos (1)
677#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
679#define ADC_CTL_HWTRGSEL_Pos (4)
680#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
682#define ADC_CTL_HWTRGCOND_Pos (6)
683#define ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
685#define ADC_CTL_HWTRGEN_Pos (8)
686#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
688#define ADC_CTL_SWTRG_Pos (11)
689#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
691#define ADC_CHEN_CHEN0_Pos (0)
692#define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
694#define ADC_CHEN_CHEN1_Pos (1)
695#define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
697#define ADC_CHEN_CHEN2_Pos (2)
698#define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
700#define ADC_CHEN_CHEN3_Pos (3)
701#define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
703#define ADC_CHEN_CHEN4_Pos (4)
704#define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
706#define ADC_CHEN_CHEN5_Pos (5)
707#define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
709#define ADC_CHEN_CHEN6_Pos (6)
710#define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
712#define ADC_CHEN_CHEN7_Pos (7)
713#define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
715#define ADC_CHEN_CH7SEL_Pos (8)
716#define ADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
718#define ADC_CMP0_ADCMPEN_Pos (0)
719#define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
721#define ADC_CMP0_ADCMPIE_Pos (1)
722#define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
724#define ADC_CMP0_CMPCOND_Pos (2)
725#define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
727#define ADC_CMP0_CMPCH_Pos (3)
728#define ADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
730#define ADC_CMP0_CMPMCNT_Pos (8)
731#define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
733#define ADC_CMP0_CMPDAT_Pos (16)
734#define ADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
736#define ADC_CMP1_ADCMPEN_Pos (0)
737#define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
739#define ADC_CMP1_ADCMPIE_Pos (1)
740#define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
742#define ADC_CMP1_CMPCOND_Pos (2)
743#define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
745#define ADC_CMP1_CMPCH_Pos (3)
746#define ADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
748#define ADC_CMP1_CMPMCNT_Pos (8)
749#define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
751#define ADC_CMP1_CMPDAT_Pos (16)
752#define ADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
754#define ADC_STATUS_ADIF_Pos (0)
755#define ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
757#define ADC_STATUS_ADCMPF0_Pos (1)
758#define ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)
760#define ADC_STATUS_ADCMPF1_Pos (2)
761#define ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)
763#define ADC_STATUS_BUSY_Pos (3)
764#define ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)
766#define ADC_STATUS_CHANNEL_Pos (4)
767#define ADC_STATUS_CHANNEL_Msk (0x7ul << ADC_STATUS_CHANNEL_Pos)
769#define ADC_STATUS_VALID_Pos (8)
770#define ADC_STATUS_VALID_Msk (0x1ul << ADC_STATUS_VALID_Pos)
772#define ADC_STATUS_OV_Pos (16)
773#define ADC_STATUS_OV_Msk (0x1ul << ADC_STATUS_OV_Pos)
775#define ADC_TRGDLY_DELAY_Pos (0)
776#define ADC_TRGDLY_DELAY_Msk (0xfful << ADC_TRGDLY_DELAY_Pos)
778#define ADC_EXTSMPT_EXTSMPT_Pos (0)
779#define ADC_EXTSMPT_EXTSMPT_Msk (0xful << ADC_EXTSMPT_EXTSMPT_Pos)
781#define ADC_SEQCTL_SEQEN_Pos (0)
782#define ADC_SEQCTL_SEQEN_Msk (0x1ul << ADC_SEQCTL_SEQEN_Pos)
784#define ADC_SEQCTL_SEQTYPE_Pos (1)
785#define ADC_SEQCTL_SEQTYPE_Msk (0x1ul << ADC_SEQCTL_SEQTYPE_Pos)
787#define ADC_SEQCTL_MODESEL_Pos (2)
788#define ADC_SEQCTL_MODESEL_Msk (0x3ul << ADC_SEQCTL_MODESEL_Pos)
790#define ADC_SEQCTL_TRG1CTL_Pos (8)
791#define ADC_SEQCTL_TRG1CTL_Msk (0xful << ADC_SEQCTL_TRG1CTL_Pos)
793#define ADC_SEQCTL_TRG2CTL_Pos (16)
794#define ADC_SEQCTL_TRG2CTL_Msk (0xful << ADC_SEQCTL_TRG2CTL_Pos)
796#define ADC_SEQDAT1_RESULT_Pos (0)
797#define ADC_SEQDAT1_RESULT_Msk (0x3fful << ADC_SEQDAT1_RESULT_Pos)
799#define ADC_SEQDAT1_OV_Pos (16)
800#define ADC_SEQDAT1_OV_Msk (0x1ul << ADC_SEQDAT1_OV_Pos)
802#define ADC_SEQDAT1_VALID_Pos (17)
803#define ADC_SEQDAT1_VALID_Msk (0x1ul << ADC_SEQDAT1_VALID_Pos)
805#define ADC_SEQDAT2_RESULT_Pos (0)
806#define ADC_SEQDAT2_RESULT_Msk (0x3fful << ADC_SEQDAT2_RESULT_Pos)
808#define ADC_SEQDAT2_OV_Pos (16)
809#define ADC_SEQDAT2_OV_Msk (0x1ul << ADC_SEQDAT2_OV_Pos)
811#define ADC_SEQDAT2_VALID_Pos (17)
812#define ADC_SEQDAT2_VALID_Msk (0x1ul << ADC_SEQDAT2_VALID_Pos)
1175#define CLK_PWRCTL_XTLEN_Pos (0)
1176#define CLK_PWRCTL_XTLEN_Msk (0x3ul << CLK_PWRCTL_XTLEN_Pos)
1178#define CLK_PWRCTL_HIRCEN_Pos (2)
1179#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
1181#define CLK_PWRCTL_LIRCEN_Pos (3)
1182#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
1184#define CLK_PWRCTL_PDWKDLY_Pos (4)
1185#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
1187#define CLK_PWRCTL_PDWKIEN_Pos (5)
1188#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
1190#define CLK_PWRCTL_PDWKIF_Pos (6)
1191#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
1193#define CLK_PWRCTL_PDEN_Pos (7)
1194#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
1196#define CLK_PWRCTL_PDLXT_Pos (9)
1197#define CLK_PWRCTL_PDLXT_Msk (0x1ul << CLK_PWRCTL_PDLXT_Pos)
1199#define CLK_AHBCLK_ISPCKEN_Pos (2)
1200#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
1202#define CLK_APBCLK_WDTCKEN_Pos (0)
1203#define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos)
1205#define CLK_APBCLK_TMR0CKEN_Pos (2)
1206#define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos)
1208#define CLK_APBCLK_TMR1CKEN_Pos (3)
1209#define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos)
1211#define CLK_APBCLK_CLKOCKEN_Pos (6)
1212#define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos)
1214#define CLK_APBCLK_I2C0CKEN_Pos (8)
1215#define CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos)
1217#define CLK_APBCLK_I2C1CKEN_Pos (9)
1218#define CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos)
1220#define CLK_APBCLK_SPICKEN_Pos (12)
1221#define CLK_APBCLK_SPICKEN_Msk (0x1ul << CLK_APBCLK_SPICKEN_Pos)
1223#define CLK_APBCLK_UART0CKEN_Pos (16)
1224#define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos)
1226#define CLK_APBCLK_UART1CKEN_Pos (17)
1227#define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos)
1229#define CLK_APBCLK_PWMCH01CKEN_Pos (20)
1230#define CLK_APBCLK_PWMCH01CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH01CKEN_Pos)
1232#define CLK_APBCLK_PWMCH23CKEN_Pos (21)
1233#define CLK_APBCLK_PWMCH23CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH23CKEN_Pos)
1235#define CLK_APBCLK_PWMCH45CKEN_Pos (22)
1236#define CLK_APBCLK_PWMCH45CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH45CKEN_Pos)
1238#define CLK_APBCLK_ADCCKEN_Pos (28)
1239#define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos)
1241#define CLK_APBCLK_ACMPCKEN_Pos (30)
1242#define CLK_APBCLK_ACMPCKEN_Msk (0x1ul << CLK_APBCLK_ACMPCKEN_Pos)
1244#define CLK_STATUS_XTLSTB_Pos (0)
1245#define CLK_STATUS_XTLSTB_Msk (0x1ul << CLK_STATUS_XTLSTB_Pos)
1247#define CLK_STATUS_PLLSTB_Pos (2)
1248#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
1250#define CLK_STATUS_LIRCSTB_Pos (3)
1251#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
1253#define CLK_STATUS_HIRCSTB_Pos (4)
1254#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
1256#define CLK_STATUS_CLKSFAIL_Pos (7)
1257#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
1259#define CLK_CLKSEL0_HCLKSEL_Pos (0)
1260#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
1262#define CLK_CLKSEL0_STCLKSEL_Pos (3)
1263#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
1265#define CLK_CLKSEL1_WDTSEL_Pos (0)
1266#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
1268#define CLK_CLKSEL1_ADCSEL_Pos (2)
1269#define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos)
1271#define CLK_CLKSEL1_SPISEL_Pos (4)
1272#define CLK_CLKSEL1_SPISEL_Msk (0x3ul << CLK_CLKSEL1_SPISEL_Pos)
1274#define CLK_CLKSEL1_TMR0SEL_Pos (8)
1275#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
1277#define CLK_CLKSEL1_TMR1SEL_Pos (12)
1278#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
1280#define CLK_CLKSEL1_UARTSEL_Pos (24)
1281#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos)
1283#define CLK_CLKSEL1_PWMCH01SEL_Pos (28)
1284#define CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
1286#define CLK_CLKSEL1_PWMCH23SEL_Pos (30)
1287#define CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
1289#define CLK_CLKDIV_HCLKDIV_Pos (0)
1290#define CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
1292#define CLK_CLKDIV_UARTDIV_Pos (8)
1293#define CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
1295#define CLK_CLKDIV_ADCDIV_Pos (16)
1296#define CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
1298#define CLK_CLKSEL2_CLKOSEL_Pos (2)
1299#define CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
1301#define CLK_CLKSEL2_PWMCH45SEL_Pos (4)
1302#define CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
1304#define CLK_CLKSEL2_WWDTSEL_Pos (16)
1305#define CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
1307#define CLK_PLLCTL_FBDIV_Pos (0)
1308#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
1310#define CLK_PLLCTL_INDIV_Pos (9)
1311#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
1313#define CLK_PLLCTL_OUTDIV_Pos (14)
1314#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
1316#define CLK_PLLCTL_PD_Pos (16)
1317#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
1319#define CLK_PLLCTL_BP_Pos (17)
1320#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
1322#define CLK_PLLCTL_OE_Pos (18)
1323#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
1325#define CLK_PLLCTL_PLLSRC_Pos (19)
1326#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
1328#define CLK_CLKOCTL_FREQSEL_Pos (0)
1329#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
1331#define CLK_CLKOCTL_CLKOEN_Pos (4)
1332#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
1334#define CLK_CLKOCTL_DIV1EN_Pos (5)
1335#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
1491 __I uint32_t RESERVED0[9];
1539#define FMC_ISPCTL_ISPEN_Pos (0)
1540#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
1542#define FMC_ISPCTL_BS_Pos (1)
1543#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
1545#define FMC_ISPCTL_SPUEN_Pos (2)
1546#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
1548#define FMC_ISPCTL_APUEN_Pos (3)
1549#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
1551#define FMC_ISPCTL_CFGUEN_Pos (4)
1552#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
1554#define FMC_ISPCTL_LDUEN_Pos (5)
1555#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
1557#define FMC_ISPCTL_ISPFF_Pos (6)
1558#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
1560#define FMC_ISPADDR_ISPADDR_Pos (0)
1561#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
1563#define FMC_ISPDAT_ISPDAT_Pos (0)
1564#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
1566#define FMC_ISPCMD_CMD_Pos (0)
1567#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
1569#define FMC_ISPTRG_ISPGO_Pos (0)
1570#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
1572#define FMC_DFBA_DFBA_Pos (0)
1573#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
1575#define FMC_FATCTL_FOM_Pos (4)
1576#define FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
1578#define FMC_ISPSTS_ISPBUSY_Pos (0)
1579#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
1581#define FMC_ISPSTS_CBS_Pos (1)
1582#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
1584#define FMC_ISPSTS_ISPFF_Pos (6)
1585#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
1587#define FMC_ISPSTS_VECMAP_Pos (9)
1588#define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
1590#define FMC_ISPSTS_SCODE_Pos (31)
1591#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
2984#define GP_MODE_MODE0_Pos (0)
2985#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
2987#define GP_MODE_MODE1_Pos (2)
2988#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
2990#define GP_MODE_MODE2_Pos (4)
2991#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
2993#define GP_MODE_MODE3_Pos (6)
2994#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
2996#define GP_MODE_MODE4_Pos (8)
2997#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
2999#define GP_MODE_MODE5_Pos (10)
3000#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
3002#define GP_DINOFF_DINOFF0_Pos (16)
3003#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
3005#define GP_DINOFF_DINOFF1_Pos (17)
3006#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
3008#define GP_DINOFF_DINOFF2_Pos (18)
3009#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
3011#define GP_DINOFF_DINOFF3_Pos (19)
3012#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
3014#define GP_DINOFF_DINOFF4_Pos (20)
3015#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
3017#define GP_DINOFF_DINOFF5_Pos (21)
3018#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
3020#define GP_DINOFF_DINOFF6_Pos (22)
3021#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
3023#define GP_DINOFF_DINOFF7_Pos (23)
3024#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
3026#define GP_DOUT_DOUT0_Pos (0)
3027#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
3029#define GP_DOUT_DOUT1_Pos (1)
3030#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
3032#define GP_DOUT_DOUT2_Pos (2)
3033#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
3035#define GP_DOUT_DOUT3_Pos (3)
3036#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
3038#define GP_DOUT_DOUT4_Pos (4)
3039#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
3041#define GP_DOUT_DOUT5_Pos (5)
3042#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
3044#define GP_DOUT_DOUT6_Pos (6)
3045#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
3047#define GP_DOUT_DOUT7_Pos (7)
3048#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
3050#define GP_DATMSK_DATMSK0_Pos (0)
3051#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
3053#define GP_DATMSK_DATMSK1_Pos (1)
3054#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
3056#define GP_DATMSK_DATMSK2_Pos (2)
3057#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
3059#define GP_DATMSK_DATMSK3_Pos (3)
3060#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
3062#define GP_DATMSK_DATMSK4_Pos (4)
3063#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
3065#define GP_DATMSK_DATMSK5_Pos (5)
3066#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
3068#define GP_DATMSK_DATMSK6_Pos (6)
3069#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
3071#define GP_DATMSK_DATMSK7_Pos (7)
3072#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
3074#define GP_PIN_PIN0_Pos (0)
3075#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
3077#define GP_PIN_PIN1_Pos (1)
3078#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
3080#define GP_PIN_PIN2_Pos (2)
3081#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
3083#define GP_PIN_PIN3_Pos (3)
3084#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
3086#define GP_PIN_PIN4_Pos (4)
3087#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
3089#define GP_PIN_PIN5_Pos (5)
3090#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
3092#define GP_PIN_PIN6_Pos (6)
3093#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
3095#define GP_PIN_PIN7_Pos (7)
3096#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
3098#define GP_DBEN_DBEN0_Pos (0)
3099#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
3101#define GP_DBEN_DBEN1_Pos (1)
3102#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
3104#define GP_DBEN_DBEN2_Pos (2)
3105#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
3107#define GP_DBEN_DBEN3_Pos (3)
3108#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
3110#define GP_DBEN_DBEN4_Pos (4)
3111#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
3113#define GP_DBEN_DBEN5_Pos (5)
3114#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
3116#define GP_DBEN_DBEN6_Pos (6)
3117#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
3119#define GP_DBEN_DBEN7_Pos (7)
3120#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
3122#define GP_INTTYPE_TYPE0_Pos (0)
3123#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
3125#define GP_INTTYPE_TYPE1_Pos (1)
3126#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
3128#define GP_INTTYPE_TYPE2_Pos (2)
3129#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
3131#define GP_INTTYPE_TYPE3_Pos (3)
3132#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
3134#define GP_INTTYPE_TYPE4_Pos (4)
3135#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
3137#define GP_INTTYPE_TYPE5_Pos (5)
3138#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
3140#define GP_INTTYPE_TYPE6_Pos (6)
3141#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
3143#define GP_INTTYPE_TYPE7_Pos (7)
3144#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
3146#define GP_INTEN_FLIEN0_Pos (0)
3147#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
3149#define GP_INTEN_FLIEN1_Pos (1)
3150#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
3152#define GP_INTEN_FLIEN2_Pos (2)
3153#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
3155#define GP_INTEN_FLIEN3_Pos (3)
3156#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
3158#define GP_INTEN_FLIEN4_Pos (4)
3159#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
3161#define GP_INTEN_FLIEN5_Pos (5)
3162#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
3164#define GP_INTEN_FLIEN6_Pos (6)
3165#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
3167#define GP_INTEN_FLIEN7_Pos (7)
3168#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
3170#define GP_INTEN_RHIEN0_Pos (16)
3171#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
3173#define GP_INTEN_RHIEN1_Pos (17)
3174#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
3176#define GP_INTEN_RHIEN2_Pos (18)
3177#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
3179#define GP_INTEN_RHIEN3_Pos (19)
3180#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
3182#define GP_INTEN_RHIEN4_Pos (20)
3183#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
3185#define GP_INTEN_RHIEN5_Pos (21)
3186#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
3188#define GP_INTEN_RHIEN6_Pos (22)
3189#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
3191#define GP_INTEN_RHIEN7_Pos (23)
3192#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
3194#define GP_INTSRC_INTSRC0_Pos (0)
3195#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
3197#define GP_INTSRC_INTSRC1_Pos (1)
3198#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
3200#define GP_INTSRC_INTSRC2_Pos (2)
3201#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
3203#define GP_INTSRC_INTSRC3_Pos (3)
3204#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
3206#define GP_INTSRC_INTSRC4_Pos (4)
3207#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
3209#define GP_INTSRC_INTSRC5_Pos (5)
3210#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
3212#define GP_INTSRC_INTSRC6_Pos (6)
3213#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
3215#define GP_INTSRC_INTSRC7_Pos (7)
3216#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
3218#define GP_INTSRC_INTSRC8_Pos (8)
3219#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
3221#define GP_INTSRC_INTSRC9_Pos (9)
3222#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
3224#define GP_INTSRC_INTSRC10_Pos (10)
3225#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
3227#define GP_INTSRC_INTSRC11_Pos (11)
3228#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
3230#define GP_INTSRC_INTSRC12_Pos (12)
3231#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
3233#define GP_INTSRC_INTSRC13_Pos (13)
3234#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
3236#define GP_INTSRC_INTSRC14_Pos (14)
3237#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
3239#define GP_INTSRC_INTSRC15_Pos (15)
3240#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
3242#define GP_MODE_MODE0_Pos (0)
3243#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
3245#define GP_MODE_MODE1_Pos (2)
3246#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
3248#define GP_MODE_MODE2_Pos (4)
3249#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
3251#define GP_MODE_MODE3_Pos (6)
3252#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
3254#define GP_MODE_MODE4_Pos (8)
3255#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
3257#define GP_MODE_MODE5_Pos (10)
3258#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
3260#define GP_DINOFF_DINOFF0_Pos (16)
3261#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
3263#define GP_DINOFF_DINOFF1_Pos (17)
3264#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
3266#define GP_DINOFF_DINOFF2_Pos (18)
3267#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
3269#define GP_DINOFF_DINOFF3_Pos (19)
3270#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
3272#define GP_DINOFF_DINOFF4_Pos (20)
3273#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
3275#define GP_DINOFF_DINOFF5_Pos (21)
3276#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
3278#define GP_DINOFF_DINOFF6_Pos (22)
3279#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
3281#define GP_DINOFF_DINOFF7_Pos (23)
3282#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
3284#define GP_DOUT_DOUT0_Pos (0)
3285#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
3287#define GP_DOUT_DOUT1_Pos (1)
3288#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
3290#define GP_DOUT_DOUT2_Pos (2)
3291#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
3293#define GP_DOUT_DOUT3_Pos (3)
3294#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
3296#define GP_DOUT_DOUT4_Pos (4)
3297#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
3299#define GP_DOUT_DOUT5_Pos (5)
3300#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
3302#define GP_DOUT_DOUT6_Pos (6)
3303#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
3305#define GP_DOUT_DOUT7_Pos (7)
3306#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
3308#define GP_DATMSK_DATMSK0_Pos (0)
3309#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
3311#define GP_DATMSK_DATMSK1_Pos (1)
3312#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
3314#define GP_DATMSK_DATMSK2_Pos (2)
3315#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
3317#define GP_DATMSK_DATMSK3_Pos (3)
3318#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
3320#define GP_DATMSK_DATMSK4_Pos (4)
3321#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
3323#define GP_DATMSK_DATMSK5_Pos (5)
3324#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
3326#define GP_DATMSK_DATMSK6_Pos (6)
3327#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
3329#define GP_DATMSK_DATMSK7_Pos (7)
3330#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
3332#define GP_PIN_PIN0_Pos (0)
3333#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
3335#define GP_PIN_PIN1_Pos (1)
3336#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
3338#define GP_PIN_PIN2_Pos (2)
3339#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
3341#define GP_PIN_PIN3_Pos (3)
3342#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
3344#define GP_PIN_PIN4_Pos (4)
3345#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
3347#define GP_PIN_PIN5_Pos (5)
3348#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
3350#define GP_PIN_PIN6_Pos (6)
3351#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
3353#define GP_PIN_PIN7_Pos (7)
3354#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
3356#define GP_DBEN_DBEN0_Pos (0)
3357#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
3359#define GP_DBEN_DBEN1_Pos (1)
3360#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
3362#define GP_DBEN_DBEN2_Pos (2)
3363#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
3365#define GP_DBEN_DBEN3_Pos (3)
3366#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
3368#define GP_DBEN_DBEN4_Pos (4)
3369#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
3371#define GP_DBEN_DBEN5_Pos (5)
3372#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
3374#define GP_DBEN_DBEN6_Pos (6)
3375#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
3377#define GP_DBEN_DBEN7_Pos (7)
3378#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
3380#define GP_INTTYPE_TYPE0_Pos (0)
3381#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
3383#define GP_INTTYPE_TYPE1_Pos (1)
3384#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
3386#define GP_INTTYPE_TYPE2_Pos (2)
3387#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
3389#define GP_INTTYPE_TYPE3_Pos (3)
3390#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
3392#define GP_INTTYPE_TYPE4_Pos (4)
3393#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
3395#define GP_INTTYPE_TYPE5_Pos (5)
3396#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
3398#define GP_INTTYPE_TYPE6_Pos (6)
3399#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
3401#define GP_INTTYPE_TYPE7_Pos (7)
3402#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
3404#define GP_INTEN_FLIEN0_Pos (0)
3405#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
3407#define GP_INTEN_FLIEN1_Pos (1)
3408#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
3410#define GP_INTEN_FLIEN2_Pos (2)
3411#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
3413#define GP_INTEN_FLIEN3_Pos (3)
3414#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
3416#define GP_INTEN_FLIEN4_Pos (4)
3417#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
3419#define GP_INTEN_FLIEN5_Pos (5)
3420#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
3422#define GP_INTEN_FLIEN6_Pos (6)
3423#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
3425#define GP_INTEN_FLIEN7_Pos (7)
3426#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
3428#define GP_INTEN_RHIEN0_Pos (16)
3429#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
3431#define GP_INTEN_RHIEN1_Pos (17)
3432#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
3434#define GP_INTEN_RHIEN2_Pos (18)
3435#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
3437#define GP_INTEN_RHIEN3_Pos (19)
3438#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
3440#define GP_INTEN_RHIEN4_Pos (20)
3441#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
3443#define GP_INTEN_RHIEN5_Pos (21)
3444#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
3446#define GP_INTEN_RHIEN6_Pos (22)
3447#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
3449#define GP_INTEN_RHIEN7_Pos (23)
3450#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
3452#define GP_INTSRC_INTSRC0_Pos (0)
3453#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
3455#define GP_INTSRC_INTSRC1_Pos (1)
3456#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
3458#define GP_INTSRC_INTSRC2_Pos (2)
3459#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
3461#define GP_INTSRC_INTSRC3_Pos (3)
3462#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
3464#define GP_INTSRC_INTSRC4_Pos (4)
3465#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
3467#define GP_INTSRC_INTSRC5_Pos (5)
3468#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
3470#define GP_INTSRC_INTSRC6_Pos (6)
3471#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
3473#define GP_INTSRC_INTSRC7_Pos (7)
3474#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
3476#define GP_INTSRC_INTSRC8_Pos (8)
3477#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
3479#define GP_INTSRC_INTSRC9_Pos (9)
3480#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
3482#define GP_INTSRC_INTSRC10_Pos (10)
3483#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
3485#define GP_INTSRC_INTSRC11_Pos (11)
3486#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
3488#define GP_INTSRC_INTSRC12_Pos (12)
3489#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
3491#define GP_INTSRC_INTSRC13_Pos (13)
3492#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
3494#define GP_INTSRC_INTSRC14_Pos (14)
3495#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
3497#define GP_INTSRC_INTSRC15_Pos (15)
3498#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
3500#define GP_MODE_MODE0_Pos (0)
3501#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
3503#define GP_MODE_MODE1_Pos (2)
3504#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
3506#define GP_MODE_MODE2_Pos (4)
3507#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
3509#define GP_MODE_MODE3_Pos (6)
3510#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
3512#define GP_MODE_MODE4_Pos (8)
3513#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
3515#define GP_MODE_MODE5_Pos (10)
3516#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
3518#define GP_DINOFF_DINOFF0_Pos (16)
3519#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
3521#define GP_DINOFF_DINOFF1_Pos (17)
3522#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
3524#define GP_DINOFF_DINOFF2_Pos (18)
3525#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
3527#define GP_DINOFF_DINOFF3_Pos (19)
3528#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
3530#define GP_DINOFF_DINOFF4_Pos (20)
3531#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
3533#define GP_DINOFF_DINOFF5_Pos (21)
3534#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
3536#define GP_DINOFF_DINOFF6_Pos (22)
3537#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
3539#define GP_DINOFF_DINOFF7_Pos (23)
3540#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
3542#define GP_DOUT_DOUT0_Pos (0)
3543#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
3545#define GP_DOUT_DOUT1_Pos (1)
3546#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
3548#define GP_DOUT_DOUT2_Pos (2)
3549#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
3551#define GP_DOUT_DOUT3_Pos (3)
3552#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
3554#define GP_DOUT_DOUT4_Pos (4)
3555#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
3557#define GP_DOUT_DOUT5_Pos (5)
3558#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
3560#define GP_DOUT_DOUT6_Pos (6)
3561#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
3563#define GP_DOUT_DOUT7_Pos (7)
3564#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
3566#define GP_DATMSK_DATMSK0_Pos (0)
3567#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
3569#define GP_DATMSK_DATMSK1_Pos (1)
3570#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
3572#define GP_DATMSK_DATMSK2_Pos (2)
3573#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
3575#define GP_DATMSK_DATMSK3_Pos (3)
3576#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
3578#define GP_DATMSK_DATMSK4_Pos (4)
3579#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
3581#define GP_DATMSK_DATMSK5_Pos (5)
3582#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
3584#define GP_DATMSK_DATMSK6_Pos (6)
3585#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
3587#define GP_DATMSK_DATMSK7_Pos (7)
3588#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
3590#define GP_PIN_PIN0_Pos (0)
3591#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
3593#define GP_PIN_PIN1_Pos (1)
3594#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
3596#define GP_PIN_PIN2_Pos (2)
3597#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
3599#define GP_PIN_PIN3_Pos (3)
3600#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
3602#define GP_PIN_PIN4_Pos (4)
3603#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
3605#define GP_PIN_PIN5_Pos (5)
3606#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
3608#define GP_PIN_PIN6_Pos (6)
3609#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
3611#define GP_PIN_PIN7_Pos (7)
3612#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
3614#define GP_DBEN_DBEN0_Pos (0)
3615#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
3617#define GP_DBEN_DBEN1_Pos (1)
3618#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
3620#define GP_DBEN_DBEN2_Pos (2)
3621#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
3623#define GP_DBEN_DBEN3_Pos (3)
3624#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
3626#define GP_DBEN_DBEN4_Pos (4)
3627#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
3629#define GP_DBEN_DBEN5_Pos (5)
3630#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
3632#define GP_DBEN_DBEN6_Pos (6)
3633#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
3635#define GP_DBEN_DBEN7_Pos (7)
3636#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
3638#define GP_INTTYPE_TYPE0_Pos (0)
3639#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
3641#define GP_INTTYPE_TYPE1_Pos (1)
3642#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
3644#define GP_INTTYPE_TYPE2_Pos (2)
3645#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
3647#define GP_INTTYPE_TYPE3_Pos (3)
3648#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
3650#define GP_INTTYPE_TYPE4_Pos (4)
3651#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
3653#define GP_INTTYPE_TYPE5_Pos (5)
3654#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
3656#define GP_INTTYPE_TYPE6_Pos (6)
3657#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
3659#define GP_INTTYPE_TYPE7_Pos (7)
3660#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
3662#define GP_INTEN_FLIEN0_Pos (0)
3663#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
3665#define GP_INTEN_FLIEN1_Pos (1)
3666#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
3668#define GP_INTEN_FLIEN2_Pos (2)
3669#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
3671#define GP_INTEN_FLIEN3_Pos (3)
3672#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
3674#define GP_INTEN_FLIEN4_Pos (4)
3675#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
3677#define GP_INTEN_FLIEN5_Pos (5)
3678#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
3680#define GP_INTEN_FLIEN6_Pos (6)
3681#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
3683#define GP_INTEN_FLIEN7_Pos (7)
3684#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
3686#define GP_INTEN_RHIEN0_Pos (16)
3687#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
3689#define GP_INTEN_RHIEN1_Pos (17)
3690#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
3692#define GP_INTEN_RHIEN2_Pos (18)
3693#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
3695#define GP_INTEN_RHIEN3_Pos (19)
3696#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
3698#define GP_INTEN_RHIEN4_Pos (20)
3699#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
3701#define GP_INTEN_RHIEN5_Pos (21)
3702#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
3704#define GP_INTEN_RHIEN6_Pos (22)
3705#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
3707#define GP_INTEN_RHIEN7_Pos (23)
3708#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
3710#define GP_INTSRC_INTSRC0_Pos (0)
3711#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
3713#define GP_INTSRC_INTSRC1_Pos (1)
3714#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
3716#define GP_INTSRC_INTSRC2_Pos (2)
3717#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
3719#define GP_INTSRC_INTSRC3_Pos (3)
3720#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
3722#define GP_INTSRC_INTSRC4_Pos (4)
3723#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
3725#define GP_INTSRC_INTSRC5_Pos (5)
3726#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
3728#define GP_INTSRC_INTSRC6_Pos (6)
3729#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
3731#define GP_INTSRC_INTSRC7_Pos (7)
3732#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
3734#define GP_INTSRC_INTSRC8_Pos (8)
3735#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
3737#define GP_INTSRC_INTSRC9_Pos (9)
3738#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
3740#define GP_INTSRC_INTSRC10_Pos (10)
3741#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
3743#define GP_INTSRC_INTSRC11_Pos (11)
3744#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
3746#define GP_INTSRC_INTSRC12_Pos (12)
3747#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
3749#define GP_INTSRC_INTSRC13_Pos (13)
3750#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
3752#define GP_INTSRC_INTSRC14_Pos (14)
3753#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
3755#define GP_INTSRC_INTSRC15_Pos (15)
3756#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
3758#define GP_MODE_MODE0_Pos (0)
3759#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
3761#define GP_MODE_MODE1_Pos (2)
3762#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
3764#define GP_MODE_MODE2_Pos (4)
3765#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
3767#define GP_MODE_MODE3_Pos (6)
3768#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
3770#define GP_MODE_MODE4_Pos (8)
3771#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
3773#define GP_MODE_MODE5_Pos (10)
3774#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
3776#define GP_DINOFF_DINOFF0_Pos (16)
3777#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
3779#define GP_DINOFF_DINOFF1_Pos (17)
3780#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
3782#define GP_DINOFF_DINOFF2_Pos (18)
3783#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
3785#define GP_DINOFF_DINOFF3_Pos (19)
3786#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
3788#define GP_DINOFF_DINOFF4_Pos (20)
3789#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
3791#define GP_DINOFF_DINOFF5_Pos (21)
3792#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
3794#define GP_DINOFF_DINOFF6_Pos (22)
3795#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
3797#define GP_DINOFF_DINOFF7_Pos (23)
3798#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
3800#define GP_DOUT_DOUT0_Pos (0)
3801#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
3803#define GP_DOUT_DOUT1_Pos (1)
3804#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
3806#define GP_DOUT_DOUT2_Pos (2)
3807#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
3809#define GP_DOUT_DOUT3_Pos (3)
3810#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
3812#define GP_DOUT_DOUT4_Pos (4)
3813#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
3815#define GP_DOUT_DOUT5_Pos (5)
3816#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
3818#define GP_DOUT_DOUT6_Pos (6)
3819#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
3821#define GP_DOUT_DOUT7_Pos (7)
3822#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
3824#define GP_DATMSK_DATMSK0_Pos (0)
3825#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
3827#define GP_DATMSK_DATMSK1_Pos (1)
3828#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
3830#define GP_DATMSK_DATMSK2_Pos (2)
3831#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
3833#define GP_DATMSK_DATMSK3_Pos (3)
3834#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
3836#define GP_DATMSK_DATMSK4_Pos (4)
3837#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
3839#define GP_DATMSK_DATMSK5_Pos (5)
3840#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
3842#define GP_DATMSK_DATMSK6_Pos (6)
3843#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
3845#define GP_DATMSK_DATMSK7_Pos (7)
3846#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
3848#define GP_PIN_PIN0_Pos (0)
3849#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
3851#define GP_PIN_PIN1_Pos (1)
3852#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
3854#define GP_PIN_PIN2_Pos (2)
3855#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
3857#define GP_PIN_PIN3_Pos (3)
3858#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
3860#define GP_PIN_PIN4_Pos (4)
3861#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
3863#define GP_PIN_PIN5_Pos (5)
3864#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
3866#define GP_PIN_PIN6_Pos (6)
3867#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
3869#define GP_PIN_PIN7_Pos (7)
3870#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
3872#define GP_DBEN_DBEN0_Pos (0)
3873#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
3875#define GP_DBEN_DBEN1_Pos (1)
3876#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
3878#define GP_DBEN_DBEN2_Pos (2)
3879#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
3881#define GP_DBEN_DBEN3_Pos (3)
3882#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
3884#define GP_DBEN_DBEN4_Pos (4)
3885#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
3887#define GP_DBEN_DBEN5_Pos (5)
3888#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
3890#define GP_DBEN_DBEN6_Pos (6)
3891#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
3893#define GP_DBEN_DBEN7_Pos (7)
3894#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
3896#define GP_INTTYPE_TYPE0_Pos (0)
3897#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
3899#define GP_INTTYPE_TYPE1_Pos (1)
3900#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
3902#define GP_INTTYPE_TYPE2_Pos (2)
3903#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
3905#define GP_INTTYPE_TYPE3_Pos (3)
3906#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
3908#define GP_INTTYPE_TYPE4_Pos (4)
3909#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
3911#define GP_INTTYPE_TYPE5_Pos (5)
3912#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
3914#define GP_INTTYPE_TYPE6_Pos (6)
3915#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
3917#define GP_INTTYPE_TYPE7_Pos (7)
3918#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
3920#define GP_INTEN_FLIEN0_Pos (0)
3921#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
3923#define GP_INTEN_FLIEN1_Pos (1)
3924#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
3926#define GP_INTEN_FLIEN2_Pos (2)
3927#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
3929#define GP_INTEN_FLIEN3_Pos (3)
3930#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
3932#define GP_INTEN_FLIEN4_Pos (4)
3933#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
3935#define GP_INTEN_FLIEN5_Pos (5)
3936#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
3938#define GP_INTEN_FLIEN6_Pos (6)
3939#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
3941#define GP_INTEN_FLIEN7_Pos (7)
3942#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
3944#define GP_INTEN_RHIEN0_Pos (16)
3945#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
3947#define GP_INTEN_RHIEN1_Pos (17)
3948#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
3950#define GP_INTEN_RHIEN2_Pos (18)
3951#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
3953#define GP_INTEN_RHIEN3_Pos (19)
3954#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
3956#define GP_INTEN_RHIEN4_Pos (20)
3957#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
3959#define GP_INTEN_RHIEN5_Pos (21)
3960#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
3962#define GP_INTEN_RHIEN6_Pos (22)
3963#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
3965#define GP_INTEN_RHIEN7_Pos (23)
3966#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
3968#define GP_INTSRC_INTSRC0_Pos (0)
3969#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
3971#define GP_INTSRC_INTSRC1_Pos (1)
3972#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
3974#define GP_INTSRC_INTSRC2_Pos (2)
3975#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
3977#define GP_INTSRC_INTSRC3_Pos (3)
3978#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
3980#define GP_INTSRC_INTSRC4_Pos (4)
3981#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
3983#define GP_INTSRC_INTSRC5_Pos (5)
3984#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
3986#define GP_INTSRC_INTSRC6_Pos (6)
3987#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
3989#define GP_INTSRC_INTSRC7_Pos (7)
3990#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
3992#define GP_INTSRC_INTSRC8_Pos (8)
3993#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
3995#define GP_INTSRC_INTSRC9_Pos (9)
3996#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
3998#define GP_INTSRC_INTSRC10_Pos (10)
3999#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
4001#define GP_INTSRC_INTSRC11_Pos (11)
4002#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
4004#define GP_INTSRC_INTSRC12_Pos (12)
4005#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
4007#define GP_INTSRC_INTSRC13_Pos (13)
4008#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
4010#define GP_INTSRC_INTSRC14_Pos (14)
4011#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
4013#define GP_INTSRC_INTSRC15_Pos (15)
4014#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
4016#define GP_MODE_MODE0_Pos (0)
4017#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
4019#define GP_MODE_MODE1_Pos (2)
4020#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
4022#define GP_MODE_MODE2_Pos (4)
4023#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
4025#define GP_MODE_MODE3_Pos (6)
4026#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
4028#define GP_MODE_MODE4_Pos (8)
4029#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
4031#define GP_MODE_MODE5_Pos (10)
4032#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
4034#define GP_DINOFF_DINOFF0_Pos (16)
4035#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
4037#define GP_DINOFF_DINOFF1_Pos (17)
4038#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
4040#define GP_DINOFF_DINOFF2_Pos (18)
4041#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
4043#define GP_DINOFF_DINOFF3_Pos (19)
4044#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
4046#define GP_DINOFF_DINOFF4_Pos (20)
4047#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
4049#define GP_DINOFF_DINOFF5_Pos (21)
4050#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
4052#define GP_DINOFF_DINOFF6_Pos (22)
4053#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
4055#define GP_DINOFF_DINOFF7_Pos (23)
4056#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
4058#define GP_DOUT_DOUT0_Pos (0)
4059#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
4061#define GP_DOUT_DOUT1_Pos (1)
4062#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
4064#define GP_DOUT_DOUT2_Pos (2)
4065#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
4067#define GP_DOUT_DOUT3_Pos (3)
4068#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
4070#define GP_DOUT_DOUT4_Pos (4)
4071#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
4073#define GP_DOUT_DOUT5_Pos (5)
4074#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
4076#define GP_DOUT_DOUT6_Pos (6)
4077#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
4079#define GP_DOUT_DOUT7_Pos (7)
4080#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
4082#define GP_DATMSK_DATMSK0_Pos (0)
4083#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
4085#define GP_DATMSK_DATMSK1_Pos (1)
4086#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
4088#define GP_DATMSK_DATMSK2_Pos (2)
4089#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
4091#define GP_DATMSK_DATMSK3_Pos (3)
4092#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
4094#define GP_DATMSK_DATMSK4_Pos (4)
4095#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
4097#define GP_DATMSK_DATMSK5_Pos (5)
4098#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
4100#define GP_DATMSK_DATMSK6_Pos (6)
4101#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
4103#define GP_DATMSK_DATMSK7_Pos (7)
4104#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
4106#define GP_PIN_PIN0_Pos (0)
4107#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
4109#define GP_PIN_PIN1_Pos (1)
4110#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
4112#define GP_PIN_PIN2_Pos (2)
4113#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
4115#define GP_PIN_PIN3_Pos (3)
4116#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
4118#define GP_PIN_PIN4_Pos (4)
4119#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
4121#define GP_PIN_PIN5_Pos (5)
4122#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
4124#define GP_PIN_PIN6_Pos (6)
4125#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
4127#define GP_PIN_PIN7_Pos (7)
4128#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
4130#define GP_DBEN_DBEN0_Pos (0)
4131#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
4133#define GP_DBEN_DBEN1_Pos (1)
4134#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
4136#define GP_DBEN_DBEN2_Pos (2)
4137#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
4139#define GP_DBEN_DBEN3_Pos (3)
4140#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
4142#define GP_DBEN_DBEN4_Pos (4)
4143#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
4145#define GP_DBEN_DBEN5_Pos (5)
4146#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
4148#define GP_DBEN_DBEN6_Pos (6)
4149#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
4151#define GP_DBEN_DBEN7_Pos (7)
4152#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
4154#define GP_INTTYPE_TYPE0_Pos (0)
4155#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
4157#define GP_INTTYPE_TYPE1_Pos (1)
4158#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
4160#define GP_INTTYPE_TYPE2_Pos (2)
4161#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
4163#define GP_INTTYPE_TYPE3_Pos (3)
4164#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
4166#define GP_INTTYPE_TYPE4_Pos (4)
4167#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
4169#define GP_INTTYPE_TYPE5_Pos (5)
4170#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
4172#define GP_INTTYPE_TYPE6_Pos (6)
4173#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
4175#define GP_INTTYPE_TYPE7_Pos (7)
4176#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
4178#define GP_INTEN_FLIEN0_Pos (0)
4179#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
4181#define GP_INTEN_FLIEN1_Pos (1)
4182#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
4184#define GP_INTEN_FLIEN2_Pos (2)
4185#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
4187#define GP_INTEN_FLIEN3_Pos (3)
4188#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
4190#define GP_INTEN_FLIEN4_Pos (4)
4191#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
4193#define GP_INTEN_FLIEN5_Pos (5)
4194#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
4196#define GP_INTEN_FLIEN6_Pos (6)
4197#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
4199#define GP_INTEN_FLIEN7_Pos (7)
4200#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
4202#define GP_INTEN_RHIEN0_Pos (16)
4203#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
4205#define GP_INTEN_RHIEN1_Pos (17)
4206#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
4208#define GP_INTEN_RHIEN2_Pos (18)
4209#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
4211#define GP_INTEN_RHIEN3_Pos (19)
4212#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
4214#define GP_INTEN_RHIEN4_Pos (20)
4215#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
4217#define GP_INTEN_RHIEN5_Pos (21)
4218#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
4220#define GP_INTEN_RHIEN6_Pos (22)
4221#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
4223#define GP_INTEN_RHIEN7_Pos (23)
4224#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
4226#define GP_INTSRC_INTSRC0_Pos (0)
4227#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
4229#define GP_INTSRC_INTSRC1_Pos (1)
4230#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
4232#define GP_INTSRC_INTSRC2_Pos (2)
4233#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
4235#define GP_INTSRC_INTSRC3_Pos (3)
4236#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
4238#define GP_INTSRC_INTSRC4_Pos (4)
4239#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
4241#define GP_INTSRC_INTSRC5_Pos (5)
4242#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
4244#define GP_INTSRC_INTSRC6_Pos (6)
4245#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
4247#define GP_INTSRC_INTSRC7_Pos (7)
4248#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
4250#define GP_INTSRC_INTSRC8_Pos (8)
4251#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
4253#define GP_INTSRC_INTSRC9_Pos (9)
4254#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
4256#define GP_INTSRC_INTSRC10_Pos (10)
4257#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
4259#define GP_INTSRC_INTSRC11_Pos (11)
4260#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
4262#define GP_INTSRC_INTSRC12_Pos (12)
4263#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
4265#define GP_INTSRC_INTSRC13_Pos (13)
4266#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
4268#define GP_INTSRC_INTSRC14_Pos (14)
4269#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
4271#define GP_INTSRC_INTSRC15_Pos (15)
4272#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
4274#define GP_MODE_MODE0_Pos (0)
4275#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
4277#define GP_MODE_MODE1_Pos (2)
4278#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
4280#define GP_MODE_MODE2_Pos (4)
4281#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
4283#define GP_MODE_MODE3_Pos (6)
4284#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
4286#define GP_MODE_MODE4_Pos (8)
4287#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
4289#define GP_MODE_MODE5_Pos (10)
4290#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
4292#define GP_DINOFF_DINOFF0_Pos (16)
4293#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
4295#define GP_DINOFF_DINOFF1_Pos (17)
4296#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
4298#define GP_DINOFF_DINOFF2_Pos (18)
4299#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
4301#define GP_DINOFF_DINOFF3_Pos (19)
4302#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
4304#define GP_DINOFF_DINOFF4_Pos (20)
4305#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
4307#define GP_DINOFF_DINOFF5_Pos (21)
4308#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
4310#define GP_DINOFF_DINOFF6_Pos (22)
4311#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
4313#define GP_DINOFF_DINOFF7_Pos (23)
4314#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
4316#define GP_DOUT_DOUT0_Pos (0)
4317#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
4319#define GP_DOUT_DOUT1_Pos (1)
4320#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
4322#define GP_DOUT_DOUT2_Pos (2)
4323#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
4325#define GP_DOUT_DOUT3_Pos (3)
4326#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
4328#define GP_DOUT_DOUT4_Pos (4)
4329#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
4331#define GP_DOUT_DOUT5_Pos (5)
4332#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
4334#define GP_DOUT_DOUT6_Pos (6)
4335#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
4337#define GP_DOUT_DOUT7_Pos (7)
4338#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
4340#define GP_DATMSK_DATMSK0_Pos (0)
4341#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
4343#define GP_DATMSK_DATMSK1_Pos (1)
4344#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
4346#define GP_DATMSK_DATMSK2_Pos (2)
4347#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
4349#define GP_DATMSK_DATMSK3_Pos (3)
4350#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
4352#define GP_DATMSK_DATMSK4_Pos (4)
4353#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
4355#define GP_DATMSK_DATMSK5_Pos (5)
4356#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
4358#define GP_DATMSK_DATMSK6_Pos (6)
4359#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
4361#define GP_DATMSK_DATMSK7_Pos (7)
4362#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
4364#define GP_PIN_PIN0_Pos (0)
4365#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
4367#define GP_PIN_PIN1_Pos (1)
4368#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
4370#define GP_PIN_PIN2_Pos (2)
4371#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
4373#define GP_PIN_PIN3_Pos (3)
4374#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
4376#define GP_PIN_PIN4_Pos (4)
4377#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
4379#define GP_PIN_PIN5_Pos (5)
4380#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
4382#define GP_PIN_PIN6_Pos (6)
4383#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
4385#define GP_PIN_PIN7_Pos (7)
4386#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
4388#define GP_DBEN_DBEN0_Pos (0)
4389#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
4391#define GP_DBEN_DBEN1_Pos (1)
4392#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
4394#define GP_DBEN_DBEN2_Pos (2)
4395#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
4397#define GP_DBEN_DBEN3_Pos (3)
4398#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
4400#define GP_DBEN_DBEN4_Pos (4)
4401#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
4403#define GP_DBEN_DBEN5_Pos (5)
4404#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
4406#define GP_DBEN_DBEN6_Pos (6)
4407#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
4409#define GP_DBEN_DBEN7_Pos (7)
4410#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
4412#define GP_INTTYPE_TYPE0_Pos (0)
4413#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
4415#define GP_INTTYPE_TYPE1_Pos (1)
4416#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
4418#define GP_INTTYPE_TYPE2_Pos (2)
4419#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
4421#define GP_INTTYPE_TYPE3_Pos (3)
4422#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
4424#define GP_INTTYPE_TYPE4_Pos (4)
4425#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
4427#define GP_INTTYPE_TYPE5_Pos (5)
4428#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
4430#define GP_INTTYPE_TYPE6_Pos (6)
4431#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
4433#define GP_INTTYPE_TYPE7_Pos (7)
4434#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
4436#define GP_INTEN_FLIEN0_Pos (0)
4437#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
4439#define GP_INTEN_FLIEN1_Pos (1)
4440#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
4442#define GP_INTEN_FLIEN2_Pos (2)
4443#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
4445#define GP_INTEN_FLIEN3_Pos (3)
4446#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
4448#define GP_INTEN_FLIEN4_Pos (4)
4449#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
4451#define GP_INTEN_FLIEN5_Pos (5)
4452#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
4454#define GP_INTEN_FLIEN6_Pos (6)
4455#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
4457#define GP_INTEN_FLIEN7_Pos (7)
4458#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
4460#define GP_INTEN_RHIEN0_Pos (16)
4461#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
4463#define GP_INTEN_RHIEN1_Pos (17)
4464#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
4466#define GP_INTEN_RHIEN2_Pos (18)
4467#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
4469#define GP_INTEN_RHIEN3_Pos (19)
4470#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
4472#define GP_INTEN_RHIEN4_Pos (20)
4473#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
4475#define GP_INTEN_RHIEN5_Pos (21)
4476#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
4478#define GP_INTEN_RHIEN6_Pos (22)
4479#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
4481#define GP_INTEN_RHIEN7_Pos (23)
4482#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
4484#define GP_INTSRC_INTSRC0_Pos (0)
4485#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
4487#define GP_INTSRC_INTSRC1_Pos (1)
4488#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
4490#define GP_INTSRC_INTSRC2_Pos (2)
4491#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
4493#define GP_INTSRC_INTSRC3_Pos (3)
4494#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
4496#define GP_INTSRC_INTSRC4_Pos (4)
4497#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
4499#define GP_INTSRC_INTSRC5_Pos (5)
4500#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
4502#define GP_INTSRC_INTSRC6_Pos (6)
4503#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
4505#define GP_INTSRC_INTSRC7_Pos (7)
4506#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
4508#define GP_INTSRC_INTSRC8_Pos (8)
4509#define GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
4511#define GP_INTSRC_INTSRC9_Pos (9)
4512#define GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
4514#define GP_INTSRC_INTSRC10_Pos (10)
4515#define GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
4517#define GP_INTSRC_INTSRC11_Pos (11)
4518#define GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
4520#define GP_INTSRC_INTSRC12_Pos (12)
4521#define GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
4523#define GP_INTSRC_INTSRC13_Pos (13)
4524#define GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
4526#define GP_INTSRC_INTSRC14_Pos (14)
4527#define GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
4529#define GP_INTSRC_INTSRC15_Pos (15)
4530#define GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
4532#define GP_DBCTL_DBCLKSEL_Pos (0)
4533#define GP_DBCTL_DBCLKSEL_Msk (0xful << GP_DBCTL_DBCLKSEL_Pos)
4535#define GP_DBCTL_DBCLKSRC_Pos (4)
4536#define GP_DBCTL_DBCLKSRC_Msk (0x1ul << GP_DBCTL_DBCLKSRC_Pos)
4538#define GP_DBCTL_ICLKON_Pos (5)
4539#define GP_DBCTL_ICLKON_Msk (0x1ul << GP_DBCTL_ICLKON_Pos)
4776 __I uint32_t RESERVED0[2];
4843#define I2C_CTL_AA_Pos (2)
4844#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
4846#define I2C_CTL_SI_Pos (3)
4847#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
4849#define I2C_CTL_STO_Pos (4)
4850#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
4852#define I2C_CTL_STA_Pos (5)
4853#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
4855#define I2C_CTL_I2CEN_Pos (6)
4856#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
4858#define I2C_CTL_INTEN_Pos (7)
4859#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
4861#define I2C_ADDR0_GC_Pos (0)
4862#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
4864#define I2C_ADDR0_ADDR_Pos (1)
4865#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
4867#define I2C_DAT_DAT_Pos (0)
4868#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
4870#define I2C_STATUS_STATUS_Pos (0)
4871#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
4873#define I2C_CLKDIV_DIVIDER_Pos (0)
4874#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
4876#define I2C_TOCTL_TOIF_Pos (0)
4877#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
4879#define I2C_TOCTL_TOCURIEN_Pos (1)
4880#define I2C_TOCTL_TOCURIEN_Msk (0x1ul << I2C_TOCTL_TOCURIEN_Pos)
4882#define I2C_TOCTL_TOCEN_Pos (2)
4883#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
4885#define I2C_ADDR1_GC_Pos (0)
4886#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
4888#define I2C_ADDR1_ADDR_Pos (1)
4889#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
4891#define I2C_ADDR2_GC_Pos (0)
4892#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
4894#define I2C_ADDR2_ADDR_Pos (1)
4895#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos)
4897#define I2C_ADDR3_GC_Pos (0)
4898#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
4900#define I2C_ADDR3_ADDR_Pos (1)
4901#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos)
4903#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
4904#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
4906#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
4907#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
4909#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
4910#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)
4912#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
4913#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)
4915#define I2C_CTL1_WKEN_Pos (0)
4916#define I2C_CTL1_WKEN_Msk (0x1ul << I2C_CTL1_WKEN_Pos)
4918#define I2C_CTL1_TWOLVFIFO_Pos (1)
4919#define I2C_CTL1_TWOLVFIFO_Msk (0x1ul << I2C_CTL1_TWOLVFIFO_Pos)
4921#define I2C_CTL1_NSTRETCH_Pos (2)
4922#define I2C_CTL1_NSTRETCH_Msk (0x1ul << I2C_CTL1_NSTRETCH_Pos)
4924#define I2C_CTL1_OVIEN_Pos (3)
4925#define I2C_CTL1_OVIEN_Msk (0x1ul << I2C_CTL1_OVIEN_Pos)
4927#define I2C_CTL1_URIEN_Pos (4)
4928#define I2C_CTL1_URIEN_Msk (0x1ul << I2C_CTL1_URIEN_Pos)
4930#define I2C_STATUS1_WKIF_Pos (0)
4931#define I2C_STATUS1_WKIF_Msk (0x1ul << I2C_STATUS1_WKIF_Pos)
4933#define I2C_STATUS1_FULL_Pos (1)
4934#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos)
4936#define I2C_STATUS1_EMPTY_Pos (2)
4937#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos)
4939#define I2C_STATUS1_OVIF_Pos (3)
4940#define I2C_STATUS1_OVIF_Msk (0x1ul << I2C_STATUS1_OVIF_Pos)
4942#define I2C_STATUS1_URIF_Pos (4)
4943#define I2C_STATUS1_URIF_Msk (0x1ul << I2C_STATUS1_URIF_Pos)
5102 uint32_t RESERVE0[2];
5145 uint32_t RESERVE1[1];
5201 uint32_t RESERVE2[5];
5218 uint32_t RESERVE3[2];
5287#define INT_IRQ0_SRC_BOD_INT_Pos (0)
5288#define INT_IRQ0_SRC_BOD_INT_Msk (0x1ul << INT_IRQ0_SRC_BOD_INT_Pos)
5290#define INT_IRQ1_SRC_WDT_INT_Pos (0)
5291#define INT_IRQ1_SRC_WDT_INT_Msk (0x1ul << INT_IRQ1_SRC_WDT_INT_Pos)
5293#define INT_IRQ1_SRC_WWDT_INT_Pos (1)
5294#define INT_IRQ1_SRC_WWDT_INT_Msk (0x1ul << INT_IRQ1_SRC_WWDT_INT_Pos)
5296#define INT_IRQ2_SRC_EINT0_Pos (0)
5297#define INT_IRQ2_SRC_EINT0_Msk (0x1ul << INT_IRQ2_SRC_EINT0_Pos)
5299#define INT_IRQ3_SRC_EINT1_Pos (0)
5300#define INT_IRQ3_SRC_EINT1_Msk (0x1ul << INT_IRQ_SRC3_EINT1_Pos)
5302#define INT_IRQ4_SRC_GP0_INT_Pos (0)
5303#define INT_IRQ4_SRC_GP0_INT_Msk (0x1ul << INT_IRQ4_SRC_GP0_INT_Pos)
5305#define INT_IRQ4_SRC_GP1_INT_Pos (1)
5306#define INT_IRQ4_SRC_GP1_INT_Msk (0x1ul << INT_IRQ4_SRC_GP1_INT_Pos)
5308#define INT_IRQ5_SRC_GP2_INT_Pos (0)
5309#define INT_IRQ5_SRC_GP2_INT_Msk (0x1ul << INT_IRQ5_SRC_GP2_INT_Pos)
5311#define INT_IRQ5_SRC_GP3_INT_Pos (1)
5312#define INT_IRQ5_SRC_GP3_INT_Msk (0x1ul << INT_IRQ5_SRC_GP3_INT_Pos)
5314#define INT_IRQ5_SRC_GP4_INT_Pos (2)
5315#define INT_IRQ5_SRC_GP4_INT_Msk (0x1ul << INT_IRQ5_SRC_GP4_INT_Pos)
5317#define INT_IRQ6_SRC_PWM_INT_Pos (0)
5318#define INT_IRQ6_SRC_PWM_INT_Msk (0x1ul << INT_IRQ6_SRC_PWM_INT_Pos)
5320#define INT_IRQ7_SRC_BRAKE_INT_Pos (0)
5321#define INT_IRQ7_SRC_BRAKE_INT_Msk (0x1ul << INT_IRQ_SRC_BRAKE_INT_Pos)
5323#define INT_IRQ8_SRC_TMR0_INT_Pos (0)
5324#define INT_IRQ8_SRC_TMR0_INT_Msk (0x1ul << INT_IRQ8_SRC_TMR0_INT_Pos)
5326#define INT_IRQ9_SRC_TMR1_INT_Pos (0)
5327#define INT_IRQ9_SRC_TMR1_INT_Msk (0x1ul << INT_IRQ9_SRC_TMR1_INT_Pos)
5329#define INT_IRQ12_SRC_UART0_INT_Pos (0)
5330#define INT_IRQ12_SRC_UART0_INT_Msk (0x1ul << INT_IRQ12_SRC_UART0_INT_Pos)
5332#define INT_IRQ13_SRC_UART1_INT_Pos (0)
5333#define INT_IRQ13_SRC_UART1_INT_Msk (0x1ul << INT_IRQ13_SRC_UART1_INT_Pos)
5335#define INT_IRQ14_SRC_SPI_INT_Pos (0)
5336#define INT_IRQ14_SRC_SPI_INT_Msk (0x1ul << INT_IRQ14_SRC_SPI_INT_Pos)
5338#define INT_IRQ16_SRC_GP5_INT_Pos (0)
5339#define INT_IRQ16_SRC_GP5_INT_Msk (0x1ul << INT_IRQ16_SRC_GP5_INT_Pos)
5341#define INT_IRQ17_SRC_HIRC_TRIM_INT_Pos (0)
5342#define INT_IRQ17_SRC_HIRC_TRIM_INT_Msk (0x1ul << INT_IRQ17_SRC_HIRC_TRIM_INT_Pos)
5344#define INT_IRQ18_SRC_I2C0_INT_Pos (0)
5345#define INT_IRQ18_SRC_I2C0_INT_Msk (0x1ul << INT_IRQ18_SRC_I2C0_INT_Pos)
5347#define INT_IRQ19_SRC_I2C1_INT_Pos (0)
5348#define INT_IRQ19_SRC_I2C1_INT_Msk (0x1ul << INT_IRQ19_SRC_I2C1_INT_Pos)
5350#define INT_IRQ25_SRC_ACMP_INT_Pos (0)
5351#define INT_IRQ25_SRC_ACMP_INT_Msk (0x1ul << INT_IRQ25_SRC_ACMP_INT_Pos)
5353#define INT_IRQ28_SRC_PWRWU_INT_Pos (0)
5354#define INT_IRQ28_SRC_PWRWU_INT_Msk (0x1ul << INT_IRQ28_SRC_PWRWU_INT_Pos)
5356#define INT_IRQ29_SRC_ADC_INT_Pos (0)
5357#define INT_IRQ29_SRC_ADC_INT_Msk (0x1ul << INT_IRQ29_SRC_ADC_INT_Pos)
5359#define INT_CON_NMI_SEL_Pos (0)
5360#define INT_CON_NMI_SEL_Msk (0x1ful << INT_CON_NMI_SEL_Pos)
5362#define INT_CON_NMI_SEL_EN_Pos (8)
5363#define INT_CON_NMI_SEL_EN_Msk (0x1ul << INT_CON_NMI_SEL_EN_Pos)
5365#define INT_IRQ_MCU_IRQ_Pos (0)
5366#define INT_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_IRQ_MCU_IRQ_Pos)
6985 __I uint32_t RESERVED0[6];
7899#define PWM_CLKPSC_CLKPSC01_Pos (0)
7900#define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos)
7902#define PWM_CLKPSC_CLKPSC23_Pos (8)
7903#define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos)
7905#define PWM_CLKPSC_CLKPSC45_Pos (16)
7906#define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos)
7908#define PWM_CLKDIV_CLKDIV0_Pos (0)
7909#define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos)
7911#define PWM_CLKDIV_CLKDIV1_Pos (4)
7912#define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos)
7914#define PWM_CLKDIV_CLKDIV2_Pos (8)
7915#define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos)
7917#define PWM_CLKDIV_CLKDIV3_Pos (12)
7918#define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos)
7920#define PWM_CLKDIV_CLKDIV4_Pos (16)
7921#define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos)
7923#define PWM_CLKDIV_CLKDIV5_Pos (20)
7924#define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos)
7926#define PWM_CTL_CNTEN0_Pos (0)
7927#define PWM_CTL_CNTEN0_Msk (0x1ul << PWM_CTL_CNTEN0_Pos)
7929#define PWM_CTL_DBGTRIOFF_Pos (1)
7930#define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos)
7932#define PWM_CTL_PINV0_Pos (2)
7933#define PWM_CTL_PINV0_Msk (0x1ul << PWM_CTL_PINV0_Pos)
7935#define PWM_CTL_CNTMODE0_Pos (3)
7936#define PWM_CTL_CNTMODE0_Msk (0x1ul << PWM_CTL_CNTMODE0_Pos)
7938#define PWM_CTL_CNTEN1_Pos (4)
7939#define PWM_CTL_CNTEN1_Msk (0x1ul << PWM_CTL_CNTEN1_Pos)
7941#define PWM_CTL_HCUPDT_Pos (5)
7942#define PWM_CTL_HCUPDT_Msk (0x1ul << PWM_CTL_HCUPDT_Pos)
7944#define PWM_CTL_PINV1_Pos (6)
7945#define PWM_CTL_PINV1_Msk (0x1ul << PWM_CTL_PINV1_Pos)
7947#define PWM_CTL_CNTMODE1_Pos (7)
7948#define PWM_CTL_CNTMODE1_Msk (0x1ul << PWM_CTL_CNTMODE1_Pos)
7950#define PWM_CTL_CNTEN2_Pos (8)
7951#define PWM_CTL_CNTEN2_Msk (0x1ul << PWM_CTL_CNTEN2_Pos)
7953#define PWM_CTL_PINV2_Pos (10)
7954#define PWM_CTL_PINV2_Msk (0x1ul << PWM_CTL_PINV2_Pos)
7956#define PWM_CTL_CNTMODE2_Pos (11)
7957#define PWM_CTL_CNTMODE2_Msk (0x1ul << PWM_CTL_CNTMODE2_Pos)
7959#define PWM_CTL_CNTEN3_Pos (12)
7960#define PWM_CTL_CNTEN3_Msk (0x1ul << PWM_CTL_CNTEN3_Pos)
7962#define PWM_CTL_PINV3_Pos (14)
7963#define PWM_CTL_PINV3_Msk (0x1ul << PWM_CTL_PINV3_Pos)
7965#define PWM_CTL_CNTMODE3_Pos (15)
7966#define PWM_CTL_CNTMODE3_Msk (0x1ul << PWM_CTL_CNTMODE3_Pos)
7968#define PWM_CTL_CNTEN4_Pos (16)
7969#define PWM_CTL_CNTEN4_Msk (0x1ul << PWM_CTL_CNTEN4_Pos)
7971#define PWM_CTL_PINV4_Pos (18)
7972#define PWM_CTL_PINV4_Msk (0x1ul << PWM_CTL_PINV4_Pos)
7974#define PWM_CTL_CNTMODE4_Pos (19)
7975#define PWM_CTL_CNTMODE4_Msk (0x1ul << PWM_CTL_CNTMODE4_Pos)
7977#define PWM_CTL_CNTEN5_Pos (20)
7978#define PWM_CTL_CNTEN5_Msk (0x1ul << PWM_CTL_CNTEN5_Pos)
7980#define PWM_CTL_ASYMEN_Pos (21)
7981#define PWM_CTL_ASYMEN_Msk (0x1ul << PWM_CTL_ASYMEN_Pos)
7983#define PWM_CTL_PINV5_Pos (22)
7984#define PWM_CTL_PINV5_Msk (0x1ul << PWM_CTL_PINV5_Pos)
7986#define PWM_CTL_CNTMODE5_Pos (23)
7987#define PWM_CTL_CNTMODE5_Msk (0x1ul << PWM_CTL_CNTMODE5_Pos)
7989#define PWM_CTL_DTCNT01_Pos (24)
7990#define PWM_CTL_DTCNT01_Msk (0x1ul << PWM_CTL_DTCNT01_Pos)
7992#define PWM_CTL_DTCNT23_Pos (25)
7993#define PWM_CTL_DTCNT23_Msk (0x1ul << PWM_CTL_DTCNT23_Pos)
7995#define PWM_CTL_DTCNT45_Pos (26)
7996#define PWM_CTL_DTCNT45_Msk (0x1ul << PWM_CTL_DTCNT45_Pos)
7998#define PWM_CTL_CNTCLR_Pos (27)
7999#define PWM_CTL_CNTCLR_Msk (0x1ul << PWM_CTL_CNTCLR_Pos)
8001#define PWM_CTL_MODE_Pos (28)
8002#define PWM_CTL_MODE_Msk (0x3ul << PWM_CTL_MODE_Pos)
8004#define PWM_CTL_GROUPEN_Pos (30)
8005#define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos)
8007#define PWM_CTL_CNTTYPE_Pos (31)
8008#define PWM_CTL_CNTTYPE_Msk (0x1ul << PWM_CTL_CNTTYPE_Pos)
8010#define PWM_PERIOD0_PERIOD0_Pos (0)
8011#define PWM_PERIOD0_PERIOD0_Msk (0xfffful << PWM_PERIOD0_PERIOD0_Pos)
8013#define PWM_PERIOD0_PERIOD1_Pos (0)
8014#define PWM_PERIOD0_PERIOD1_Msk (0xfffful << PWM_PERIOD0_PERIOD1_Pos)
8016#define PWM_PERIOD0_PERIOD2_Pos (0)
8017#define PWM_PERIOD0_PERIOD2_Msk (0xfffful << PWM_PERIOD0_PERIOD2_Pos)
8019#define PWM_PERIOD0_PERIOD3_Pos (0)
8020#define PWM_PERIOD0_PERIOD3_Msk (0xfffful << PWM_PERIOD0_PERIOD3_Pos)
8022#define PWM_PERIOD0_PERIOD4_Pos (0)
8023#define PWM_PERIOD0_PERIOD4_Msk (0xfffful << PWM_PERIOD0_PERIOD4_Pos)
8025#define PWM_PERIOD0_PERIOD5_Pos (0)
8026#define PWM_PERIOD0_PERIOD5_Msk (0xfffful << PWM_PERIOD0_PERIOD5_Pos)
8028#define PWM_PERIOD1_PERIOD0_Pos (0)
8029#define PWM_PERIOD1_PERIOD0_Msk (0xfffful << PWM_PERIOD1_PERIOD0_Pos)
8031#define PWM_PERIOD1_PERIOD1_Pos (0)
8032#define PWM_PERIOD1_PERIOD1_Msk (0xfffful << PWM_PERIOD1_PERIOD1_Pos)
8034#define PWM_PERIOD1_PERIOD2_Pos (0)
8035#define PWM_PERIOD1_PERIOD2_Msk (0xfffful << PWM_PERIOD1_PERIOD2_Pos)
8037#define PWM_PERIOD1_PERIOD3_Pos (0)
8038#define PWM_PERIOD1_PERIOD3_Msk (0xfffful << PWM_PERIOD1_PERIOD3_Pos)
8040#define PWM_PERIOD1_PERIOD4_Pos (0)
8041#define PWM_PERIOD1_PERIOD4_Msk (0xfffful << PWM_PERIOD1_PERIOD4_Pos)
8043#define PWM_PERIOD1_PERIOD5_Pos (0)
8044#define PWM_PERIOD1_PERIOD5_Msk (0xfffful << PWM_PERIOD1_PERIOD5_Pos)
8046#define PWM_PERIOD2_PERIOD0_Pos (0)
8047#define PWM_PERIOD2_PERIOD0_Msk (0xfffful << PWM_PERIOD2_PERIOD0_Pos)
8049#define PWM_PERIOD2_PERIOD1_Pos (0)
8050#define PWM_PERIOD2_PERIOD1_Msk (0xfffful << PWM_PERIOD2_PERIOD1_Pos)
8052#define PWM_PERIOD2_PERIOD2_Pos (0)
8053#define PWM_PERIOD2_PERIOD2_Msk (0xfffful << PWM_PERIOD2_PERIOD2_Pos)
8055#define PWM_PERIOD2_PERIOD3_Pos (0)
8056#define PWM_PERIOD2_PERIOD3_Msk (0xfffful << PWM_PERIOD2_PERIOD3_Pos)
8058#define PWM_PERIOD2_PERIOD4_Pos (0)
8059#define PWM_PERIOD2_PERIOD4_Msk (0xfffful << PWM_PERIOD2_PERIOD4_Pos)
8061#define PWM_PERIOD2_PERIOD5_Pos (0)
8062#define PWM_PERIOD2_PERIOD5_Msk (0xfffful << PWM_PERIOD2_PERIOD5_Pos)
8064#define PWM_PERIOD3_PERIOD0_Pos (0)
8065#define PWM_PERIOD3_PERIOD0_Msk (0xfffful << PWM_PERIOD3_PERIOD0_Pos)
8067#define PWM_PERIOD3_PERIOD1_Pos (0)
8068#define PWM_PERIOD3_PERIOD1_Msk (0xfffful << PWM_PERIOD3_PERIOD1_Pos)
8070#define PWM_PERIOD3_PERIOD2_Pos (0)
8071#define PWM_PERIOD3_PERIOD2_Msk (0xfffful << PWM_PERIOD3_PERIOD2_Pos)
8073#define PWM_PERIOD3_PERIOD3_Pos (0)
8074#define PWM_PERIOD3_PERIOD3_Msk (0xfffful << PWM_PERIOD3_PERIOD3_Pos)
8076#define PWM_PERIOD3_PERIOD4_Pos (0)
8077#define PWM_PERIOD3_PERIOD4_Msk (0xfffful << PWM_PERIOD3_PERIOD4_Pos)
8079#define PWM_PERIOD3_PERIOD5_Pos (0)
8080#define PWM_PERIOD3_PERIOD5_Msk (0xfffful << PWM_PERIOD3_PERIOD5_Pos)
8082#define PWM_PERIOD4_PERIOD0_Pos (0)
8083#define PWM_PERIOD4_PERIOD0_Msk (0xfffful << PWM_PERIOD4_PERIOD0_Pos)
8085#define PWM_PERIOD4_PERIOD1_Pos (0)
8086#define PWM_PERIOD4_PERIOD1_Msk (0xfffful << PWM_PERIOD4_PERIOD1_Pos)
8088#define PWM_PERIOD4_PERIOD2_Pos (0)
8089#define PWM_PERIOD4_PERIOD2_Msk (0xfffful << PWM_PERIOD4_PERIOD2_Pos)
8091#define PWM_PERIOD4_PERIOD3_Pos (0)
8092#define PWM_PERIOD4_PERIOD3_Msk (0xfffful << PWM_PERIOD4_PERIOD3_Pos)
8094#define PWM_PERIOD4_PERIOD4_Pos (0)
8095#define PWM_PERIOD4_PERIOD4_Msk (0xfffful << PWM_PERIOD4_PERIOD4_Pos)
8097#define PWM_PERIOD4_PERIOD5_Pos (0)
8098#define PWM_PERIOD4_PERIOD5_Msk (0xfffful << PWM_PERIOD4_PERIOD5_Pos)
8100#define PWM_PERIOD5_PERIOD0_Pos (0)
8101#define PWM_PERIOD5_PERIOD0_Msk (0xfffful << PWM_PERIOD5_PERIOD0_Pos)
8103#define PWM_PERIOD5_PERIOD1_Pos (0)
8104#define PWM_PERIOD5_PERIOD1_Msk (0xfffful << PWM_PERIOD5_PERIOD1_Pos)
8106#define PWM_PERIOD5_PERIOD2_Pos (0)
8107#define PWM_PERIOD5_PERIOD2_Msk (0xfffful << PWM_PERIOD5_PERIOD2_Pos)
8109#define PWM_PERIOD5_PERIOD3_Pos (0)
8110#define PWM_PERIOD5_PERIOD3_Msk (0xfffful << PWM_PERIOD5_PERIOD3_Pos)
8112#define PWM_PERIOD5_PERIOD4_Pos (0)
8113#define PWM_PERIOD5_PERIOD4_Msk (0xfffful << PWM_PERIOD5_PERIOD4_Pos)
8115#define PWM_PERIOD5_PERIOD5_Pos (0)
8116#define PWM_PERIOD5_PERIOD5_Msk (0xfffful << PWM_PERIOD5_PERIOD5_Pos)
8118#define PWM_CMPDAT0_CMP0_Pos (0)
8119#define PWM_CMPDAT0_CMP0_Msk (0xfffful << PWM_CMPDAT0_CMP0_Pos)
8121#define PWM_CMPDAT0_CMP1_Pos (0)
8122#define PWM_CMPDAT0_CMP1_Msk (0xfffful << PWM_CMPDAT0_CMP1_Pos)
8124#define PWM_CMPDAT0_CMP2_Pos (0)
8125#define PWM_CMPDAT0_CMP2_Msk (0xfffful << PWM_CMPDAT0_CMP2_Pos)
8127#define PWM_CMPDAT0_CMP3_Pos (0)
8128#define PWM_CMPDAT0_CMP3_Msk (0xfffful << PWM_CMPDAT0_CMP3_Pos)
8130#define PWM_CMPDAT0_CMP4_Pos (0)
8131#define PWM_CMPDAT0_CMP4_Msk (0xfffful << PWM_CMPDAT0_CMP4_Pos)
8133#define PWM_CMPDAT0_CMP5_Pos (0)
8134#define PWM_CMPDAT0_CMP5_Msk (0xfffful << PWM_CMPDAT0_CMP5_Pos)
8136#define PWM_CMPDAT0_CMPD0_Pos (16)
8137#define PWM_CMPDAT0_CMPD0_Msk (0xfffful << PWM_CMPDAT0_CMPD0_Pos)
8139#define PWM_CMPDAT0_CMPD1_Pos (16)
8140#define PWM_CMPDAT0_CMPD1_Msk (0xfffful << PWM_CMPDAT0_CMPD1_Pos)
8142#define PWM_CMPDAT0_CMPD2_Pos (16)
8143#define PWM_CMPDAT0_CMPD2_Msk (0xfffful << PWM_CMPDAT0_CMPD2_Pos)
8145#define PWM_CMPDAT0_CMPD3_Pos (16)
8146#define PWM_CMPDAT0_CMPD3_Msk (0xfffful << PWM_CMPDAT0_CMPD3_Pos)
8148#define PWM_CMPDAT0_CMPD4_Pos (16)
8149#define PWM_CMPDAT0_CMPD4_Msk (0xfffful << PWM_CMPDAT0_CMPD4_Pos)
8151#define PWM_CMPDAT0_CMPD5_Pos (16)
8152#define PWM_CMPDAT0_CMPD5_Msk (0xfffful << PWM_CMPDAT0_CMPD5_Pos)
8154#define PWM_CMPDAT1_CMP0_Pos (0)
8155#define PWM_CMPDAT1_CMP0_Msk (0xfffful << PWM_CMPDAT1_CMP0_Pos)
8157#define PWM_CMPDAT1_CMP1_Pos (0)
8158#define PWM_CMPDAT1_CMP1_Msk (0xfffful << PWM_CMPDAT1_CMP1_Pos)
8160#define PWM_CMPDAT1_CMP2_Pos (0)
8161#define PWM_CMPDAT1_CMP2_Msk (0xfffful << PWM_CMPDAT1_CMP2_Pos)
8163#define PWM_CMPDAT1_CMP3_Pos (0)
8164#define PWM_CMPDAT1_CMP3_Msk (0xfffful << PWM_CMPDAT1_CMP3_Pos)
8166#define PWM_CMPDAT1_CMP4_Pos (0)
8167#define PWM_CMPDAT1_CMP4_Msk (0xfffful << PWM_CMPDAT1_CMP4_Pos)
8169#define PWM_CMPDAT1_CMP5_Pos (0)
8170#define PWM_CMPDAT1_CMP5_Msk (0xfffful << PWM_CMPDAT1_CMP5_Pos)
8172#define PWM_CMPDAT1_CMPD0_Pos (16)
8173#define PWM_CMPDAT1_CMPD0_Msk (0xfffful << PWM_CMPDAT1_CMPD0_Pos)
8175#define PWM_CMPDAT1_CMPD1_Pos (16)
8176#define PWM_CMPDAT1_CMPD1_Msk (0xfffful << PWM_CMPDAT1_CMPD1_Pos)
8178#define PWM_CMPDAT1_CMPD2_Pos (16)
8179#define PWM_CMPDAT1_CMPD2_Msk (0xfffful << PWM_CMPDAT1_CMPD2_Pos)
8181#define PWM_CMPDAT1_CMPD3_Pos (16)
8182#define PWM_CMPDAT1_CMPD3_Msk (0xfffful << PWM_CMPDAT1_CMPD3_Pos)
8184#define PWM_CMPDAT1_CMPD4_Pos (16)
8185#define PWM_CMPDAT1_CMPD4_Msk (0xfffful << PWM_CMPDAT1_CMPD4_Pos)
8187#define PWM_CMPDAT1_CMPD5_Pos (16)
8188#define PWM_CMPDAT1_CMPD5_Msk (0xfffful << PWM_CMPDAT1_CMPD5_Pos)
8190#define PWM_CMPDAT2_CMP0_Pos (0)
8191#define PWM_CMPDAT2_CMP0_Msk (0xfffful << PWM_CMPDAT2_CMP0_Pos)
8193#define PWM_CMPDAT2_CMP1_Pos (0)
8194#define PWM_CMPDAT2_CMP1_Msk (0xfffful << PWM_CMPDAT2_CMP1_Pos)
8196#define PWM_CMPDAT2_CMP2_Pos (0)
8197#define PWM_CMPDAT2_CMP2_Msk (0xfffful << PWM_CMPDAT2_CMP2_Pos)
8199#define PWM_CMPDAT2_CMP3_Pos (0)
8200#define PWM_CMPDAT2_CMP3_Msk (0xfffful << PWM_CMPDAT2_CMP3_Pos)
8202#define PWM_CMPDAT2_CMP4_Pos (0)
8203#define PWM_CMPDAT2_CMP4_Msk (0xfffful << PWM_CMPDAT2_CMP4_Pos)
8205#define PWM_CMPDAT2_CMP5_Pos (0)
8206#define PWM_CMPDAT2_CMP5_Msk (0xfffful << PWM_CMPDAT2_CMP5_Pos)
8208#define PWM_CMPDAT2_CMPD0_Pos (16)
8209#define PWM_CMPDAT2_CMPD0_Msk (0xfffful << PWM_CMPDAT2_CMPD0_Pos)
8211#define PWM_CMPDAT2_CMPD1_Pos (16)
8212#define PWM_CMPDAT2_CMPD1_Msk (0xfffful << PWM_CMPDAT2_CMPD1_Pos)
8214#define PWM_CMPDAT2_CMPD2_Pos (16)
8215#define PWM_CMPDAT2_CMPD2_Msk (0xfffful << PWM_CMPDAT2_CMPD2_Pos)
8217#define PWM_CMPDAT2_CMPD3_Pos (16)
8218#define PWM_CMPDAT2_CMPD3_Msk (0xfffful << PWM_CMPDAT2_CMPD3_Pos)
8220#define PWM_CMPDAT2_CMPD4_Pos (16)
8221#define PWM_CMPDAT2_CMPD4_Msk (0xfffful << PWM_CMPDAT2_CMPD4_Pos)
8223#define PWM_CMPDAT2_CMPD5_Pos (16)
8224#define PWM_CMPDAT2_CMPD5_Msk (0xfffful << PWM_CMPDAT2_CMPD5_Pos)
8226#define PWM_CMPDAT3_CMP0_Pos (0)
8227#define PWM_CMPDAT3_CMP0_Msk (0xfffful << PWM_CMPDAT3_CMP0_Pos)
8229#define PWM_CMPDAT3_CMP1_Pos (0)
8230#define PWM_CMPDAT3_CMP1_Msk (0xfffful << PWM_CMPDAT3_CMP1_Pos)
8232#define PWM_CMPDAT3_CMP2_Pos (0)
8233#define PWM_CMPDAT3_CMP2_Msk (0xfffful << PWM_CMPDAT3_CMP2_Pos)
8235#define PWM_CMPDAT3_CMP3_Pos (0)
8236#define PWM_CMPDAT3_CMP3_Msk (0xfffful << PWM_CMPDAT3_CMP3_Pos)
8238#define PWM_CMPDAT3_CMP4_Pos (0)
8239#define PWM_CMPDAT3_CMP4_Msk (0xfffful << PWM_CMPDAT3_CMP4_Pos)
8241#define PWM_CMPDAT3_CMP5_Pos (0)
8242#define PWM_CMPDAT3_CMP5_Msk (0xfffful << PWM_CMPDAT3_CMP5_Pos)
8244#define PWM_CMPDAT3_CMPD0_Pos (16)
8245#define PWM_CMPDAT3_CMPD0_Msk (0xfffful << PWM_CMPDAT3_CMPD0_Pos)
8247#define PWM_CMPDAT3_CMPD1_Pos (16)
8248#define PWM_CMPDAT3_CMPD1_Msk (0xfffful << PWM_CMPDAT3_CMPD1_Pos)
8250#define PWM_CMPDAT3_CMPD2_Pos (16)
8251#define PWM_CMPDAT3_CMPD2_Msk (0xfffful << PWM_CMPDAT3_CMPD2_Pos)
8253#define PWM_CMPDAT3_CMPD3_Pos (16)
8254#define PWM_CMPDAT3_CMPD3_Msk (0xfffful << PWM_CMPDAT3_CMPD3_Pos)
8256#define PWM_CMPDAT3_CMPD4_Pos (16)
8257#define PWM_CMPDAT3_CMPD4_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos)
8259#define PWM_CMPDAT3_CMPD5_Pos (16)
8260#define PWM_CMPDAT3_CMPD5_Msk (0xfffful << PWM_CMPDAT3_CMPD5_Pos)
8262#define PWM_CMPDAT4_CMP0_Pos (0)
8263#define PWM_CMPDAT4_CMP0_Msk (0xfffful << PWM_CMPDAT4_CMP0_Pos)
8265#define PWM_CMPDAT4_CMP1_Pos (0)
8266#define PWM_CMPDAT4_CMP1_Msk (0xfffful << PWM_CMPDAT4_CMP1_Pos)
8268#define PWM_CMPDAT4_CMP2_Pos (0)
8269#define PWM_CMPDAT4_CMP2_Msk (0xfffful << PWM_CMPDAT4_CMP2_Pos)
8271#define PWM_CMPDAT4_CMP3_Pos (0)
8272#define PWM_CMPDAT4_CMP3_Msk (0xfffful << PWM_CMPDAT4_CMP3_Pos)
8274#define PWM_CMPDAT4_CMP4_Pos (0)
8275#define PWM_CMPDAT4_CMP4_Msk (0xfffful << PWM_CMPDAT4_CMP4_Pos)
8277#define PWM_CMPDAT4_CMP5_Pos (0)
8278#define PWM_CMPDAT4_CMP5_Msk (0xfffful << PWM_CMPDAT4_CMP5_Pos)
8280#define PWM_CMPDAT4_CMPD0_Pos (16)
8281#define PWM_CMPDAT4_CMPD0_Msk (0xfffful << PWM_CMPDAT4_CMPD0_Pos)
8283#define PWM_CMPDAT4_CMPD1_Pos (16)
8284#define PWM_CMPDAT4_CMPD1_Msk (0xfffful << PWM_CMPDAT4_CMPD1_Pos)
8286#define PWM_CMPDAT4_CMPD2_Pos (16)
8287#define PWM_CMPDAT4_CMPD2_Msk (0xfffful << PWM_CMPDAT4_CMPD2_Pos)
8289#define PWM_CMPDAT4_CMPD3_Pos (16)
8290#define PWM_CMPDAT4_CMPD3_Msk (0xfffful << PWM_CMPDAT4_CMPD3_Pos)
8292#define PWM_CMPDAT4_CMPD4_Pos (16)
8293#define PWM_CMPDAT4_CMPD4_Msk (0xfffful << PWM_CMPDAT4_CMPD4_Pos)
8295#define PWM_CMPDAT4_CMPD5_Pos (16)
8296#define PWM_CMPDAT4_CMPD5_Msk (0xfffful << PWM_CMPDAT4_CMPD5_Pos)
8298#define PWM_CMPDAT5_CMP0_Pos (0)
8299#define PWM_CMPDAT5_CMP0_Msk (0xfffful << PWM_CMPDAT5_CMP0_Pos)
8301#define PWM_CMPDAT5_CMP1_Pos (0)
8302#define PWM_CMPDAT5_CMP1_Msk (0xfffful << PWM_CMPDAT5_CMP1_Pos)
8304#define PWM_CMPDAT5_CMP2_Pos (0)
8305#define PWM_CMPDAT5_CMP2_Msk (0xfffful << PWM_CMPDAT5_CMP2_Pos)
8307#define PWM_CMPDAT5_CMP3_Pos (0)
8308#define PWM_CMPDAT5_CMP3_Msk (0xfffful << PWM_CMPDAT5_CMP3_Pos)
8310#define PWM_CMPDAT5_CMP4_Pos (0)
8311#define PWM_CMPDAT5_CMP4_Msk (0xfffful << PWM_CMPDAT5_CMP4_Pos)
8313#define PWM_CMPDAT5_CMP5_Pos (0)
8314#define PWM_CMPDAT5_CMP5_Msk (0xfffful << PWM_CMPDAT5_CMP5_Pos)
8316#define PWM_CMPDAT5_CMPD0_Pos (16)
8317#define PWM_CMPDAT5_CMPD0_Msk (0xfffful << PWM_CMPDAT5_CMPD0_Pos)
8319#define PWM_CMPDAT5_CMPD1_Pos (16)
8320#define PWM_CMPDAT5_CMPD1_Msk (0xfffful << PWM_CMPDAT5_CMPD1_Pos)
8322#define PWM_CMPDAT5_CMPD2_Pos (16)
8323#define PWM_CMPDAT5_CMPD2_Msk (0xfffful << PWM_CMPDAT5_CMPD2_Pos)
8325#define PWM_CMPDAT5_CMPD3_Pos (16)
8326#define PWM_CMPDAT5_CMPD3_Msk (0xfffful << PWM_CMPDAT5_CMPD3_Pos)
8328#define PWM_CMPDAT5_CMPD4_Pos (16)
8329#define PWM_CMPDAT5_CMPD4_Msk (0xfffful << PWM_CMPDAT5_CMPD4_Pos)
8331#define PWM_CMPDAT5_CMPD5_Pos (16)
8332#define PWM_CMPDAT5_CMPD5_Msk (0xfffful << PWM_CMPDAT5_CMPD5_Pos)
8334#define PWM_INTEN_ZIEN0_Pos (0)
8335#define PWM_INTEN_ZIEN0_Msk (0x1ul << PWM_INTEN_ZIEN0_Pos)
8337#define PWM_INTEN_ZIEN1_Pos (1)
8338#define PWM_INTEN_ZIEN1_Msk (0x1ul << PWM_INTEN_ZIEN1_Pos)
8340#define PWM_INTEN_ZIEN2_Pos (2)
8341#define PWM_INTEN_ZIEN2_Msk (0x1ul << PWM_INTEN_ZIEN2_Pos)
8343#define PWM_INTEN_ZIEN3_Pos (3)
8344#define PWM_INTEN_ZIEN3_Msk (0x1ul << PWM_INTEN_ZIEN3_Pos)
8346#define PWM_INTEN_ZIEN4_Pos (4)
8347#define PWM_INTEN_ZIEN4_Msk (0x1ul << PWM_INTEN_ZIEN4_Pos)
8349#define PWM_INTEN_ZIEN5_Pos (5)
8350#define PWM_INTEN_ZIEN5_Msk (0x1ul << PWM_INTEN_ZIEN5_Pos)
8352#define PWM_INTEN_CMPDIEN0_Pos (8)
8353#define PWM_INTEN_CMPDIEN0_Msk (0x1ul << PWM_INTEN_CMPDIEN0_Pos)
8355#define PWM_INTEN_CMPDIEN1_Pos (9)
8356#define PWM_INTEN_CMPDIEN1_Msk (0x1ul << PWM_INTEN_CMPDIEN1_Pos)
8358#define PWM_INTEN_CMPDIEN2_Pos (10)
8359#define PWM_INTEN_CMPDIEN2_Msk (0x1ul << PWM_INTEN_CMPDIEN2_Pos)
8361#define PWM_INTEN_CMPDIEN3_Pos (11)
8362#define PWM_INTEN_CMPDIEN3_Msk (0x1ul << PWM_INTEN_CMPDIEN3_Pos)
8364#define PWM_INTEN_CMPDIEN4_Pos (12)
8365#define PWM_INTEN_CMPDIEN4_Msk (0x1ul << PWM_INTEN_CMPDIEN4_Pos)
8367#define PWM_INTEN_CMPDIEN5_Pos (13)
8368#define PWM_INTEN_CMPDIEN5_Msk (0x1ul << PWM_INTEN_CMPDIEN5_Pos)
8370#define PWM_INTEN_BRKIEN_Pos (16)
8371#define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos)
8373#define PWM_INTEN_PINTTYPE_Pos (17)
8374#define PWM_INTEN_PINTTYPE_Msk (0x1ul << PWM_INTEN_PINTTYPE_Pos)
8376#define PWM_INTEN_PIEN0_Pos (18)
8377#define PWM_INTEN_PIEN0_Msk (0x1ul << PWM_INTEN_PIEN0_Pos)
8379#define PWM_INTEN_PIEN1_Pos (19)
8380#define PWM_INTEN_PIEN1_Msk (0x1ul << PWM_INTEN_PIEN1_Pos)
8382#define PWM_INTEN_PIEN2_Pos (20)
8383#define PWM_INTEN_PIEN2_Msk (0x1ul << PWM_INTEN_PIEN2_Pos)
8385#define PWM_INTEN_PIEN3_Pos (21)
8386#define PWM_INTEN_PIEN3_Msk (0x1ul << PWM_INTEN_PIEN3_Pos)
8388#define PWM_INTEN_PIEN4_Pos (22)
8389#define PWM_INTEN_PIEN4_Msk (0x1ul << PWM_INTEN_PIEN4_Pos)
8391#define PWM_INTEN_PIEN5_Pos (23)
8392#define PWM_INTEN_PIEN5_Msk (0x1ul << PWM_INTEN_PIEN5_Pos)
8394#define PWM_INTEN_CMPUIEN0_Pos (24)
8395#define PWM_INTEN_CMPUIEN0_Msk (0x1ul << PWM_INTEN_CMPUIEN0_Pos)
8397#define PWM_INTEN_CMPUIEN1_Pos (25)
8398#define PWM_INTEN_CMPUIEN1_Msk (0x1ul << PWM_INTEN_CMPUIEN1_Pos)
8400#define PWM_INTEN_CMPUIEN2_Pos (26)
8401#define PWM_INTEN_CMPUIEN2_Msk (0x1ul << PWM_INTEN_CMPUIEN2_Pos)
8403#define PWM_INTEN_CMPUIEN3_Pos (27)
8404#define PWM_INTEN_CMPUIEN3_Msk (0x1ul << PWM_INTEN_CMPUIEN3_Pos)
8406#define PWM_INTEN_CMPUIEN4_Pos (28)
8407#define PWM_INTEN_CMPUIEN4_Msk (0x1ul << PWM_INTEN_CMPUIEN4_Pos)
8409#define PWM_INTEN_CMPUIEN5_Pos (29)
8410#define PWM_INTEN_CMPUIEN5_Msk (0x1ul << PWM_INTEN_CMPUIEN5_Pos)
8412#define PWM_INTSTS_ZIF0_Pos (0)
8413#define PWM_INTSTS_ZIF0_Msk (0x1ul << PWM_INTSTS_ZIF0_Pos)
8415#define PWM_INTSTS_ZIF1_Pos (1)
8416#define PWM_INTSTS_ZIF1_Msk (0x1ul << PWM_INTSTS_ZIF1_Pos)
8418#define PWM_INTSTS_ZIF2_Pos (2)
8419#define PWM_INTSTS_ZIF2_Msk (0x1ul << PWM_INTSTS_ZIF2_Pos)
8421#define PWM_INTSTS_ZIF3_Pos (3)
8422#define PWM_INTSTS_ZIF3_Msk (0x1ul << PWM_INTSTS_ZIF3_Pos)
8424#define PWM_INTSTS_ZIF4_Pos (4)
8425#define PWM_INTSTS_ZIF4_Msk (0x1ul << PWM_INTSTS_ZIF4_Pos)
8427#define PWM_INTSTS_ZIF5_Pos (5)
8428#define PWM_INTSTS_ZIF5_Msk (0x1ul << PWM_INTSTS_ZIF5_Pos)
8430#define PWM_INTSTS_CMPDIF0_Pos (8)
8431#define PWM_INTSTS_CMPDIF0_Msk (0x1ul << PWM_INTSTS_CMPDIF0_Pos)
8433#define PWM_INTSTS_CMPDIF1_Pos (9)
8434#define PWM_INTSTS_CMPDIF1_Msk (0x1ul << PWM_INTSTS_CMPDIF1_Pos)
8436#define PWM_INTSTS_CMPDIF2_Pos (10)
8437#define PWM_INTSTS_CMPDIF2_Msk (0x1ul << PWM_INTSTS_CMPDIF2_Pos)
8439#define PWM_INTSTS_CMPDIF3_Pos (11)
8440#define PWM_INTSTS_CMPDIF3_Msk (0x1ul << PWM_INTSTS_CMPDIF3_Pos)
8442#define PWM_INTSTS_CMPDIF4_Pos (12)
8443#define PWM_INTSTS_CMPDIF4_Msk (0x1ul << PWM_INTSTS_CMPDIF4_Pos)
8445#define PWM_INTSTS_CMPDIF5_Pos (13)
8446#define PWM_INTSTS_CMPDIF5_Msk (0x1ul << PWM_INTSTS_CMPDIF5_Pos)
8448#define PWM_INTSTS_BRKIF0_Pos (16)
8449#define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos)
8451#define PWM_INTSTS_BRKIF1_Pos (17)
8452#define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos)
8454#define PWM_INTSTS_PIF0_Pos (18)
8455#define PWM_INTSTS_PIF0_Msk (0x1ul << PWM_INTSTS_PIF0_Pos)
8457#define PWM_INTSTS_PIF1_Pos (19)
8458#define PWM_INTSTS_PIF1_Msk (0x1ul << PWM_INTSTS_PIF1_Pos)
8460#define PWM_INTSTS_PIF2_Pos (20)
8461#define PWM_INTSTS_PIF2_Msk (0x1ul << PWM_INTSTS_PIF2_Pos)
8463#define PWM_INTSTS_PIF3_Pos (21)
8464#define PWM_INTSTS_PIF3_Msk (0x1ul << PWM_INTSTS_PIF3_Pos)
8466#define PWM_INTSTS_PIF4_Pos (22)
8467#define PWM_INTSTS_PIF4_Msk (0x1ul << PWM_INTSTS_PIF4_Pos)
8469#define PWM_INTSTS_PIF5_Pos (23)
8470#define PWM_INTSTS_PIF5_Msk (0x1ul << PWM_INTSTS_PIF5_Pos)
8472#define PWM_INTSTS_CMPUIF0_Pos (24)
8473#define PWM_INTSTS_CMPUIF0_Msk (0x1ul << PWM_INTSTS_CMPUIF0_Pos)
8475#define PWM_INTSTS_CMPUIF1_Pos (25)
8476#define PWM_INTSTS_CMPUIF1_Msk (0x1ul << PWM_INTSTS_CMPUIF1_Pos)
8478#define PWM_INTSTS_CMPUIF2_Pos (26)
8479#define PWM_INTSTS_CMPUIF2_Msk (0x1ul << PWM_INTSTS_CMPUIF2_Pos)
8481#define PWM_INTSTS_CMPUIF3_Pos (27)
8482#define PWM_INTSTS_CMPUIF3_Msk (0x1ul << PWM_INTSTS_CMPUIF3_Pos)
8484#define PWM_INTSTS_CMPUIF4_Pos (28)
8485#define PWM_INTSTS_CMPUIF4_Msk (0x1ul << PWM_INTSTS_CMPUIF4_Pos)
8487#define PWM_INTSTS_CMPUIF5_Pos (29)
8488#define PWM_INTSTS_CMPUIF5_Msk (0x1ul << PWM_INTSTS_CMPUIF5_Pos)
8490#define PWM_POEN_POEN0_Pos (0)
8491#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos)
8493#define PWM_POEN_POEN1_Pos (1)
8494#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos)
8496#define PWM_POEN_POEN2_Pos (2)
8497#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos)
8499#define PWM_POEN_POEN3_Pos (3)
8500#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos)
8502#define PWM_POEN_POEN4_Pos (4)
8503#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos)
8505#define PWM_POEN_POEN5_Pos (5)
8506#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos)
8508#define PWM_BRKCTL_BRK0EN_Pos (0)
8509#define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos)
8511#define PWM_BRKCTL_BRK1EN_Pos (1)
8512#define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos)
8514#define PWM_BRKCTL_BRK0SEL_Pos (2)
8515#define PWM_BRKCTL_BRK0SEL_Msk (0x1ul << PWM_BRKCTL_BRK0SEL_Pos)
8517#define PWM_BRKCTL_BRK1SEL_Pos (3)
8518#define PWM_BRKCTL_BRK1SEL_Msk (0x1ul << PWM_BRKCTL_BRK1SEL_Pos)
8520#define PWM_BRKCTL_BRKSTS_Pos (7)
8521#define PWM_BRKCTL_BRKSTS_Msk (0x1ul << PWM_BRKCTL_BRKSTS_Pos)
8523#define PWM_BRKCTL_BRKACT_Pos (8)
8524#define PWM_BRKCTL_BRKACT_Msk (0x1ul << PWM_BRKCTL_BRKACT_Pos)
8526#define PWM_BRKCTL_SWBRK_Pos (9)
8527#define PWM_BRKCTL_SWBRK_Msk (0x1ul << PWM_BRKCTL_SWBRK_Pos)
8529#define PWM_BRKCTL_BKOD0_Pos (24)
8530#define PWM_BRKCTL_BKOD0_Msk (0x1ul << PWM_BRKCTL_BKOD0_Pos)
8532#define PWM_BRKCTL_BKOD1_Pos (25)
8533#define PWM_BRKCTL_BKOD1_Msk (0x1ul << PWM_BRKCTL_BKOD1_Pos)
8535#define PWM_BRKCTL_BKOD2_Pos (26)
8536#define PWM_BRKCTL_BKOD2_Msk (0x1ul << PWM_BRKCTL_BKOD2_Pos)
8538#define PWM_BRKCTL_BKOD3_Pos (27)
8539#define PWM_BRKCTL_BKOD3_Msk (0x1ul << PWM_BRKCTL_BKOD3_Pos)
8541#define PWM_BRKCTL_BKOD4_Pos (28)
8542#define PWM_BRKCTL_BKOD4_Msk (0x1ul << PWM_BRKCTL_BKOD4_Pos)
8544#define PWM_BRKCTL_BKOD5_Pos (29)
8545#define PWM_BRKCTL_BKOD5_Msk (0x1ul << PWM_BRKCTL_BKOD5_Pos)
8547#define PWM_BRKCTL_D6BKOD_Pos (30)
8548#define PWM_BRKCTL_D6BKOD_Msk (0x1ul << PWM_BRKCTL_D6BKOD_Pos)
8550#define PWM_BRKCTL_D7BKOD_Pos (31)
8551#define PWM_BRKCTL_D7BKOD_Msk (0x1ul << PWM_BRKCTL_D7BKOD_Pos)
8553#define PWM_DTCTL_DTI01_Pos (0)
8554#define PWM_DTCTL_DTI01_Msk (0xfful << PWM_DTCTL_DTI01_Pos)
8556#define PWM_DTCTL_DTI23_Pos (8)
8557#define PWM_DTCTL_DTI23_Msk (0xfful << PWM_DTCTL_DTI23_Pos)
8559#define PWM_DTCTL_DTI45_Pos (16)
8560#define PWM_DTCTL_DTI45_Msk (0xfful << PWM_DTCTL_DTI45_Pos)
8562#define PWM_ADCTCTL0_CUTRGEN0_Pos (0)
8563#define PWM_ADCTCTL0_CUTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN0_Pos)
8565#define PWM_ADCTCTL0_CPTRGEN0_Pos (1)
8566#define PWM_ADCTCTL0_CPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN0_Pos)
8568#define PWM_ADCTCTL0_CDTRGEN0_Pos (2)
8569#define PWM_ADCTCTL0_CDTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN0_Pos)
8571#define PWM_ADCTCTL0_ZPTRGEN0_Pos (3)
8572#define PWM_ADCTCTL0_ZPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN0_Pos)
8574#define PWM_ADCTCTL0_CUTRGEN1_Pos (8)
8575#define PWM_ADCTCTL0_CUTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN1_Pos)
8577#define PWM_ADCTCTL0_CPTRGEN1_Pos (9)
8578#define PWM_ADCTCTL0_CPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN1_Pos)
8580#define PWM_ADCTCTL0_CDTRGEN1_Pos (10)
8581#define PWM_ADCTCTL0_CDTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN1_Pos)
8583#define PWM_ADCTCTL0_ZPTRGEN1_Pos (11)
8584#define PWM_ADCTCTL0_ZPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN1_Pos)
8586#define PWM_ADCTCTL0_CUTRGEN2_Pos (16)
8587#define PWM_ADCTCTL0_CUTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN2_Pos)
8589#define PWM_ADCTCTL0_CPTRGEN2_Pos (17)
8590#define PWM_ADCTCTL0_CPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN2_Pos)
8592#define PWM_ADCTCTL0_CDTRGEN2_Pos (18)
8593#define PWM_ADCTCTL0_CDTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN2_Pos)
8595#define PWM_ADCTCTL0_ZPTRGEN2_Pos (19)
8596#define PWM_ADCTCTL0_ZPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN2_Pos)
8598#define PWM_ADCTCTL0_CUTRGEN3_Pos (24)
8599#define PWM_ADCTCTL0_CUTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN3_Pos)
8601#define PWM_ADCTCTL0_CPTRGEN3_Pos (25)
8602#define PWM_ADCTCTL0_CPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN3_Pos)
8604#define PWM_ADCTCTL0_CDTRGEN3_Pos (26)
8605#define PWM_ADCTCTL0_CDTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN3_Pos)
8607#define PWM_ADCTCTL0_ZPTRGEN3_Pos (27)
8608#define PWM_ADCTCTL0_ZPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN3_Pos)
8610#define PWM_ADCTCTL1_CUTRGEN4_Pos (0)
8611#define PWM_ADCTCTL1_CUTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN4_Pos)
8613#define PWM_ADCTCTL1_CPTRGEN4_Pos (1)
8614#define PWM_ADCTCTL1_CPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN4_Pos)
8616#define PWM_ADCTCTL1_CDTRGEN4_Pos (2)
8617#define PWM_ADCTCTL1_CDTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN4_Pos)
8619#define PWM_ADCTCTL1_ZPTRGEN4_Pos (3)
8620#define PWM_ADCTCTL1_ZPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN4_Pos)
8622#define PWM_ADCTCTL1_CUTRGEN5_Pos (8)
8623#define PWM_ADCTCTL1_CUTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN5_Pos)
8625#define PWM_ADCTCTL1_CPTRGEN5_Pos (9)
8626#define PWM_ADCTCTL1_CPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN5_Pos)
8628#define PWM_ADCTCTL1_CDTRGEN5_Pos (10)
8629#define PWM_ADCTCTL1_CDTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN5_Pos)
8631#define PWM_ADCTCTL1_ZPTRGEN5_Pos (11)
8632#define PWM_ADCTCTL1_ZPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN5_Pos)
8634#define PWM_ADCTSTS0_CUTRGF0_Pos (0)
8635#define PWM_ADCTSTS0_CUTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF0_Pos)
8637#define PWM_ADCTSTS0_CPTRGF0_Pos (1)
8638#define PWM_ADCTSTS0_CPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF0_Pos)
8640#define PWM_ADCTSTS0_CDTRGF0_Pos (2)
8641#define PWM_ADCTSTS0_CDTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF0_Pos)
8643#define PWM_ADCTSTS0_ZPTRGF0_Pos (3)
8644#define PWM_ADCTSTS0_ZPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF0_Pos)
8646#define PWM_ADCTSTS0_CUTRGF1_Pos (8)
8647#define PWM_ADCTSTS0_CUTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF1_Pos)
8649#define PWM_ADCTSTS0_CPTRGF1_Pos (9)
8650#define PWM_ADCTSTS0_CPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF1_Pos)
8652#define PWM_ADCTSTS0_CDTRGF1_Pos (10)
8653#define PWM_ADCTSTS0_CDTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF1_Pos)
8655#define PWM_ADCTSTS0_ZPTRGF1_Pos (11)
8656#define PWM_ADCTSTS0_ZPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF1_Pos)
8658#define PWM_ADCTSTS0_CUTRGF2_Pos (16)
8659#define PWM_ADCTSTS0_CUTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF2_Pos)
8661#define PWM_ADCTSTS0_CPTRGF2_Pos (17)
8662#define PWM_ADCTSTS0_CPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF2_Pos)
8664#define PWM_ADCTSTS0_CDTRGF2_Pos (18)
8665#define PWM_ADCTSTS0_CDTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF2_Pos)
8667#define PWM_ADCTSTS0_ZPTRGF2_Pos (19)
8668#define PWM_ADCTSTS0_ZPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF2_Pos)
8670#define PWM_ADCTSTS0_CUTRGF3_Pos (24)
8671#define PWM_ADCTSTS0_CUTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF3_Pos)
8673#define PWM_ADCTSTS0_CPTRGF3_Pos (25)
8674#define PWM_ADCTSTS0_CPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF3_Pos)
8676#define PWM_ADCTSTS0_CDTRGF3_Pos (26)
8677#define PWM_ADCTSTS0_CDTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF3_Pos)
8679#define PWM_ADCTSTS0_ZPTRGF3_Pos (27)
8680#define PWM_ADCTSTS0_ZPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF3_Pos)
8682#define PWM_ADCTSTS1_CUTRGF4_Pos (0)
8683#define PWM_ADCTSTS1_CUTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF4_Pos)
8685#define PWM_ADCTSTS1_CPTRGF4_Pos (1)
8686#define PWM_ADCTSTS1_CPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF4_Pos)
8688#define PWM_ADCTSTS1_CDTRGF4_Pos (2)
8689#define PWM_ADCTSTS1_CDTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF4_Pos)
8691#define PWM_ADCTSTS1_ZPTRGF4_Pos (3)
8692#define PWM_ADCTSTS1_ZPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF4_Pos)
8694#define PWM_ADCTSTS1_CUTRGF5_Pos (8)
8695#define PWM_ADCTSTS1_CUTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF5_Pos)
8697#define PWM_ADCTSTS1_CPTRGF5_Pos (9)
8698#define PWM_ADCTSTS1_CPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF5_Pos)
8700#define PWM_ADCTSTS1_CDTRGF5_Pos (10)
8701#define PWM_ADCTSTS1_CDTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF5_Pos)
8703#define PWM_ADCTSTS1_ZPTRGF5_Pos (11)
8704#define PWM_ADCTSTS1_ZPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF5_Pos)
8706#define PWM_PHCHG_MSKDAT0_Pos (0)
8707#define PWM_PHCHG_MSKDAT0_Msk (0x1ul << PWM_PHCHG_MSKDAT0_Pos)
8709#define PWM_PHCHG_MSKDAT1_Pos (1)
8710#define PWM_PHCHG_MSKDAT1_Msk (0x1ul << PWM_PHCHG_MSKDAT1_Pos)
8712#define PWM_PHCHG_MSKDAT2_Pos (2)
8713#define PWM_PHCHG_MSKDAT2_Msk (0x1ul << PWM_PHCHG_MSKDAT2_Pos)
8715#define PWM_PHCHG_MSKDAT3_Pos (3)
8716#define PWM_PHCHG_MSKDAT3_Msk (0x1ul << PWM_PHCHG_MSKDAT3_Pos)
8718#define PWM_PHCHG_MSKDAT4_Pos (4)
8719#define PWM_PHCHG_MSKDAT4_Msk (0x1ul << PWM_PHCHG_MSKDAT4_Pos)
8721#define PWM_PHCHG_MSKDAT5_Pos (5)
8722#define PWM_PHCHG_MSKDAT5_Msk (0x1ul << PWM_PHCHG_MSKDAT5_Pos)
8724#define PWM_PHCHG_MSKDAT6_Pos (6)
8725#define PWM_PHCHG_MSKDAT6_Msk (0x1ul << PWM_PHCHG_MSKDAT6_Pos)
8727#define PWM_PHCHG_MSKDAT7_Pos (7)
8728#define PWM_PHCHG_MSKDAT7_Msk (0x1ul << PWM_PHCHG_MSKDAT7_Pos)
8730#define PWM_PHCHG_MSKEN0_Pos (8)
8731#define PWM_PHCHG_MSKEN0_Msk (0x1ul << PWM_PHCHG_MSKEN0_Pos)
8733#define PWM_PHCHG_MSKEN1_Pos (9)
8734#define PWM_PHCHG_MSKEN1_Msk (0x1ul << PWM_PHCHG_MSKEN1_Pos)
8736#define PWM_PHCHG_MSKEN2_Pos (10)
8737#define PWM_PHCHG_MSKEN2_Msk (0x1ul << PWM_PHCHG_MSKEN2_Pos)
8739#define PWM_PHCHG_MSKEN3_Pos (11)
8740#define PWM_PHCHG_MSKEN3_Msk (0x1ul << PWM_PHCHG_MSKEN3_Pos)
8742#define PWM_PHCHG_MSKEN4_Pos (12)
8743#define PWM_PHCHG_MSKEN4_Msk (0x1ul << PWM_PHCHG_MSKEN4_Pos)
8745#define PWM_PHCHG_MSKEN5_Pos (13)
8746#define PWM_PHCHG_MSKEN5_Msk (0x1ul << PWM_PHCHG_MSKEN5_Pos)
8748#define PWM_PHCHG_AUTOCLR0_Pos (14)
8749#define PWM_PHCHG_AUTOCLR0_Msk (0x1ul << PWM_PHCHG_AUTOCLR0_Pos)
8751#define PWM_PHCHG_AUTOCLR1_Pos (15)
8752#define PWM_PHCHG_AUTOCLR1_Msk (0x1ul << PWM_PHCHG_AUTOCLR1_Pos)
8754#define PWM_PHCHG_AOFFEN01_Pos (16)
8755#define PWM_PHCHG_AOFFEN01_Msk (0x1ul << PWM_PHCHG_AOFFEN01_Pos)
8757#define PWM_PHCHG_AOFFEN11_Pos (17)
8758#define PWM_PHCHG_AOFFEN11_Msk (0x1ul << PWM_PHCHG_AOFFEN11_Pos)
8760#define PWM_PHCHG_AOFFEN21_Pos (18)
8761#define PWM_PHCHG_AOFFEN21_Msk (0x1ul << PWM_PHCHG_AOFFEN21_Pos)
8763#define PWM_PHCHG_AOFFEN31_Pos (19)
8764#define PWM_PHCHG_AOFFEN31_Msk (0x1ul << PWM_PHCHG_AOFFEN31_Pos)
8766#define PWM_PHCHG_A1POSSEL_Pos (20)
8767#define PWM_PHCHG_A1POSSEL_Msk (0x3ul << PWM_PHCHG_A1POSSEL_Pos)
8769#define PWM_PHCHG_TMR1TEN_Pos (22)
8770#define PWM_PHCHG_TMR1TEN_Msk (0x1ul << PWM_PHCHG_TMR1TEN_Pos)
8772#define PWM_PHCHG_ACMP1TEN_Pos (23)
8773#define PWM_PHCHG_ACMP1TEN_Msk (0x1ul << PWM_PHCHG_ACMP1TEN_Pos)
8775#define PWM_PHCHG_AOFFEN00_Pos (24)
8776#define PWM_PHCHG_AOFFEN00_Msk (0x1ul << PWM_PHCHG_AOFFEN00_Pos)
8778#define PWM_PHCHG_AOFFEN10_Pos (25)
8779#define PWM_PHCHG_AOFFEN10_Msk (0x1ul << PWM_PHCHG_AOFFEN10_Pos)
8781#define PWM_PHCHG_AOFFEN20_Pos (26)
8782#define PWM_PHCHG_AOFFEN20_Msk (0x1ul << PWM_PHCHG_AOFFEN20_Pos)
8784#define PWM_PHCHG_AOFFEN30_Pos (27)
8785#define PWM_PHCHG_AOFFEN30_Msk (0x1ul << PWM_PHCHG_AOFFEN30_Pos)
8787#define PWM_PHCHG_A0POSSEL_Pos (28)
8788#define PWM_PHCHG_A0POSSEL_Msk (0x3ul << PWM_PHCHG_A0POSSEL_Pos)
8790#define PWM_PHCHG_TMR0TEN_Pos (30)
8791#define PWM_PHCHG_TMR0TEN_Msk (0x1ul << PWM_PHCHG_TMR0TEN_Pos)
8793#define PWM_PHCHG_ACMP0TEN_Pos (31)
8794#define PWM_PHCHG_ACMP0TEN_Msk (0x1ul << PWM_PHCHG_ACMP0TEN_Pos)
8796#define PWM_PHCHGNXT_MSKDAT0_Pos (0)
8797#define PWM_PHCHGNXT_MSKDAT0_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT0_Pos)
8799#define PWM_PHCHGNXT_MSKDAT1_Pos (1)
8800#define PWM_PHCHGNXT_MSKDAT1_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT1_Pos)
8802#define PWM_PHCHGNXT_MSKDAT2_Pos (2)
8803#define PWM_PHCHGNXT_MSKDAT2_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT2_Pos)
8805#define PWM_PHCHGNXT_MSKDAT3_Pos (3)
8806#define PWM_PHCHGNXT_MSKDAT3_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT3_Pos)
8808#define PWM_PHCHGNXT_MSKDAT4_Pos (4)
8809#define PWM_PHCHGNXT_MSKDAT4_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT4_Pos)
8811#define PWM_PHCHGNXT_MSKDAT5_Pos (5)
8812#define PWM_PHCHGNXT_MSKDAT5_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT5_Pos)
8814#define PWM_PHCHGNXT_MSKDAT6_Pos (6)
8815#define PWM_PHCHGNXT_MSKDAT6_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT6_Pos)
8817#define PWM_PHCHGNXT_MSKDAT7_Pos (7)
8818#define PWM_PHCHGNXT_MSKDAT7_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT7_Pos)
8820#define PWM_PHCHGNXT_MSKEN0_Pos (8)
8821#define PWM_PHCHGNXT_MSKEN0_Msk (0x1ul << PWM_PHCHGNXT_MSKEN0_Pos)
8823#define PWM_PHCHGNXT_MSKEN1_Pos (9)
8824#define PWM_PHCHGNXT_MSKEN1_Msk (0x1ul << PWM_PHCHGNXT_MSKEN1_Pos)
8826#define PWM_PHCHGNXT_MSKEN2_Pos (10)
8827#define PWM_PHCHGNXT_MSKEN2_Msk (0x1ul << PWM_PHCHGNXT_MSKEN2_Pos)
8829#define PWM_PHCHGNXT_MSKEN3_Pos (11)
8830#define PWM_PHCHGNXT_MSKEN3_Msk (0x1ul << PWM_PHCHGNXT_MSKEN3_Pos)
8832#define PWM_PHCHGNXT_MSKEN4_Pos (12)
8833#define PWM_PHCHGNXT_MSKEN4_Msk (0x1ul << PWM_PHCHGNXT_MSKEN4_Pos)
8835#define PWM_PHCHGNXT_MSKEN5_Pos (13)
8836#define PWM_PHCHGNXT_MSKEN5_Msk (0x1ul << PWM_PHCHGNXT_MSKEN5_Pos)
8838#define PWM_PHCHGNXT_AUTOCLR0_Pos (14)
8839#define PWM_PHCHGNXT_AUTOCLR0_Msk (0x1ul << PWM_PHCHGNXT_AUTOCLR0_Pos)
8841#define PWM_PHCHGNXT_AUTOCLR1_Pos (15)
8842#define PWM_PHCHGNXT_AUTOCLR1_Msk (0x1ul << PWM_PHCHGNXT_AUTOCLR1_Pos)
8844#define PWM_PHCHGNXT_AOFFEN01_Pos (16)
8845#define PWM_PHCHGNXT_AOFFEN01_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN01_Pos)
8847#define PWM_PHCHGNXT_AOFFEN11_Pos (17)
8848#define PWM_PHCHGNXT_AOFFEN11_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN11_Pos)
8850#define PWM_PHCHGNXT_AOFFEN21_Pos (18)
8851#define PWM_PHCHGNXT_AOFFEN21_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN21_Pos)
8853#define PWM_PHCHGNXT_AOFFEN31_Pos (19)
8854#define PWM_PHCHGNXT_AOFFEN31_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN31_Pos)
8856#define PWM_PHCHGNXT_A1POSSEL_Pos (20)
8857#define PWM_PHCHGNXT_A1POSSEL_Msk (0x3ul << PWM_PHCHGNXT_A1POSSEL_Pos)
8859#define PWM_PHCHGNXT_TMR1TEN_Pos (22)
8860#define PWM_PHCHGNXT_TMR1TEN_Msk (0x1ul << PWM_PHCHGNXT_TMR1TEN_Pos)
8862#define PWM_PHCHGNXT_ACMP1TEN_Pos (23)
8863#define PWM_PHCHGNXT_ACMP1TEN_Msk (0x1ul << PWM_PHCHGNXT_ACMP1TEN_Pos)
8865#define PWM_PHCHGNXT_AOFFEN00_Pos (24)
8866#define PWM_PHCHGNXT_AOFFEN00_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN00_Pos)
8868#define PWM_PHCHGNXT_AOFFEN10_Pos (25)
8869#define PWM_PHCHGNXT_AOFFEN10_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN10_Pos)
8871#define PWM_PHCHGNXT_AOFFEN20_Pos (26)
8872#define PWM_PHCHGNXT_AOFFEN20_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN20_Pos)
8874#define PWM_PHCHGNXT_AOFFEN30_Pos (27)
8875#define PWM_PHCHGNXT_AOFFEN30_Msk (0x1ul << PWM_PHCHGNXT_AOFFEN30_Pos)
8877#define PWM_PHCHGNXT_A0POSSEL_Pos (28)
8878#define PWM_PHCHGNXT_A0POSSEL_Msk (0x3ul << PWM_PHCHGNXT_A0POSSEL_Pos)
8880#define PWM_PHCHGNXT_TMR0TEN_Pos (30)
8881#define PWM_PHCHGNXT_TMR0TEN_Msk (0x1ul << PWM_PHCHGNXT_TMR0TEN_Pos)
8883#define PWM_PHCHGNXT_ACMP0TEN_Pos (31)
8884#define PWM_PHCHGNXT_ACMP0TEN_Msk (0x1ul << PWM_PHCHGNXT_ACMP0TEN_Pos)
8886#define PWM_PHCHGMSK_MASKEND6_Pos (6)
8887#define PWM_PHCHGMSK_MASKEND6_Msk (0x1ul << PWM_PHCHGMSK_MASKEND6_Pos)
8889#define PWM_PHCHGMSK_MASKEND7_Pos (7)
8890#define PWM_PHCHGMSK_MASKEND7_Msk (0x1ul << PWM_PHCHGMSK_MASKEND7_Pos)
8892#define PWM_PHCHGMSK_POSCTL0_Pos (8)
8893#define PWM_PHCHGMSK_POSCTL0_Msk (0x1ul << PWM_PHCHGMSK_POSCTL0_Pos)
8895#define PWM_PHCHGMSK_POSCTL1_Pos (9)
8896#define PWM_PHCHGMSK_POSCTL1_Msk (0x1ul << PWM_PHCHGMSK_POSCTL1_Pos)
8898#define PWM_IFA_IFAEN_Pos (0)
8899#define PWM_IFA_IFAEN_Msk (0x1ul << PWM_IFA_IFAEN_Pos)
8901#define PWM_IFA_IFCNT_Pos (4)
8902#define PWM_IFA_IFCNT_Msk (0xful << PWM_IFA_IFCNT_Pos)
8904#define PWM_PCACTL_PCAEN_Pos (0)
8905#define PWM_PCACTL_PCAEN_Msk (0x1ul << PWM_PCACTL_PCAEN_Pos)
8907#define PWM_MSKALIGN_MSKDAT0_Pos (0)
8908#define PWM_MSKALIGN_MSKDAT0_Msk (0x1ul << PWM_MSKALIGN_MSKDAT0_Pos)
8910#define PWM_MSKALIGN_MSKDAT1_Pos (1)
8911#define PWM_MSKALIGN_MSKDAT1_Msk (0x1ul << PWM_MSKALIGN_MSKDAT1_Pos)
8913#define PWM_MSKALIGN_MSKDAT2_Pos (2)
8914#define PWM_MSKALIGN_MSKDAT2_Msk (0x1ul << PWM_MSKALIGN_MSKDAT2_Pos)
8916#define PWM_MSKALIGN_MSKDAT3_Pos (3)
8917#define PWM_MSKALIGN_MSKDAT3_Msk (0x1ul << PWM_MSKALIGN_MSKDAT3_Pos)
8919#define PWM_MSKALIGN_MSKDAT4_Pos (4)
8920#define PWM_MSKALIGN_MSKDAT4_Msk (0x1ul << PWM_MSKALIGN_MSKDAT4_Pos)
8922#define PWM_MSKALIGN_MSKDAT5_Pos (5)
8923#define PWM_MSKALIGN_MSKDAT5_Msk (0x1ul << PWM_MSKALIGN_MSKDAT5_Pos)
8925#define PWM_MSKALIGN_MSKEN0_Pos (8)
8926#define PWM_MSKALIGN_MSKEN0_Msk (0x1ul << PWM_MSKALIGN_MSKEN0_Pos)
8928#define PWM_MSKALIGN_MSKEN1_Pos (9)
8929#define PWM_MSKALIGN_MSKEN1_Msk (0x1ul << PWM_MSKALIGN_MSKEN1_Pos)
8931#define PWM_MSKALIGN_MSKEN2_Pos (10)
8932#define PWM_MSKALIGN_MSKEN2_Msk (0x1ul << PWM_MSKALIGN_MSKEN2_Pos)
8934#define PWM_MSKALIGN_MSKEN3_Pos (11)
8935#define PWM_MSKALIGN_MSKEN3_Msk (0x1ul << PWM_MSKALIGN_MSKEN3_Pos)
8937#define PWM_MSKALIGN_MSKEN4_Pos (12)
8938#define PWM_MSKALIGN_MSKEN4_Msk (0x1ul << PWM_MSKALIGN_MSKEN4_Pos)
8940#define PWM_MSKALIGN_MSKEN5_Pos (13)
8941#define PWM_MSKALIGN_MSKEN5_Msk (0x1ul << PWM_MSKALIGN_MSKEN5_Pos)
8943#define PWM_MSKALIGN_ALIGN0_Pos (16)
8944#define PWM_MSKALIGN_ALIGN0_Msk (0x1ul << PWM_MSKALIGN_ALIGN0_Pos)
8946#define PWM_MSKALIGN_ALIGN1_Pos (17)
8947#define PWM_MSKALIGN_ALIGN1_Msk (0x1ul << PWM_MSKALIGN_ALIGN1_Pos)
8949#define PWM_MSKALIGN_ALIGN2_Pos (18)
8950#define PWM_MSKALIGN_ALIGN2_Msk (0x1ul << PWM_MSKALIGN_ALIGN2_Pos)
8952#define PWM_MSKALIGN_ALIGN3_Pos (19)
8953#define PWM_MSKALIGN_ALIGN3_Msk (0x1ul << PWM_MSKALIGN_ALIGN3_Pos)
8955#define PWM_MSKALIGN_ALIGN4_Pos (20)
8956#define PWM_MSKALIGN_ALIGN4_Msk (0x1ul << PWM_MSKALIGN_ALIGN4_Pos)
8958#define PWM_MSKALIGN_ALIGN5_Pos (21)
8959#define PWM_MSKALIGN_ALIGN5_Msk (0x1ul << PWM_MSKALIGN_ALIGN5_Pos)
9116 __I uint32_t RESERVED0[1];
9136 __I uint32_t RESERVED1[3];
9154 __I uint32_t RESERVED2[6];
9304#define SPI_CTL_SPIEN_Pos (0)
9305#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos)
9307#define SPI_CTL_RXNEG_Pos (1)
9308#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
9310#define SPI_CTL_TXNEG_Pos (2)
9311#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
9313#define SPI_CTL_DWIDTH_Pos (3)
9314#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
9316#define SPI_CTL_LSB_Pos (10)
9317#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
9319#define SPI_CTL_CLKPOL_Pos (11)
9320#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
9322#define SPI_CTL_SUSPITV_Pos (12)
9323#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
9325#define SPI_CTL_UNITIF_Pos (16)
9326#define SPI_CTL_UNITIF_Msk (0x1ul << SPI_CTL_UNITIF_Pos)
9328#define SPI_CTL_UNITIEN_Pos (17)
9329#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
9331#define SPI_CTL_SLAVE_Pos (18)
9332#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
9334#define SPI_CTL_REORDER_Pos (19)
9335#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
9337#define SPI_CTL_FIFOEN_Pos (21)
9338#define SPI_CTL_FIFOEN_Msk (0x1ul << SPI_CTL_FIFOEN_Pos)
9340#define SPI_CTL_RXEMPTY_Pos (24)
9341#define SPI_CTL_RXEMPTY_Msk (0x1ul << SPI_CTL_RXEMPTY_Pos)
9343#define SPI_CTL_RXFULL_Pos (25)
9344#define SPI_CTL_RXFULL_Msk (0x1ul << SPI_CTL_RXFULL_Pos)
9346#define SPI_CTL_TXEMPTY_Pos (26)
9347#define SPI_CTL_TXEMPTY_Msk (0x1ul << SPI_CTL_TXEMPTY_Pos)
9349#define SPI_CTL_TXFULL_Pos (27)
9350#define SPI_CTL_TXFULL_Msk (0x1ul << SPI_CTL_TXFULL_Pos)
9352#define SPI_CLKDIV_DIVIDER_Pos (0)
9353#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
9355#define SPI_SSCTL_SS_Pos (0)
9356#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos)
9358#define SPI_SSCTL_SSACTPOL_Pos (2)
9359#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
9361#define SPI_SSCTL_AUTOSS_Pos (3)
9362#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
9364#define SPI_SSCTL_SSLTEN_Pos (4)
9365#define SPI_SSCTL_SSLTEN_Msk (0x1ul << SPI_SSCTL_SSLTEN_Pos)
9367#define SPI_SSCTL_LTF_Pos (5)
9368#define SPI_SSCTL_LTF_Msk (0x1ul << SPI_SSCTL_LTF_Pos)
9370#define SPI_RX_RX_Pos (0)
9371#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
9373#define SPI_TX_TX_Pos (0)
9374#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
9376#define SPI_SLVCTL_SLV3WIRE_Pos (8)
9377#define SPI_SLVCTL_SLV3WIRE_Msk (0x1ul << SPI_SLVCTL_SLV3WIRE_Pos)
9379#define SPI_SLVCTL_SLVABT_Pos (9)
9380#define SPI_SLVCTL_SLVABT_Msk (0x1ul << SPI_SLVCTL_SLVABT_Pos)
9382#define SPI_SLVCTL_SLVSTIEN_Pos (10)
9383#define SPI_SLVCTL_SLVSTIEN_Msk (0x1ul << SPI_SLVCTL_SLVSTIEN_Pos)
9385#define SPI_SLVCTL_SLVSTIF_Pos (11)
9386#define SPI_SLVCTL_SLVSTIF_Msk (0x1ul << SPI_SLVCTL_SLVSTIF_Pos)
9388#define SPI_SLVCTL_SSINAIEN_Pos (16)
9389#define SPI_SLVCTL_SSINAIEN_Msk (0x1ul << SPI_SLVCTL_SSINAIEN_Pos)
9391#define SPI_SLVCTL_DIVMOD_Pos (31)
9392#define SPI_SLVCTL_DIVMOD_Msk (0x1ul << SPI_SLVCTL_DIVMOD_Pos)
9394#define SPI_FIFOCTL_RXRST_Pos (0)
9395#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos)
9397#define SPI_FIFOCTL_TXRST_Pos (1)
9398#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos)
9400#define SPI_FIFOCTL_RXTHIEN_Pos (2)
9401#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
9403#define SPI_FIFOCTL_TXTHIEN_Pos (3)
9404#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
9406#define SPI_FIFOCTL_RXOVIEN_Pos (6)
9407#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
9409#define SPI_FIFOCTL_RXTOIEN_Pos (21)
9410#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
9412#define SPI_FIFOCTL_RXTH_Pos (24)
9413#define SPI_FIFOCTL_RXTH_Msk (0x3ul << SPI_FIFOCTL_RXTH_Pos)
9415#define SPI_FIFOCTL_TXTH_Pos (28)
9416#define SPI_FIFOCTL_TXTH_Msk (0x3ul << SPI_FIFOCTL_TXTH_Pos)
9418#define SPI_STATUS_RXTHIF_Pos (0)
9419#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
9421#define SPI_STATUS_RXOVIF_Pos (2)
9422#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
9424#define SPI_STATUS_TXTHIF_Pos (4)
9425#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
9427#define SPI_STATUS_SLVSTIF_Pos (11)
9428#define SPI_STATUS_SLVSTIF_Msk (0x1ul << SPI_STATUS_SLVSTIF_Pos)
9430#define SPI_STATUS_RXCNT_Pos (12)
9431#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
9433#define SPI_STATUS_UNITIF_Pos (16)
9434#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
9436#define SPI_STATUS_SLVTOIF_Pos (20)
9437#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
9439#define SPI_STATUS_RXEMPTY_Pos (24)
9440#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
9442#define SPI_STATUS_RXFULL_Pos (25)
9443#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
9445#define SPI_STATUS_TXEMPTY_Pos (26)
9446#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
9448#define SPI_STATUS_TXFULL_Pos (27)
9449#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
9451#define SPI_STATUS_TXCNT_Pos (28)
9452#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
9590 __I uint32_t RESERVED0[2];
9636 __I uint32_t RESERVED1[5];
9946 __I uint32_t RESERVED2[14];
10023 __I uint32_t RESERVED3[29];
10064#define SYS_PDID_PDID_Pos (0)
10065#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
10067#define SYS_RSTSTS_PORF_Pos (0)
10068#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
10070#define SYS_RSTSTS_PINRF_Pos (1)
10071#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
10073#define SYS_RSTSTS_WDTRF_Pos (2)
10074#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
10076#define SYS_RSTSTS_BODRF_Pos (4)
10077#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
10079#define SYS_RSTSTS_SYSRF_Pos (5)
10080#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
10082#define SYS_RSTSTS_CPURF_Pos (7)
10083#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
10085#define SYS_RSTSTS_CPULKRF_Pos (8)
10086#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos)
10088#define SYS_IPRST0_CHIPRST_Pos (0)
10089#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos)
10091#define SYS_IPRST0_CPURST_Pos (1)
10092#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos)
10094#define SYS_IPRST1_GPIORST_Pos (1)
10095#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos)
10097#define SYS_IPRST1_TMR0RST_Pos (2)
10098#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos)
10100#define SYS_IPRST1_TMR1RST_Pos (3)
10101#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos)
10103#define SYS_IPRST1_I2C0RST_Pos (8)
10104#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos)
10106#define SYS_IPRST1_I2C1RST_Pos (9)
10107#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos)
10109#define SYS_IPRST1_SPI0RST_Pos (12)
10110#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos)
10112#define SYS_IPRST1_UART0RST_Pos (16)
10113#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos)
10115#define SYS_IPRST1_UART1RST_Pos (17)
10116#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos)
10118#define SYS_IPRST1_PWM0RST_Pos (20)
10119#define SYS_IPRST1_PWM0RST_Msk (0x1ul << SYS_IPRST1_PWM0RST_Pos)
10121#define SYS_IPRST1_ACMPRST_Pos (22)
10122#define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos)
10124#define SYS_IPRST1_ADCRST_Pos (28)
10125#define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos)
10127#define SYS_BODCTL_BODEN_Pos (0)
10128#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
10130#define SYS_BODCTL_BODVL_Pos (1)
10131#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos)
10133#define SYS_BODCTL_BODRSTEN_Pos (3)
10134#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos)
10136#define SYS_BODCTL_BODIF_Pos (4)
10137#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos)
10139#define SYS_BODCTL_BODLPM_Pos (5)
10140#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos)
10142#define SYS_BODCTL_BODOUT_Pos (6)
10143#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
10145#define SYS_P0_MFP_MFP_Pos (0)
10146#define SYS_P0_MFP_MFP_Msk (0xfful << SYS_P0_MFP_MFP_Pos)
10148#define SYS_P0_MFP_ALT0_Pos (8)
10149#define SYS_P0_MFP_ALT0_Msk (0x1ul << SYS_P0_MFP_ALT0_Pos)
10151#define SYS_P0_MFP_ALT1_Pos (9)
10152#define SYS_P0_MFP_ALT1_Msk (0x1ul << SYS_P0_MFP_ALT1_Pos)
10154#define SYS_P0_MFP_ALT4_Pos (12)
10155#define SYS_P0_MFP_ALT4_Msk (0x1ul << SYS_P0_MFP_ALT4_Pos)
10157#define SYS_P0_MFP_ALT5_Pos (13)
10158#define SYS_P0_MFP_ALT5_Msk (0x1ul << SYS_P0_MFP_ALT5_Pos)
10160#define SYS_P0_MFP_ALT6_Pos (14)
10161#define SYS_P0_MFP_ALT6_Msk (0x1ul << SYS_P0_MFP_ALT6_Pos)
10163#define SYS_P0_MFP_ALT7_Pos (15)
10164#define SYS_P0_MFP_ALT7_Msk (0x1ul << SYS_P0_MFP_ALT7_Pos)
10166#define SYS_P0_MFP_TYPE_Pos (16)
10167#define SYS_P0_MFP_TYPE_Msk (0xfful << SYS_P0_MFP_TYPE_Pos)
10169#define SYS_P1_MFP_MFP_Pos (0)
10170#define SYS_P1_MFP_MFP_Msk (0xfful << SYS_P1_MFP_MFP_Pos)
10172#define SYS_P1_MFP_ALT0_Pos (8)
10173#define SYS_P1_MFP_ALT0_Msk (0x1ul << SYS_P1_MFP_ALT0_Pos)
10175#define SYS_P1_MFP_ALT2_Pos (10)
10176#define SYS_P1_MFP_ALT2_Msk (0x1ul << SYS_P1_MFP_ALT2_Pos)
10178#define SYS_P1_MFP_ALT3_Pos (11)
10179#define SYS_P1_MFP_ALT3_Msk (0x1ul << SYS_P1_MFP_ALT3_Pos)
10181#define SYS_P1_MFP_ALT4_Pos (12)
10182#define SYS_P1_MFP_ALT4_Msk (0x1ul << SYS_P1_MFP_ALT4_Pos)
10184#define SYS_P1_MFP_ALT5_Pos (13)
10185#define SYS_P1_MFP_ALT5_Msk (0x1ul << SYS_P1_MFP_ALT5_Pos)
10187#define SYS_P1_MFP_TYPE_Pos (16)
10188#define SYS_P1_MFP_TYPE_Msk (0xfful << SYS_P1_MFP_TYPE_Pos)
10190#define SYS_P1_MFP_P12EXT_Pos (26)
10191#define SYS_P1_MFP_P12EXT_Msk (0x1ul << SYS_P1_MFP_P12EXT_Pos)
10193#define SYS_P1_MFP_P13EXT_Pos (27)
10194#define SYS_P1_MFP_P13EXT_Msk (0x1ul << SYS_P1_MFP_P13EXT_Pos)
10196#define SYS_P1_MFP_P14EXT_Pos (28)
10197#define SYS_P1_MFP_P14EXT_Msk (0x1ul << SYS_P1_MFP_P14EXT_Pos)
10199#define SYS_P2_MFP_MFP_Pos (0)
10200#define SYS_P2_MFP_MFP_Msk (0xfful << SYS_P2_MFP_MFP_Pos)
10202#define SYS_P2_MFP_ALT2_Pos (10)
10203#define SYS_P2_MFP_ALT2_Msk (0x1ul << SYS_P2_MFP_ALT2_Pos)
10205#define SYS_P2_MFP_ALT3_Pos (11)
10206#define SYS_P2_MFP_ALT3_Msk (0x1ul << SYS_P2_MFP_ALT3_Pos)
10208#define SYS_P2_MFP_ALT4_Pos (12)
10209#define SYS_P2_MFP_ALT4_Msk (0x1ul << SYS_P2_MFP_ALT4_Pos)
10211#define SYS_P2_MFP_ALT5_Pos (13)
10212#define SYS_P2_MFP_ALT5_Msk (0x1ul << SYS_P2_MFP_ALT5_Pos)
10214#define SYS_P2_MFP_ALT6_Pos (14)
10215#define SYS_P2_MFP_ALT6_Msk (0x1ul << SYS_P2_MFP_ALT6_Pos)
10217#define SYS_P2_MFP_TYPE_Pos (16)
10218#define SYS_P2_MFP_TYPE_Msk (0xfful << SYS_P2_MFP_TYPE_Pos)
10220#define SYS_P3_MFP_MFP_Pos (0)
10221#define SYS_P3_MFP_MFP_Msk (0xfful << SYS_P3_MFP_MFP_Pos)
10223#define SYS_P3_MFP_ALT0_Pos (8)
10224#define SYS_P3_MFP_ALT0_Msk (0x1ul << SYS_P3_MFP_ALT0_Pos)
10226#define SYS_P3_MFP_ALT1_Pos (9)
10227#define SYS_P3_MFP_ALT1_Msk (0x1ul << SYS_P3_MFP_ALT1_Pos)
10229#define SYS_P3_MFP_ALT2_Pos (10)
10230#define SYS_P3_MFP_ALT2_Msk (0x1ul << SYS_P3_MFP_ALT2_Pos)
10232#define SYS_P3_MFP_ALT4_Pos (12)
10233#define SYS_P3_MFP_ALT4_Msk (0x1ul << SYS_P3_MFP_ALT4_Pos)
10235#define SYS_P3_MFP_ALT5_Pos (13)
10236#define SYS_P3_MFP_ALT5_Msk (0x1ul << SYS_P3_MFP_ALT5_Pos)
10238#define SYS_P3_MFP_ALT6_Pos (14)
10239#define SYS_P3_MFP_ALT6_Msk (0x1ul << SYS_P3_MFP_ALT6_Pos)
10241#define SYS_P3_MFP_TYPE_Pos (16)
10242#define SYS_P3_MFP_TYPE_Msk (0xfful << SYS_P3_MFP_TYPE_Pos)
10244#define SYS_P3_MFP_P32EXT_Pos (26)
10245#define SYS_P3_MFP_P32EXT_Msk (0x1ul << SYS_P3_MFP_P32EXT_Pos)
10247#define SYS_P4_MFP_MFP_Pos (0)
10248#define SYS_P4_MFP_MFP_Msk (0xfful << SYS_P4_MFP_MFP_Pos)
10250#define SYS_P4_MFP_ALT6_Pos (14)
10251#define SYS_P4_MFP_ALT6_Msk (0x1ul << SYS_P4_MFP_ALT6_Pos)
10253#define SYS_P4_MFP_ALT7_Pos (15)
10254#define SYS_P4_MFP_ALT7_Msk (0x1ul << SYS_P4_MFP_ALT7_Pos)
10256#define SYS_P4_MFP_TYPE_Pos (16)
10257#define SYS_P4_MFP_TYPE_Msk (0xfful << SYS_P4_MFP_TYPE_Pos)
10259#define SYS_P5_MFP_MFP_Pos (0)
10260#define SYS_P5_MFP_MFP_Msk (0xfful << SYS_P5_MFP_MFP_Pos)
10262#define SYS_P5_MFP_ALT0_Pos (8)
10263#define SYS_P5_MFP_ALT0_Msk (0x1ul << SYS_P5_MFP_ALT0_Pos)
10265#define SYS_P5_MFP_ALT1_Pos (9)
10266#define SYS_P5_MFP_ALT1_Msk (0x1ul << SYS_P5_MFP_ALT1_Pos)
10268#define SYS_P5_MFP_ALT2_Pos (10)
10269#define SYS_P5_MFP_ALT2_Msk (0x1ul << SYS_P5_MFP_ALT2_Pos)
10271#define SYS_P5_MFP_ALT3_Pos (11)
10272#define SYS_P5_MFP_ALT3_Msk (0x1ul << SYS_P5_MFP_ALT3_Pos)
10274#define SYS_P5_MFP_ALT4_Pos (12)
10275#define SYS_P5_MFP_ALT4_Msk (0x1ul << SYS_P5_MFP_ALT4_Pos)
10277#define SYS_P5_MFP_ALT5_Pos (13)
10278#define SYS_P5_MFP_ALT5_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)
10280#define SYS_P5_MFP_TYPE_Pos (16)
10281#define SYS_P5_MFP_TYPE_Msk (0xfful << SYS_P5_MFP_TYPE_Pos)
10283#define SYS_IRCTCTL_FREQSEL_Pos (0)
10284#define SYS_IRCTCTL_FREQSEL_Msk (0x1ul << SYS_IRCTCTL_FREQSEL_Pos)
10286#define SYS_IRCTCTL_LOOPSEL_Pos (4)
10287#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)
10289#define SYS_IRCTIEN_TFAILIEN_Pos (1)
10290#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)
10292#define SYS_IRCTIEN_CLKEIEN_Pos (2)
10293#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)
10295#define SYS_IRCTISTS_FREQLOCK_Pos (0)
10296#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)
10298#define SYS_IRCTISTS_TFAILIF_Pos (1)
10299#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)
10301#define SYS_IRCTISTS_CLKERRIF_Pos (2)
10302#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)
10304#define SYS_REGLCTL_REGLCTL_Pos (0)
10305#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos)
10529#define TIMER_CTL_PSC_Pos (0)
10530#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
10532#define TIMER_CTL_CMPCTL_Pos (17)
10533#define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos)
10535#define TIMER_CTL_TGLPINSEL_Pos (18)
10536#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos)
10538#define TIMER_CTL_CAPSRC_Pos (19)
10539#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos)
10541#define TIMER_CTL_WKEN_Pos (23)
10542#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
10544#define TIMER_CTL_EXTCNTEN_Pos (24)
10545#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
10547#define TIMER_CTL_ACTSTS_Pos (25)
10548#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
10550#define TIMER_CTL_RSTCNT_Pos (26)
10551#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
10553#define TIMER_CTL_OPMODE_Pos (27)
10554#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
10556#define TIMER_CTL_INTEN_Pos (29)
10557#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
10559#define TIMER_CTL_CNTEN_Pos (30)
10560#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
10562#define TIMER_CTL_ICEDEBUG_Pos (31)
10563#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
10565#define TIMER_CMP_CMPDAT_Pos (0)
10566#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos)
10568#define TIMER_INTSTS_TIF_Pos (0)
10569#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
10571#define TIMER_INTSTS_TWKF_Pos (1)
10572#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
10574#define TIMER_CNT_CNT_Pos (0)
10575#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
10577#define TIMER_CAP_CAPDAT_Pos (0)
10578#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
10580#define TIMER_EXTCTL_CNTPHASE_Pos (0)
10581#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
10583#define TIMER_EXTCTL_CAPEDGE_Pos (1)
10584#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
10586#define TIMER_EXTCTL_CAPEN_Pos (3)
10587#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
10589#define TIMER_EXTCTL_CAPFUNCS_Pos (4)
10590#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
10592#define TIMER_EXTCTL_CAPIEN_Pos (5)
10593#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
10595#define TIMER_EXTCTL_CAPDBEN_Pos (6)
10596#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
10598#define TIMER_EXTCTL_CNTDBEN_Pos (7)
10599#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)
10601#define TIMER_EXTCTL_CAPSEL_Pos (8)
10602#define TIMER_EXTCTL_CAPSEL_Msk (0x1ul << TIMER_EXTCTL_CAPSEL_Pos)
10604#define TIMER_EXTCTL_ACMPSSEL_Pos (9)
10605#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos)
10607#define TIMER_EINTSTS_CAPIF_Pos (0)
10608#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos)
10610#define TIMER_CTL_PSC_Pos (0)
10611#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
10613#define TIMER_CTL_CMPCTL_Pos (17)
10614#define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos)
10616#define TIMER_CTL_TGLPINSEL_Pos (18)
10617#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos)
10619#define TIMER_CTL_CAPSRC_Pos (19)
10620#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos)
10622#define TIMER_CTL_WKEN_Pos (23)
10623#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
10625#define TIMER_CTL_EXTCNTEN_Pos (24)
10626#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
10628#define TIMER_CTL_ACTSTS_Pos (25)
10629#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
10631#define TIMER_CTL_RSTCNT_Pos (26)
10632#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
10634#define TIMER_CTL_OPMODE_Pos (27)
10635#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
10637#define TIMER_CTL_INTEN_Pos (29)
10638#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
10640#define TIMER_CTL_CNTEN_Pos (30)
10641#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
10643#define TIMER_CTL_ICEDEBUG_Pos (31)
10644#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
10646#define TIMER_CMP_CMPDAT_Pos (0)
10647#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos)
10649#define TIMER_INTSTS_TIF_Pos (0)
10650#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
10652#define TIMER_INTSTS_TWKF_Pos (1)
10653#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
10655#define TIMER_CNT_CNT_Pos (0)
10656#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
10658#define TIMER_CAP_CAPDAT_Pos (0)
10659#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
10661#define TIMER_EXTCTL_CNTPHASE_Pos (0)
10662#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
10664#define TIMER_EXTCTL_CAPEDGE_Pos (1)
10665#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
10667#define TIMER_EXTCTL_CAPEN_Pos (3)
10668#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
10670#define TIMER_EXTCTL_CAPFUNCS_Pos (4)
10671#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
10673#define TIMER_EXTCTL_CAPIEN_Pos (5)
10674#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
10676#define TIMER_EXTCTL_CAPDBEN_Pos (6)
10677#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
10679#define TIMER_EXTCTL_CNTDBEN_Pos (7)
10680#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)
10682#define TIMER_EXTCTL_CAPSEL_Pos (8)
10683#define TIMER_EXTCTL_CAPSEL_Msk (0x1ul << TIMER_EXTCTL_CAPSEL_Pos)
10685#define TIMER_EXTCTL_ACMPSSEL_Pos (9)
10686#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos)
10688#define TIMER_EINTSTS_CAPIF_Pos (0)
10689#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos)
11165#define UART_DAT_DAT_Pos (0)
11166#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
11168#define UART_INTEN_RDAIEN_Pos (0)
11169#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
11171#define UART_INTEN_THREIEN_Pos (1)
11172#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
11174#define UART_INTEN_RLSIEN_Pos (2)
11175#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
11177#define UART_INTEN_MODEMIEN_Pos (3)
11178#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
11180#define UART_INTEN_RXTOIEN_Pos (4)
11181#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
11183#define UART_INTEN_BUFERRIEN_Pos (5)
11184#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
11186#define UART_INTEN_WKCTSIEN_Pos (9)
11187#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos)
11189#define UART_INTEN_TOCNTEN_Pos (11)
11190#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos)
11192#define UART_INTEN_ATORTSEN_Pos (12)
11193#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos)
11195#define UART_INTEN_ATOCTSEN_Pos (13)
11196#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos)
11198#define UART_FIFO_RXRST_Pos (1)
11199#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos)
11201#define UART_FIFO_TXRST_Pos (2)
11202#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos)
11204#define UART_FIFO_RFITL_Pos (4)
11205#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos)
11207#define UART_FIFO_RXOFF_Pos (8)
11208#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos)
11210#define UART_FIFO_RTSTRGLV_Pos (16)
11211#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos)
11213#define UART_LINE_WLS_Pos (0)
11214#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
11216#define UART_LINE_NSB_Pos (2)
11217#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
11219#define UART_LINE_PBE_Pos (3)
11220#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
11222#define UART_LINE_EPE_Pos (4)
11223#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
11225#define UART_LINE_SPE_Pos (5)
11226#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
11228#define UART_LINE_BCB_Pos (6)
11229#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
11231#define UART_MODEM_RTS_Pos (1)
11232#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos)
11234#define UART_MODEM_RTSACTLV_Pos (9)
11235#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
11237#define UART_MODEM_RTSSTS_Pos (13)
11238#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
11240#define UART_MODEMSTS_CTSDETF_Pos (0)
11241#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos)
11243#define UART_MODEMSTS_CTSSTS_Pos (4)
11244#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos)
11246#define UART_MODEMSTS_CTSACTLV_Pos (8)
11247#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)
11249#define UART_FIFOSTS_RXOVIF_Pos (0)
11250#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
11252#define UART_FIFOSTS_ADDRDETF_Pos (3)
11253#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)
11255#define UART_FIFOSTS_PEF_Pos (4)
11256#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
11258#define UART_FIFOSTS_FEF_Pos (5)
11259#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
11261#define UART_FIFOSTS_BIF_Pos (6)
11262#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
11264#define UART_FIFOSTS_RXPTR_Pos (8)
11265#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos)
11267#define UART_FIFOSTS_RXEMPTY_Pos (14)
11268#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
11270#define UART_FIFOSTS_RXFULL_Pos (15)
11271#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
11273#define UART_FIFOSTS_TXPTR_Pos (16)
11274#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos)
11276#define UART_FIFOSTS_TXEMPTY_Pos (22)
11277#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
11279#define UART_FIFOSTS_TXFULL_Pos (23)
11280#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
11282#define UART_FIFOSTS_TXOVIF_Pos (24)
11283#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
11285#define UART_FIFOSTS_TXEMPTYF_Pos (28)
11286#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)
11288#define UART_INTSTS_RDAIF_Pos (0)
11289#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
11291#define UART_INTSTS_THREIF_Pos (1)
11292#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
11294#define UART_INTSTS_RLSIF_Pos (2)
11295#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
11297#define UART_INTSTS_MODEMIF_Pos (3)
11298#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
11300#define UART_INTSTS_RXTOIF_Pos (4)
11301#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
11303#define UART_INTSTS_BUFERRIF_Pos (5)
11304#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
11306#define UART_INTSTS_RDAINT_Pos (8)
11307#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos)
11309#define UART_INTSTS_THREINT_Pos (9)
11310#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos)
11312#define UART_INTSTS_RLSINT_Pos (10)
11313#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos)
11315#define UART_INTSTS_MODEMINT_Pos (11)
11316#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos)
11318#define UART_INTSTS_RXTOINT_Pos (12)
11319#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos)
11321#define UART_INTSTS_BUFERRINT_Pos (13)
11322#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos)
11324#define UART_INTSTS_CTSWKIF_Pos (16)
11325#define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos)
11327#define UART_TOUT_TOIC_Pos (0)
11328#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos)
11330#define UART_TOUT_DLY_Pos (8)
11331#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
11333#define UART_BAUD_BRD_Pos (0)
11334#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
11336#define UART_BAUD_EDIVM1_Pos (24)
11337#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos)
11339#define UART_BAUD_BAUDM0_Pos (28)
11340#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos)
11342#define UART_BAUD_BAUDM1_Pos (29)
11343#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos)
11345#define UART_IRDA_TXEN_Pos (1)
11346#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
11348#define UART_IRDA_TXINV_Pos (5)
11349#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
11351#define UART_IRDA_RXINV_Pos (6)
11352#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
11354#define UART_ALTCTL_RS485_NMM_Pos (8)
11355#define UART_ALTCTL_RS485_NMM_Msk (0x1ul << UART_ALTCTL_RS485_NMM_Pos)
11357#define UART_ALTCTL_RS485_AAD_Pos (9)
11358#define UART_ALTCTL_RS485_AAD_Msk (0x1ul << UART_ALTCTL_RS485_AAD_Pos)
11360#define UART_ALTCTL_RS485_AUD_Pos (10)
11361#define UART_ALTCTL_RS485_AUD_Msk (0x1ul << UART_ALTCTL_RS485_AUD_Pos)
11363#define UART_ALTCTL_ADDRDEN_Pos (15)
11364#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
11366#define UART_ALTCTL_ADDRMV_Pos (24)
11367#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos)
11369#define UART_FUNSEL_FUN_SEL_Pos (0)
11370#define UART_FUNSEL_FUN_SEL_Msk (0x3ul << UART_FUNSEL_FUN_SEL_Pos)
11482#define WDT_CTL_RSTCNT_Pos (0)
11483#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
11485#define WDT_CTL_RSTEN_Pos (1)
11486#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
11488#define WDT_CTL_RSTF_Pos (2)
11489#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)
11491#define WDT_CTL_IF_Pos (3)
11492#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)
11494#define WDT_CTL_WKEN_Pos (4)
11495#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
11497#define WDT_CTL_WKF_Pos (5)
11498#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
11500#define WDT_CTL_INTEN_Pos (6)
11501#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)
11503#define WDT_CTL_WDTEN_Pos (7)
11504#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
11506#define WDT_CTL_TOUTSEL_Pos (8)
11507#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos)
11509#define WDT_CTL_ICEDEBUG_Pos (31)
11510#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos)
11512#define WDT_ALTCTL_RSTDSEL_Pos (0)
11513#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)
11626#define WWDT_RLDCNT_RLDCNT_Pos (0)
11627#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)
11629#define WWDT_CTL_WWDTEN_Pos (0)
11630#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
11632#define WWDT_CTL_INTEN_Pos (1)
11633#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos)
11635#define WWDT_CTL_PSCSEL_Pos (8)
11636#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos)
11638#define WWDT_CTL_CMPDAT_Pos (16)
11639#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos)
11641#define WWDT_CTL_ICEDEBUG_Pos (31)
11642#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos)
11644#define WWDT_STATUS_WWDTIF_Pos (0)
11645#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
11647#define WWDT_STATUS_WWDTRF_Pos (1)
11648#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
11650#define WWDT_CNT_CNTDAT_Pos (0)
11651#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos)
11657#if defined ( __CC_ARM )
11658#pragma no_anon_unions
11666#define FLASH_BASE ((uint32_t)0x00000000)
11667#define SRAM_BASE ((uint32_t)0x20000000)
11668#define APB1PERIPH_BASE ((uint32_t)0x40000000)
11669#define APB2PERIPH_BASE ((uint32_t)0x40100000)
11670#define AHBPERIPH_BASE ((uint32_t)0x50000000)
11673#define WDT_BASE (APB1PERIPH_BASE + 0x04000)
11674#define WWDT_BASE (APB1PERIPH_BASE + 0x04100)
11675#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
11676#define TIMER1_BASE (APB1PERIPH_BASE + 0x10020)
11677#define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
11678#define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
11679#define SPI_BASE (APB1PERIPH_BASE + 0x30000)
11680#define PWM_BASE (APB1PERIPH_BASE + 0x40000)
11681#define UART0_BASE (APB1PERIPH_BASE + 0x50000)
11682#define UART1_BASE (APB2PERIPH_BASE + 0x50000)
11683#define ACMP_BASE (APB1PERIPH_BASE + 0xD0000)
11684#define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
11686#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
11687#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
11688#define INTR_BASE (AHBPERIPH_BASE + 0x00300)
11689#define P0_BASE (AHBPERIPH_BASE + 0x04000)
11690#define P1_BASE (AHBPERIPH_BASE + 0x04040)
11691#define P2_BASE (AHBPERIPH_BASE + 0x04080)
11692#define P3_BASE (AHBPERIPH_BASE + 0x040C0)
11693#define P4_BASE (AHBPERIPH_BASE + 0x04100)
11694#define P5_BASE (AHBPERIPH_BASE + 0x04140)
11695#define GPIO_DBNCECON_BASE (AHBPERIPH_BASE + 0x04180)
11696#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
11697#define GPIOBIT0_BASE (AHBPERIPH_BASE + 0x04200)
11698#define GPIOBIT1_BASE (AHBPERIPH_BASE + 0x04220)
11699#define GPIOBIT2_BASE (AHBPERIPH_BASE + 0x04240)
11700#define GPIOBIT3_BASE (AHBPERIPH_BASE + 0x04260)
11701#define GPIOBIT4_BASE (AHBPERIPH_BASE + 0x04280)
11702#define GPIOBIT5_BASE (AHBPERIPH_BASE + 0x042A0)
11703#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
11713#define WDT ((WDT_T *) WDT_BASE)
11714#define WWDT ((WWDT_T *) WWDT_BASE)
11715#define TIMER0 ((TIMER_T *) TIMER0_BASE)
11716#define TIMER1 ((TIMER_T *) TIMER1_BASE)
11717#define I2C ((I2C_T *) I2C0_BASE)
11718#define I2C0 ((I2C_T *) I2C0_BASE)
11719#define I2C1 ((I2C_T *) I2C1_BASE)
11720#define SPI ((SPI_T *) SPI_BASE)
11721#define SPI0 ((SPI_T *) SPI_BASE)
11722#define PWM ((PWM_T *) PWM_BASE)
11723#define UART ((UART_T *) UART0_BASE)
11724#define UART0 ((UART_T *) UART0_BASE)
11725#define UART1 ((UART_T *) UART1_BASE)
11726#define ADC ((ADC_T *) ADC_BASE)
11727#define ACMP ((ACMP_T *) ACMP_BASE)
11729#define SYS ((SYS_T *) SYS_BASE)
11730#define CLK ((CLK_T *) CLK_BASE)
11731#define INTR ((INTR_T *) INTR_BASE)
11732#define P0 ((GPIO_T *) P0_BASE)
11733#define P1 ((GPIO_T *) P1_BASE)
11734#define P2 ((GPIO_T *) P2_BASE)
11735#define P3 ((GPIO_T *) P3_BASE)
11736#define P4 ((GPIO_T *) P4_BASE)
11737#define P5 ((GPIO_T *) P5_BASE)
11738#define GPIO ((GPIO_DB_T *) GPIO_DBNCECON_BASE)
11739#define FMC ((FMC_T *) FMC_BASE)
11749typedef volatile unsigned char vu8;
11758#define M8(addr) (*((vu8 *) (addr)))
11766#define M16(addr) (*((vu16 *) (addr)))
11774#define M32(addr) (*((vu32 *) (addr)))
11783#define outpw(port,value) *((volatile unsigned int *)(port)) = value
11791#define inpw(port) (*((volatile unsigned int *)(port)))
11800#define outps(port,value) *((volatile unsigned short *)(port)) = value
11808#define inps(port) (*((volatile unsigned short *)(port)))
11816#define outpb(port,value) *((volatile unsigned char *)(port)) = value
11823#define inpb(port) (*((volatile unsigned char *)(port)))
11832#define outp32(port,value) *((volatile unsigned int *)(port)) = value
11840#define inp32(port) (*((volatile unsigned int *)(port)))
11849#define outp16(port,value) *((volatile unsigned short *)(port)) = value
11857#define inp16(port) (*((volatile unsigned short *)(port)))
11865#define outp8(port,value) *((volatile unsigned char *)(port)) = value
11872#define inp8(port) (*((volatile unsigned char *)(port)))
11896#define BIT0 (0x00000001)
11897#define BIT1 (0x00000002)
11898#define BIT2 (0x00000004)
11899#define BIT3 (0x00000008)
11900#define BIT4 (0x00000010)
11901#define BIT5 (0x00000020)
11902#define BIT6 (0x00000040)
11903#define BIT7 (0x00000080)
11904#define BIT8 (0x00000100)
11905#define BIT9 (0x00000200)
11906#define BIT10 (0x00000400)
11907#define BIT11 (0x00000800)
11908#define BIT12 (0x00001000)
11909#define BIT13 (0x00002000)
11910#define BIT14 (0x00004000)
11911#define BIT15 (0x00008000)
11912#define BIT16 (0x00010000)
11913#define BIT17 (0x00020000)
11914#define BIT18 (0x00040000)
11915#define BIT19 (0x00080000)
11916#define BIT20 (0x00100000)
11917#define BIT21 (0x00200000)
11918#define BIT22 (0x00400000)
11919#define BIT23 (0x00800000)
11920#define BIT24 (0x01000000)
11921#define BIT25 (0x02000000)
11922#define BIT26 (0x04000000)
11923#define BIT27 (0x08000000)
11924#define BIT28 (0x10000000)
11925#define BIT29 (0x20000000)
11926#define BIT30 (0x40000000)
11927#define BIT31 (0x80000000)
11930#define BYTE0_Msk (0x000000FF)
11931#define BYTE1_Msk (0x0000FF00)
11932#define BYTE2_Msk (0x00FF0000)
11933#define BYTE3_Msk (0xFF000000)
11935#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
11936#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
11937#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
11938#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
Mini58 series Analog Comparator(ACMP) driver header file.
Mini58 series ADC driver header file.
Mini58 series CLK driver header file.
Mini58 series FMC driver header file.
Mini58 series GPIO driver header file.
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Mini58 series I2C driver header file.
Mini58 series PWM driver header file.
Mini58 series SPI driver header file.
Mini58 series SYS driver header file.
Mini58 series system clock definition file.
Mini58 series TIMER driver header file.
Mini58 series UART driver header file.
Mini58 series WDT driver header file.
Mini58 series WWDT driver header file.