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M480 BSP V3.05.005
The Board Support Package for M480 Series
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#include <dac_reg.h>
Data Fields | |
__IO uint32_t | CTL |
__IO uint32_t | SWTRG |
__IO uint32_t | DAT |
__I uint32_t | DATOUT |
__IO uint32_t | STATUS |
__IO uint32_t | TCTL |
@addtogroup DAC Digital to Analog Converter(DAC) Memory Mapped Structure for DAC Controller
DAC_T::CTL |
[0x0000] DAC Control Register
Bits | Field | Descriptions |
[0] | DACEN | DAC Enable Bit
0 = DAC is Disabled. 1 = DAC is Enabled. |
[1] | DACIEN | DAC Interrupt Enable Bit
0 = Interrupt is Disabled. 1 = Interrupt is Enabled. |
[2] | DMAEN | DMA Mode Enable Bit
0 = DMA mode Disabled. 1 = DMA mode Enabled. |
[3] | DMAURIEN | DMA Under-run Interrupt Enable Bit
0 = DMA under-run interrupt Disabled. 1 = DMA under-run interrupt Enabled. |
[4] | TRGEN | Trigger Mode Enable Bit
0 = DAC event trigger mode Disabled. 1 = DAC event trigger mode Enabled. |
[7:5] | TRGSEL | Trigger Source Selection
000 = Software trigger. 001 = External pin DAC0_ST trigger. 010 = Timer 0 trigger. 011 = Timer 1 trigger. 100 = Timer 2 trigger. 101 = Timer 3 trigger. 110 = EPWM0 trigger. 111 = EPWM1 trigger. |
[8] | BYPASS | Bypass Buffer Mode
0 = Output voltage buffer Enabled. 1 = Output voltage buffer Disabled. |
[10] | LALIGN | DAC Data Left-aligned Enabled Control
0 = Right alignment. 1 = Left alignment. |
[13:12] | ETRGSEL | External Pin Trigger Selection
00 = Low level trigger. 01 = High level trigger. 10 = Falling edge trigger. 11 = Rising edge trigger. |
[15:14] | BWSEL | DAC Data Bit-width Selection
00 = data is 12 bits. 01 = data is 8 bits. Others = reserved. |
[16] | GRPEN | DAC Group Mode Enable Bit
0 = DAC0 and DAC1 are not grouped. 1 = DAC0 and DAC1 are grouped. |
DAC_T::DAT |
[0x0008] DAC Data Holding Register
Bits | Field | Descriptions |
[15:0] | DACDAT | DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. |
DAC_T::DATOUT |
[0x000c] DAC Data Output Register
Bits | Field | Descriptions |
[11:0] | DATOUT | DAC 12-bit Output Data
These bits are current digital data for DAC output conversion. It is loaded from DAC_DAT register and user cannot write it directly. |
DAC_T::STATUS |
[0x0010] DAC Status Register
Bits | Field | Descriptions |
[0] | FINISH | DAC Conversion Complete Finish Flag
0 = DAC is in conversion state. 1 = DAC conversion finish. This bit set to 1 when conversion time counter counts to SETTLET It is cleared to 0 when DAC starts a new conversion User writes 1 to clear this bit to 0. |
[1] | DMAUDR | DMA Under-run Interrupt Flag
0 = No DMA under-run error condition occurred. 1 = DMA under-run error condition occurred. User writes 1 to clear this bit. |
[8] | BUSY | DAC Busy Flag (Read Only)
0 = DAC is ready for next conversion. 1 = DAC is busy in conversion. This is read only bit. |
DAC_T::SWTRG |
[0x0004] DAC Software Trigger Control Register
Bits | Field | Descriptions |
[0] | SWTRG | Software Trigger
0 = Software trigger Disabled. 1 = Software trigger Enabled. User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. |
DAC_T::TCTL |
[0x0014] DAC Timing Control Register
Bits | Field | Descriptions |
[9:0] | SETTLET | DAC Output Settling Time
User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. SELTTLET = DAC controller clock speed x settling time. |