M480 BSP
V3.05.005
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
qei_reg.h
Go to the documentation of this file.
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/**************************************************************************/
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#ifndef __QEI_REG_H__
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#define __QEI_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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typedef
struct
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{
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__IO uint32_t
CNT
;
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__IO uint32_t
CNTHOLD
;
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__IO uint32_t
CNTLATCH
;
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__IO uint32_t
CNTCMP
;
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__I uint32_t RESERVE0[1];
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__IO uint32_t
CNTMAX
;
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__IO uint32_t
CTL
;
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__I uint32_t RESERVE1[4];
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__IO uint32_t
STATUS
;
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}
QEI_T
;
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#define QEI_CNT_CNT_Pos (0)
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#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos)
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#define QEI_CNTHOLD_CNTHOLD_Pos (0)
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#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos)
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#define QEI_CNTLATCH_CNTLATCH_Pos (0)
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#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos)
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#define QEI_CNTCMP_CNTCMP_Pos (0)
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#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos)
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#define QEI_CNTMAX_CNTMAX_Pos (0)
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#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos)
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#define QEI_CTL_NFCLKSEL_Pos (0)
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#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos)
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#define QEI_CTL_NFDIS_Pos (3)
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#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos)
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#define QEI_CTL_CHAEN_Pos (4)
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#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos)
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#define QEI_CTL_CHBEN_Pos (5)
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#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos)
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#define QEI_CTL_IDXEN_Pos (6)
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#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos)
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#define QEI_CTL_MODE_Pos (8)
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#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos)
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#define QEI_CTL_CHAINV_Pos (12)
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#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos)
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#define QEI_CTL_CHBINV_Pos (13)
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#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos)
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#define QEI_CTL_IDXINV_Pos (14)
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#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos)
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#define QEI_CTL_OVUNIEN_Pos (16)
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#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos)
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#define QEI_CTL_DIRIEN_Pos (17)
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#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos)
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#define QEI_CTL_CMPIEN_Pos (18)
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#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos)
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#define QEI_CTL_IDXIEN_Pos (19)
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#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos)
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#define QEI_CTL_HOLDTMR0_Pos (20)
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#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos)
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#define QEI_CTL_HOLDTMR1_Pos (21)
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#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos)
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#define QEI_CTL_HOLDTMR2_Pos (22)
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#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos)
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#define QEI_CTL_HOLDTMR3_Pos (23)
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#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos)
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#define QEI_CTL_HOLDCNT_Pos (24)
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#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos)
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#define QEI_CTL_IDXLATEN_Pos (25)
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#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos)
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#define QEI_CTL_IDXRLDEN_Pos (27)
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#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos)
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#define QEI_CTL_CMPEN_Pos (28)
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#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos)
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#define QEI_CTL_QEIEN_Pos (29)
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#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos)
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#define QEI_STATUS_IDXF_Pos (0)
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#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos)
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#define QEI_STATUS_CMPF_Pos (1)
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#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos)
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#define QEI_STATUS_OVUNF_Pos (2)
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#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos)
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#define QEI_STATUS_DIRCHGF_Pos (3)
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#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos)
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#define QEI_STATUS_DIRF_Pos (8)
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#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos)
/* QEI_CONST */
/* end of QEI register group */
/* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif
/* __QEI_REG_H__ */
QEI_T
Definition:
qei_reg.h:27
QEI_T::STATUS
__IO uint32_t STATUS
Definition:
qei_reg.h:414
QEI_T::CTL
__IO uint32_t CTL
Definition:
qei_reg.h:410
QEI_T::CNTLATCH
__IO uint32_t CNTLATCH
Definition:
qei_reg.h:404
QEI_T::CNTMAX
__IO uint32_t CNTMAX
Definition:
qei_reg.h:409
QEI_T::CNTHOLD
__IO uint32_t CNTHOLD
Definition:
qei_reg.h:403
QEI_T::CNT
__IO uint32_t CNT
Definition:
qei_reg.h:402
QEI_T::CNTCMP
__IO uint32_t CNTCMP
Definition:
qei_reg.h:405
Generated on Thu Mar 16 2023 13:35:48 for M480 BSP by
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