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M480 BSP V3.05.005
The Board Support Package for M480 Series
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Macros | |
#define | DAC_START_CONV(dac) |
Start the D/A conversion. More... | |
#define | DAC_ENABLE_LEFT_ALIGN(dac) |
Enable DAC data left-aligned. More... | |
#define | DAC_ENABLE_RIGHT_ALIGN(dac) |
Enable DAC data right-aligned. More... | |
#define | DAC_ENABLE_BYPASS_BUFFER(dac) |
Enable bypass voltage output buffer mode. More... | |
#define | DAC_DISABLE_BYPASS_BUFFER(dac) |
Disable bypass voltage output buffer mode. More... | |
#define | DAC_ENABLE_INT(dac, u32Ch) |
Enable the interrupt. More... | |
#define | DAC_DISABLE_INT(dac, u32Ch) |
Disable the interrupt. More... | |
#define | DAC_ENABLE_DMAUDR_INT(dac) |
Enable DMA under-run interrupt. More... | |
#define | DAC_DISABLE_DMAUDR_INT(dac) |
Disable DMA under-run interrupt. More... | |
#define | DAC_ENABLE_PDMA(dac) |
Enable PDMA mode. More... | |
#define | DAC_DISABLE_PDMA(dac) |
Disable PDMA mode. More... | |
#define | DAC_WRITE_DATA(dac, u32Ch, u32Data) |
Write data for conversion. More... | |
#define | DAC_READ_DATA(dac, u32Ch) |
Read DAC 12-bit holding data. More... | |
#define | DAC_IS_BUSY(dac, u32Ch) |
Get the busy state of DAC. More... | |
#define | DAC_GET_INT_FLAG(dac, u32Ch) |
Get the interrupt flag. More... | |
#define | DAC_GET_DMAUDR_FLAG(dac) |
Get the DMA under-run flag. More... | |
#define | DAC_CLR_INT_FLAG(dac, u32Ch) |
This macro clear the interrupt status bit. More... | |
#define | DAC_CLR_DMAUDR_FLAG(dac) |
This macro clear the DMA under-run flag. More... | |
#define | DAC_ENABLE_GROUP_MODE(dac) |
Enable DAC group mode. More... | |
#define | DAC_DISABLE_GROUP_MODE(dac) |
Disable DAC group mode. More... | |
Functions | |
void | DAC_Open (DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc) |
This function make DAC module be ready to convert. More... | |
void | DAC_Close (DAC_T *dac, uint32_t u32Ch) |
Disable DAC analog power. More... | |
uint32_t | DAC_SetDelayTime (DAC_T *dac, uint32_t u32Delay) |
Set delay time for DAC to become stable. More... | |
#define DAC_CLR_DMAUDR_FLAG | ( | dac | ) |
#define DAC_CLR_INT_FLAG | ( | dac, | |
u32Ch | |||
) |
#define DAC_DISABLE_BYPASS_BUFFER | ( | dac | ) |
#define DAC_DISABLE_DMAUDR_INT | ( | dac | ) |
#define DAC_DISABLE_GROUP_MODE | ( | dac | ) |
#define DAC_DISABLE_INT | ( | dac, | |
u32Ch | |||
) |
#define DAC_DISABLE_PDMA | ( | dac | ) |
#define DAC_ENABLE_BYPASS_BUFFER | ( | dac | ) |
#define DAC_ENABLE_DMAUDR_INT | ( | dac | ) |
#define DAC_ENABLE_GROUP_MODE | ( | dac | ) |
#define DAC_ENABLE_INT | ( | dac, | |
u32Ch | |||
) |
#define DAC_ENABLE_LEFT_ALIGN | ( | dac | ) |
#define DAC_ENABLE_PDMA | ( | dac | ) |
#define DAC_ENABLE_RIGHT_ALIGN | ( | dac | ) |
#define DAC_GET_DMAUDR_FLAG | ( | dac | ) |
#define DAC_GET_INT_FLAG | ( | dac, | |
u32Ch | |||
) |
Get the interrupt flag.
[in] | dac | Base address of DAC module. |
[in] | u32Ch | Not used in M480 DAC. |
0 | DAC is in conversion state. |
1 | DAC conversion finish. |
This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
#define DAC_IS_BUSY | ( | dac, | |
u32Ch | |||
) |
#define DAC_READ_DATA | ( | dac, | |
u32Ch | |||
) |
#define DAC_START_CONV | ( | dac | ) |
#define DAC_WRITE_DATA | ( | dac, | |
u32Ch, | |||
u32Data | |||
) |
Write data for conversion.
[in] | dac | Base address of DAC module. |
[in] | u32Ch | Not used in M480 DAC. |
[in] | u32Data | Decides the data for conversion, valid range are between 0~0xFFF. |
12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
void DAC_Close | ( | DAC_T * | dac, |
uint32_t | u32Ch | ||
) |
void DAC_Open | ( | DAC_T * | dac, |
uint32_t | u32Ch, | ||
uint32_t | u32TrgSrc | ||
) |
This function make DAC module be ready to convert.
[in] | dac | Base address of DAC module. |
[in] | u32Ch | Not used in M480 DAC. |
[in] | u32TrgSrc | Decides the trigger source. Valid values are:
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The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, external STDAC pin, timer event, or EPWM event.
uint32_t DAC_SetDelayTime | ( | DAC_T * | dac, |
uint32_t | u32Delay | ||
) |
Set delay time for DAC to become stable.
[in] | dac | Base address of DAC module. |
[in] | u32Delay | Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. |
For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0.