M480 BSP
V3.05.005
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
i2c_reg.h
Go to the documentation of this file.
1
/**************************************************************************/
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#ifndef __I2C_REG_H__
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#define __I2C_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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26
typedef
struct
27
{
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29
1046
__IO uint32_t
CTL0
;
1047
__IO uint32_t
ADDR0
;
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__IO uint32_t
DAT
;
1049
__I uint32_t
STATUS0
;
1050
__IO uint32_t
CLKDIV
;
1051
__IO uint32_t
TOCTL
;
1052
__IO uint32_t
ADDR1
;
1053
__IO uint32_t
ADDR2
;
1054
__IO uint32_t
ADDR3
;
1055
__IO uint32_t
ADDRMSK0
;
1056
__IO uint32_t
ADDRMSK1
;
1057
__IO uint32_t
ADDRMSK2
;
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__IO uint32_t
ADDRMSK3
;
1060
__I uint32_t RESERVE0[2];
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__IO uint32_t
WKCTL
;
1063
__IO uint32_t
WKSTS
;
1064
__IO uint32_t
CTL1
;
1065
__IO uint32_t
STATUS1
;
1066
__IO uint32_t
TMCTL
;
1067
__IO uint32_t
BUSCTL
;
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__IO uint32_t
BUSTCTL
;
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__IO uint32_t
BUSSTS
;
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__IO uint32_t
PKTSIZE
;
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__I uint32_t
PKTCRC
;
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__IO uint32_t
BUSTOUT
;
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__IO uint32_t
CLKTOUT
;
1075
}
I2C_T
;
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#define I2C_CTL0_AA_Pos (2)
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#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos)
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#define I2C_CTL0_SI_Pos (3)
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#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos)
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#define I2C_CTL0_STO_Pos (4)
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#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos)
1091
#define I2C_CTL0_STA_Pos (5)
1092
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos)
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#define I2C_CTL0_I2CEN_Pos (6)
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#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos)
1097
#define I2C_CTL0_INTEN_Pos (7)
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#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos)
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#define I2C_ADDR0_GC_Pos (0)
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#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
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#define I2C_ADDR0_ADDR_Pos (1)
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#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos)
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#define I2C_DAT_DAT_Pos (0)
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#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
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#define I2C_STATUS0_STATUS_Pos (0)
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#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos)
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#define I2C_CLKDIV_DIVIDER_Pos (0)
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#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos)
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#define I2C_TOCTL_TOIF_Pos (0)
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#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
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#define I2C_TOCTL_TOCDIV4_Pos (1)
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#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
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#define I2C_TOCTL_TOCEN_Pos (2)
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#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
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#define I2C_ADDR1_GC_Pos (0)
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#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
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#define I2C_ADDR1_ADDR_Pos (1)
1128
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos)
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#define I2C_ADDR2_GC_Pos (0)
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#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
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#define I2C_ADDR2_ADDR_Pos (1)
1134
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos)
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#define I2C_ADDR3_GC_Pos (0)
1137
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
1139
#define I2C_ADDR3_ADDR_Pos (1)
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#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos)
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#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
1143
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos)
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#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
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#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos)
1148
#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
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#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos)
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#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
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#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos)
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#define I2C_WKCTL_WKEN_Pos (0)
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#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos)
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#define I2C_WKCTL_NHDBUSEN_Pos (7)
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#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos)
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#define I2C_WKSTS_WKIF_Pos (0)
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#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos)
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#define I2C_WKSTS_WKAKDONE_Pos (1)
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#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos)
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#define I2C_WKSTS_WRSTSWK_Pos (2)
1167
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos)
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#define I2C_CTL1_TXPDMAEN_Pos (0)
1170
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos)
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#define I2C_CTL1_RXPDMAEN_Pos (1)
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#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos)
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#define I2C_CTL1_PDMARST_Pos (2)
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#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos)
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#define I2C_CTL1_PDMASTR_Pos (8)
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#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos)
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#define I2C_CTL1_ADDR10EN_Pos (9)
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#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos)
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#define I2C_STATUS1_ADMAT0_Pos (0)
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#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos)
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#define I2C_STATUS1_ADMAT1_Pos (1)
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#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos)
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#define I2C_STATUS1_ADMAT2_Pos (2)
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#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos)
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#define I2C_STATUS1_ADMAT3_Pos (3)
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#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos)
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#define I2C_STATUS1_ONBUSY_Pos (8)
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#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos)
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#define I2C_TMCTL_STCTL_Pos (0)
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#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos)
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#define I2C_TMCTL_HTCTL_Pos (16)
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#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos)
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#define I2C_BUSCTL_ACKMEN_Pos (0)
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#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos)
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#define I2C_BUSCTL_PECEN_Pos (1)
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#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos)
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#define I2C_BUSCTL_BMDEN_Pos (2)
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#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos)
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#define I2C_BUSCTL_BMHEN_Pos (3)
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#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos)
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#define I2C_BUSCTL_ALERTEN_Pos (4)
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#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos)
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#define I2C_BUSCTL_SCTLOSTS_Pos (5)
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#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)
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#define I2C_BUSCTL_SCTLOEN_Pos (6)
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#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)
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#define I2C_BUSCTL_BUSEN_Pos (7)
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#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos)
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#define I2C_BUSCTL_PECTXEN_Pos (8)
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#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos)
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#define I2C_BUSCTL_TIDLE_Pos (9)
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#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos)
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#define I2C_BUSCTL_PECCLR_Pos (10)
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#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos)
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#define I2C_BUSCTL_ACKM9SI_Pos (11)
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#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)
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#define I2C_BUSCTL_BCDIEN_Pos (12)
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#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos)
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#define I2C_BUSCTL_PECDIEN_Pos (13)
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#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos)
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#define I2C_BUSTCTL_BUSTOEN_Pos (0)
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#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)
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#define I2C_BUSTCTL_CLKTOEN_Pos (1)
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#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)
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#define I2C_BUSTCTL_BUSTOIEN_Pos (2)
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#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)
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#define I2C_BUSTCTL_CLKTOIEN_Pos (3)
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#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)
1259
#define I2C_BUSTCTL_TORSTEN_Pos (4)
1260
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)
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#define I2C_BUSSTS_BUSY_Pos (0)
1263
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos)
1265
#define I2C_BUSSTS_BCDONE_Pos (1)
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#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos)
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#define I2C_BUSSTS_PECERR_Pos (2)
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#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos)
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#define I2C_BUSSTS_ALERT_Pos (3)
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#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos)
1274
#define I2C_BUSSTS_SCTLDIN_Pos (4)
1275
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)
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#define I2C_BUSSTS_BUSTO_Pos (5)
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#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos)
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#define I2C_BUSSTS_CLKTO_Pos (6)
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#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos)
1283
#define I2C_BUSSTS_PECDONE_Pos (7)
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#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos)
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#define I2C_PKTSIZE_PLDSIZE_Pos (0)
1287
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos)
1289
#define I2C_PKTCRC_PECCRC_Pos (0)
1290
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos)
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#define I2C_BUSTOUT_BUSTO_Pos (0)
1293
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos)
1295
#define I2C_CLKTOUT_CLKTO_Pos (0)
1296
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos)
/* I2C_CONST */
/* end of I2C register group */
/* end of REGISTER group */
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1302
#if defined ( __CC_ARM )
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#pragma no_anon_unions
1304
#endif
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#endif
/* __I2C_REG_H__ */
I2C_T
Definition:
i2c_reg.h:27
I2C_T::CLKTOUT
__IO uint32_t CLKTOUT
Definition:
i2c_reg.h:1073
I2C_T::ADDR2
__IO uint32_t ADDR2
Definition:
i2c_reg.h:1053
I2C_T::BUSTCTL
__IO uint32_t BUSTCTL
Definition:
i2c_reg.h:1068
I2C_T::ADDR3
__IO uint32_t ADDR3
Definition:
i2c_reg.h:1054
I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition:
i2c_reg.h:1056
I2C_T::ADDR0
__IO uint32_t ADDR0
Definition:
i2c_reg.h:1047
I2C_T::TOCTL
__IO uint32_t TOCTL
Definition:
i2c_reg.h:1051
I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition:
i2c_reg.h:1050
I2C_T::DAT
__IO uint32_t DAT
Definition:
i2c_reg.h:1048
I2C_T::PKTCRC
__I uint32_t PKTCRC
Definition:
i2c_reg.h:1071
I2C_T::ADDR1
__IO uint32_t ADDR1
Definition:
i2c_reg.h:1052
I2C_T::BUSTOUT
__IO uint32_t BUSTOUT
Definition:
i2c_reg.h:1072
I2C_T::STATUS1
__IO uint32_t STATUS1
Definition:
i2c_reg.h:1065
I2C_T::CTL0
__IO uint32_t CTL0
Definition:
i2c_reg.h:1046
I2C_T::ADDRMSK2
__IO uint32_t ADDRMSK2
Definition:
i2c_reg.h:1057
I2C_T::BUSSTS
__IO uint32_t BUSSTS
Definition:
i2c_reg.h:1069
I2C_T::TMCTL
__IO uint32_t TMCTL
Definition:
i2c_reg.h:1066
I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition:
i2c_reg.h:1055
I2C_T::BUSCTL
__IO uint32_t BUSCTL
Definition:
i2c_reg.h:1067
I2C_T::ADDRMSK3
__IO uint32_t ADDRMSK3
Definition:
i2c_reg.h:1058
I2C_T::CTL1
__IO uint32_t CTL1
Definition:
i2c_reg.h:1064
I2C_T::PKTSIZE
__IO uint32_t PKTSIZE
Definition:
i2c_reg.h:1070
I2C_T::STATUS0
__I uint32_t STATUS0
Definition:
i2c_reg.h:1049
I2C_T::WKSTS
__IO uint32_t WKSTS
Definition:
i2c_reg.h:1063
I2C_T::WKCTL
__IO uint32_t WKCTL
Definition:
i2c_reg.h:1062
Generated on Thu Mar 16 2023 13:35:48 for M480 BSP by
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