M480 BSP V3.05.005
The Board Support Package for M480 Series
i2s.h
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1/****************************************************************************/
9#ifndef __I2S_H__
10#define __I2S_H__
11
12#ifdef __cplusplus
13extern "C"
14{
15#endif
16
28#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos)
29#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos)
30#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos)
31#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos)
33/* Audio Format */
34#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk
35#define I2S_DISABLE_MONO (0U)
37/* I2S Data Format */
38#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos)
39#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos)
40#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos)
41#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos)
42#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos)
43#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos)
45/* I2S Data Format */
46#define I2S_ORDER_AT_MSB (0U)
47#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk
49/* I2S TDM Channel Number */
50#define I2S_TDM_2CH 0U
51#define I2S_TDM_4CH 1U
52#define I2S_TDM_6CH 2U
53#define I2S_TDM_8CH 3U
55/* I2S TDM Channel Width */
56#define I2S_TDM_WIDTH_8BIT 0U
57#define I2S_TDM_WIDTH_16BIT 1U
58#define I2S_TDM_WIDTH_24BIT 2U
59#define I2S_TDM_WIDTH_32BIT 3U
61/* I2S TDM Sync Width */
62#define I2S_TDM_SYNC_ONE_BCLK 0U
63#define I2S_TDM_SYNC_ONE_CHANNEL 1U
65/* I2S Operation mode */
66#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk
67#define I2S_MODE_MASTER (0u)
69/* I2S FIFO Threshold */
70#define I2S_FIFO_TX_LEVEL_WORD_0 (0U)
71#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos)
72#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos)
73#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos)
74#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos)
75#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos)
76#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos)
77#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos)
78#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos)
79#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos)
80#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos)
81#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos)
82#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos)
83#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos)
84#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos)
85#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos)
87#define I2S_FIFO_RX_LEVEL_WORD_1 (0U)
88#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos)
89#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos)
90#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos)
91#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos)
92#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos)
93#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos)
94#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos)
95#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos)
96#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos)
97#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos)
98#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos)
99#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos)
100#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos)
101#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos)
102#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos)
104/* I2S Record Channel */
105#define I2S_MONO_RIGHT (0U)
106#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk
108/* I2S Channel */
109#define I2S_RIGHT (0U)
110#define I2S_LEFT (1U) /* end of group I2S_EXPORTED_CONSTANTS */
113
117/*---------------------------------------------------------------------------------------------------------*/
118/* inline functions */
119/*---------------------------------------------------------------------------------------------------------*/
127__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
128{
129 if((u32ChMask > 0U) && (u32ChMask < 9U))
130 {
131 i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
132 }
133}
134
142__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
143{
144 if((u32ChMask > 0U) && (u32ChMask < 9U))
145 {
146 i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
147 }
148}
149
156#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
157
164#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
165
172#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
173
180#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
181
188#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
189
196#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
197
204#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
205
212#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
213
220#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
221
228#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
229
236#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
237
244#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
245
255__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
256{
257 u32Ch == I2S_MONO_LEFT ?
258 (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
259 (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
260}
261
269#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
270
277#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
278
286#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
287
295#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
296
304#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
305
313#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
314
321#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
322
329#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
330
331void I2S_Close(I2S_T *i2s);
332void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
333void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
334uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
335void I2S_DisableMCLK(I2S_T *i2s);
336void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
337void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
338uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
339 /* end of group I2S_EXPORTED_FUNCTIONS */
341
342 /* end of group I2S_Driver */
344 /* end of group Standard_Driver */
346#ifdef __cplusplus
347}
348#endif
349
350#endif
351
352/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
353
#define I2S_MONO_LEFT
Definition: i2s.h:106
__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
This function sets the recording source channel when mono mode is used.
Definition: i2s.h:255
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width.
Definition: i2s.c:236
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
This function configures some parameters of I2S interface for general purpose use....
Definition: i2s.c:91
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: i2s.c:209
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
This function disables the interrupt according to the mask parameter.
Definition: i2s.c:147
void I2S_DisableMCLK(I2S_T *i2s)
Disable MCLK .
Definition: i2s.c:196
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
Enable MCLK .
Definition: i2s.c:158
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
This function enables the interrupt according to the mask parameter.
Definition: i2s.c:135
__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
Enable zero cross detect function.
Definition: i2s.h:127
__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
Disable zero cross detect function.
Definition: i2s.h:142
void I2S_Close(I2S_T *i2s)
Disable I2S function and I2S clock.
Definition: i2s.c:123
#define I2S_CTL0_RXLCH_Msk
Definition: i2s_reg.h:1047
Definition: i2s_reg.h:27
__IO uint32_t CTL1
Definition: i2s_reg.h:997
__IO uint32_t CTL0
Definition: i2s_reg.h:988