M480 BSP V3.05.005
The Board Support Package for M480 Series
Data Fields
CRC_T Struct Reference

#include <crc_reg.h>

Data Fields

__IO uint32_t CTL
 
__IO uint32_t DAT
 
__IO uint32_t SEED
 
__I uint32_t CHECKSUM
 

Detailed Description

@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller

Definition at line 26 of file crc_reg.h.

Field Documentation

◆ CHECKSUM

CRC_T::CHECKSUM

[0x000c] CRC Checksum Register

CHECKSUM

Offset: 0x0C CRC Checksum Register

BitsFieldDescriptions
[31:0]CHECKSUM
CRC Checksum Results
This field indicates the CRC checksum result.

Definition at line 189 of file crc_reg.h.

◆ CTL

CRC_T::CTL

[0x0000] CRC Control Register

CTL

Offset: 0x00 CRC Control Register

BitsFieldDescriptions
[0]CRCEN
CRC Channel Enable Bit
0 = No effect.
1 = CRC operation Enabled.
[1]CHKSINIT
Checksum Initialization
0 = No effect.
1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
Note: This bit will be cleared automatically.
[24]DATREV
Write Data Bit Order Reverse
This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
0 = Bit order reversed for CRC write data in Disabled.
1 = Bit order reversed for CRC write data in Enabled (per byte).
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
[25]CHKSREV
Checksum Bit Order Reverse
This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
0 = Bit order reverse for CRC checksum Disabled.
1 = Bit order reverse for CRC checksum Enabled.
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
[26]DATFMT
Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
0 = 1's complement for CRC writes data in Disabled.
1 = 1's complement for CRC writes data in Enabled.
[27]CHKSFMT
Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
0 = 1's complement for CRC checksum Disabled.
1 = 1's complement for CRC checksum Enabled.
[29:28]DATLEN
CPU Write Data Length
This field indicates the write data length.
00 = Data length is 8-bit mode.
01 = Data length is 16-bit mode.
1x = Data length is 32-bit mode.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
[31:30]CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
00 = CRC-CCITT Polynomial mode.
01 = CRC-8 Polynomial mode.
10 = CRC-16 Polynomial mode.
11 = CRC-32 Polynomial mode.

Definition at line 186 of file crc_reg.h.

◆ DAT

CRC_T::DAT

[0x0004] CRC Write Data Register

DAT

Offset: 0x04 CRC Write Data Register

BitsFieldDescriptions
[31:0]DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].

Definition at line 187 of file crc_reg.h.

◆ SEED

CRC_T::SEED

[0x0008] CRC Seed Register

SEED

Offset: 0x08 CRC Seed Register

BitsFieldDescriptions
[31:0]SEED
CRC Seed Value
This field indicates the CRC seed value.
Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).

Definition at line 188 of file crc_reg.h.


The documentation for this struct was generated from the following file: