M480 BSP V3.05.005
The Board Support Package for M480 Series
Macros | Functions | Variables
clk.h File Reference

M480 Series CLK Driver Header File. More...

Go to the source code of this file.

Macros

#define FREQ_25MHZ
 
#define FREQ_50MHZ
 
#define FREQ_72MHZ
 
#define FREQ_80MHZ
 
#define FREQ_100MHZ
 
#define FREQ_125MHZ
 
#define FREQ_160MHZ
 
#define FREQ_192MHZ
 
#define FREQ_200MHZ
 
#define FREQ_250MHZ
 
#define FREQ_500MHZ
 
#define CLK_CLKSEL0_HCLKSEL_HXT
 
#define CLK_CLKSEL0_HCLKSEL_LXT
 
#define CLK_CLKSEL0_HCLKSEL_PLL
 
#define CLK_CLKSEL0_HCLKSEL_LIRC
 
#define CLK_CLKSEL0_HCLKSEL_HIRC
 
#define CLK_CLKSEL0_STCLKSEL_HXT
 
#define CLK_CLKSEL0_STCLKSEL_LXT
 
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HCLK
 
#define CLK_CLKSEL0_CCAPSEL_HXT   (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_PLL   (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_HCLK   (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_HIRC   (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_HXT   (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_PLL   (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_HIRC   (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_CCAPSEL_HCLK   (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)
 
#define CLK_CLKSEL0_SDH0SEL_HXT
 
#define CLK_CLKSEL0_SDH0SEL_PLL
 
#define CLK_CLKSEL0_SDH0SEL_HIRC
 
#define CLK_CLKSEL0_SDH0SEL_HCLK
 
#define CLK_CLKSEL0_SDH1SEL_HXT
 
#define CLK_CLKSEL0_SDH1SEL_PLL
 
#define CLK_CLKSEL0_SDH1SEL_HIRC
 
#define CLK_CLKSEL0_SDH1SEL_HCLK
 
#define CLK_CLKSEL0_USBSEL_RC48M
 
#define CLK_CLKSEL0_USBSEL_PLL
 
#define CLK_CLKSEL1_WDTSEL_LXT
 
#define CLK_CLKSEL1_WDTSEL_LIRC
 
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048
 
#define CLK_CLKSEL1_TMR0SEL_HXT
 
#define CLK_CLKSEL1_TMR0SEL_LXT
 
#define CLK_CLKSEL1_TMR0SEL_LIRC
 
#define CLK_CLKSEL1_TMR0SEL_HIRC
 
#define CLK_CLKSEL1_TMR0SEL_PCLK0
 
#define CLK_CLKSEL1_TMR0SEL_EXT
 
#define CLK_CLKSEL1_TMR1SEL_HXT
 
#define CLK_CLKSEL1_TMR1SEL_LXT
 
#define CLK_CLKSEL1_TMR1SEL_LIRC
 
#define CLK_CLKSEL1_TMR1SEL_HIRC
 
#define CLK_CLKSEL1_TMR1SEL_PCLK0
 
#define CLK_CLKSEL1_TMR1SEL_EXT
 
#define CLK_CLKSEL1_TMR2SEL_HXT
 
#define CLK_CLKSEL1_TMR2SEL_LXT
 
#define CLK_CLKSEL1_TMR2SEL_LIRC
 
#define CLK_CLKSEL1_TMR2SEL_HIRC
 
#define CLK_CLKSEL1_TMR2SEL_PCLK1
 
#define CLK_CLKSEL1_TMR2SEL_EXT
 
#define CLK_CLKSEL1_TMR3SEL_HXT
 
#define CLK_CLKSEL1_TMR3SEL_LXT
 
#define CLK_CLKSEL1_TMR3SEL_LIRC
 
#define CLK_CLKSEL1_TMR3SEL_HIRC
 
#define CLK_CLKSEL1_TMR3SEL_PCLK1
 
#define CLK_CLKSEL1_TMR3SEL_EXT
 
#define CLK_CLKSEL1_UART0SEL_HXT
 
#define CLK_CLKSEL1_UART0SEL_LXT
 
#define CLK_CLKSEL1_UART0SEL_PLL
 
#define CLK_CLKSEL1_UART0SEL_HIRC
 
#define CLK_CLKSEL1_UART1SEL_HXT
 
#define CLK_CLKSEL1_UART1SEL_LXT
 
#define CLK_CLKSEL1_UART1SEL_PLL
 
#define CLK_CLKSEL1_UART1SEL_HIRC
 
#define CLK_CLKSEL1_CLKOSEL_HXT
 
#define CLK_CLKSEL1_CLKOSEL_LXT
 
#define CLK_CLKSEL1_CLKOSEL_HIRC
 
#define CLK_CLKSEL1_CLKOSEL_HCLK
 
#define CLK_CLKSEL1_WWDTSEL_LIRC
 
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048
 
#define CLK_CLKSEL2_QSPI0SEL_HXT
 
#define CLK_CLKSEL2_QSPI0SEL_PLL
 
#define CLK_CLKSEL2_QSPI0SEL_HIRC
 
#define CLK_CLKSEL2_QSPI0SEL_PCLK0
 
#define CLK_CLKSEL2_SPI0SEL_HXT
 
#define CLK_CLKSEL2_SPI0SEL_PLL
 
#define CLK_CLKSEL2_SPI0SEL_HIRC
 
#define CLK_CLKSEL2_SPI0SEL_PCLK1
 
#define CLK_CLKSEL2_SPI1SEL_HXT
 
#define CLK_CLKSEL2_SPI1SEL_PLL
 
#define CLK_CLKSEL2_SPI1SEL_HIRC
 
#define CLK_CLKSEL2_SPI1SEL_PCLK0
 
#define CLK_CLKSEL2_EPWM0SEL_PLL
 
#define CLK_CLKSEL2_EPWM0SEL_PCLK0
 
#define CLK_CLKSEL2_EPWM1SEL_PLL
 
#define CLK_CLKSEL2_EPWM1SEL_PCLK1
 
#define CLK_CLKSEL2_BPWM0SEL_PLL
 
#define CLK_CLKSEL2_BPWM0SEL_PCLK0
 
#define CLK_CLKSEL2_BPWM1SEL_PLL
 
#define CLK_CLKSEL2_BPWM1SEL_PCLK1
 
#define CLK_CLKSEL2_SPI2SEL_HXT
 
#define CLK_CLKSEL2_SPI2SEL_PLL
 
#define CLK_CLKSEL2_SPI2SEL_HIRC
 
#define CLK_CLKSEL2_SPI2SEL_PCLK1
 
#define CLK_CLKSEL2_SPI3SEL_HXT
 
#define CLK_CLKSEL2_SPI3SEL_PLL
 
#define CLK_CLKSEL2_SPI3SEL_HIRC
 
#define CLK_CLKSEL2_SPI3SEL_PCLK0
 
#define CLK_CLKSEL3_SC0SEL_HXT
 
#define CLK_CLKSEL3_SC0SEL_PLL
 
#define CLK_CLKSEL3_SC0SEL_HIRC
 
#define CLK_CLKSEL3_SC0SEL_PCLK0
 
#define CLK_CLKSEL3_SC1SEL_HXT
 
#define CLK_CLKSEL3_SC1SEL_PLL
 
#define CLK_CLKSEL3_SC1SEL_HIRC
 
#define CLK_CLKSEL3_SC1SEL_PCLK1
 
#define CLK_CLKSEL3_SC2SEL_HXT
 
#define CLK_CLKSEL3_SC2SEL_PLL
 
#define CLK_CLKSEL3_SC2SEL_HIRC
 
#define CLK_CLKSEL3_SC2SEL_PCLK0
 
#define CLK_CLKSEL3_RTCSEL_LXT
 
#define CLK_CLKSEL3_RTCSEL_LIRC
 
#define CLK_CLKSEL3_QSPI1SEL_HXT
 
#define CLK_CLKSEL3_QSPI1SEL_PLL
 
#define CLK_CLKSEL3_QSPI1SEL_HIRC
 
#define CLK_CLKSEL3_QSPI1SEL_PCLK1
 
#define CLK_CLKSEL3_I2S0SEL_HXT
 
#define CLK_CLKSEL3_I2S0SEL_PLL
 
#define CLK_CLKSEL3_I2S0SEL_HIRC
 
#define CLK_CLKSEL3_I2S0SEL_PCLK0
 
#define CLK_CLKSEL3_UART2SEL_HXT
 
#define CLK_CLKSEL3_UART2SEL_LXT
 
#define CLK_CLKSEL3_UART2SEL_PLL
 
#define CLK_CLKSEL3_UART2SEL_HIRC
 
#define CLK_CLKSEL3_UART3SEL_HXT
 
#define CLK_CLKSEL3_UART3SEL_LXT
 
#define CLK_CLKSEL3_UART3SEL_PLL
 
#define CLK_CLKSEL3_UART3SEL_HIRC
 
#define CLK_CLKSEL3_UART4SEL_HXT
 
#define CLK_CLKSEL3_UART4SEL_LXT
 
#define CLK_CLKSEL3_UART4SEL_PLL
 
#define CLK_CLKSEL3_UART4SEL_HIRC
 
#define CLK_CLKSEL3_UART5SEL_HXT
 
#define CLK_CLKSEL3_UART5SEL_LXT
 
#define CLK_CLKSEL3_UART5SEL_PLL
 
#define CLK_CLKSEL3_UART5SEL_HIRC
 
#define CLK_CLKSEL3_UART6SEL_HXT
 
#define CLK_CLKSEL3_UART6SEL_LXT
 
#define CLK_CLKSEL3_UART6SEL_PLL
 
#define CLK_CLKSEL3_UART6SEL_HIRC
 
#define CLK_CLKSEL3_UART7SEL_HXT
 
#define CLK_CLKSEL3_UART7SEL_LXT
 
#define CLK_CLKSEL3_UART7SEL_PLL
 
#define CLK_CLKSEL3_UART7SEL_HIRC
 
#define CLK_CLKDIV0_HCLK(x)
 
#define CLK_CLKDIV0_USB(x)
 
#define CLK_CLKDIV0_SDH0(x)
 
#define CLK_CLKDIV0_UART0(x)
 
#define CLK_CLKDIV0_UART1(x)
 
#define CLK_CLKDIV0_EADC(x)
 
#define CLK_CLKDIV1_SC0(x)
 
#define CLK_CLKDIV1_SC1(x)
 
#define CLK_CLKDIV1_SC2(x)
 
#define CLK_CLKDIV2_I2S0(x)   (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos)
 
#define CLK_CLKDIV2_EADC1(x)   (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos)
 
#define CLK_CLKDIV3_CCAP(x)   (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos)
 
#define CLK_CLKDIV3_VSENSE(x)   (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos)
 
#define CLK_CLKDIV3_EMAC(x)
 
#define CLK_CLKDIV3_SDH1(x)
 
#define CLK_CLKDIV4_UART2(x)
 
#define CLK_CLKDIV4_UART3(x)
 
#define CLK_CLKDIV4_UART4(x)
 
#define CLK_CLKDIV4_UART5(x)
 
#define CLK_CLKDIV4_UART6(x)   (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos)
 
#define CLK_CLKDIV4_UART7(x)   (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos)
 
#define CLK_PCLKDIV_PCLK0DIV1
 
#define CLK_PCLKDIV_PCLK0DIV2
 
#define CLK_PCLKDIV_PCLK0DIV4
 
#define CLK_PCLKDIV_PCLK0DIV8
 
#define CLK_PCLKDIV_PCLK0DIV16
 
#define CLK_PCLKDIV_PCLK1DIV1
 
#define CLK_PCLKDIV_PCLK1DIV2
 
#define CLK_PCLKDIV_PCLK1DIV4
 
#define CLK_PCLKDIV_PCLK1DIV8
 
#define CLK_PCLKDIV_PCLK1DIV16
 
#define CLK_PCLKDIV_APB0DIV_DIV1
 
#define CLK_PCLKDIV_APB0DIV_DIV2
 
#define CLK_PCLKDIV_APB0DIV_DIV4
 
#define CLK_PCLKDIV_APB0DIV_DIV8
 
#define CLK_PCLKDIV_APB0DIV_DIV16
 
#define CLK_PCLKDIV_APB1DIV_DIV1
 
#define CLK_PCLKDIV_APB1DIV_DIV2
 
#define CLK_PCLKDIV_APB1DIV_DIV4
 
#define CLK_PCLKDIV_APB1DIV_DIV8
 
#define CLK_PCLKDIV_APB1DIV_DIV16
 
#define CLK_PLLCTL_PLLSRC_HXT
 
#define CLK_PLLCTL_PLLSRC_HIRC
 
#define CLK_PLLCTL_NF(x)
 
#define CLK_PLLCTL_NR(x)
 
#define CLK_PLLCTL_NO_1
 
#define CLK_PLLCTL_NO_2
 
#define CLK_PLLCTL_NO_4
 
#define CLK_PLLCTL_72MHz_HXT
 
#define CLK_PLLCTL_80MHz_HXT
 
#define CLK_PLLCTL_144MHz_HXT
 
#define CLK_PLLCTL_160MHz_HXT
 
#define CLK_PLLCTL_192MHz_HXT
 
#define CLK_PLLCTL_72MHz_HIRC
 
#define CLK_PLLCTL_80MHz_HIRC
 
#define CLK_PLLCTL_144MHz_HIRC
 
#define CLK_PLLCTL_160MHz_HIRC
 
#define CLK_PLLCTL_192MHz_HIRC
 
#define MODULE_APBCLK(x)
 
#define MODULE_CLKSEL(x)
 
#define MODULE_CLKSEL_Msk(x)
 
#define MODULE_CLKSEL_Pos(x)
 
#define MODULE_CLKDIV(x)
 
#define MODULE_CLKDIV_Msk(x)
 
#define MODULE_CLKDIV_Pos(x)
 
#define MODULE_IP_EN_Pos(x)
 
#define MODULE_NoMsk
 
#define NA
 
#define MODULE_APBCLK_ENC(x)
 
#define MODULE_CLKSEL_ENC(x)
 
#define MODULE_CLKSEL_Msk_ENC(x)
 
#define MODULE_CLKSEL_Pos_ENC(x)
 
#define MODULE_CLKDIV_ENC(x)
 
#define MODULE_CLKDIV_Msk_ENC(x)
 
#define MODULE_CLKDIV_Pos_ENC(x)
 
#define MODULE_IP_EN_Pos_ENC(x)
 
#define PDMA_MODULE
 
#define ISP_MODULE
 
#define EBI_MODULE
 
#define USBH_MODULE
 
#define EMAC_MODULE
 
#define SDH0_MODULE
 
#define CRC_MODULE
 
#define CCAP_MODULE
 
#define SEN_MODULE
 
#define HSUSBD_MODULE
 
#define CRPT_MODULE
 
#define SPIM_MODULE
 
#define FMCIDLE_MODULE
 
#define SDH1_MODULE
 
#define WDT_MODULE
 
#define RTC_MODULE
 
#define TMR0_MODULE
 
#define TMR1_MODULE
 
#define TMR2_MODULE
 
#define TMR3_MODULE
 
#define CLKO_MODULE
 
#define WWDT_MODULE
 
#define ACMP01_MODULE
 
#define I2C0_MODULE
 
#define I2C1_MODULE
 
#define I2C2_MODULE
 
#define QSPI0_MODULE
 
#define SPI0_MODULE
 
#define SPI1_MODULE
 
#define SPI2_MODULE
 
#define UART0_MODULE
 
#define UART1_MODULE
 
#define UART2_MODULE
 
#define UART3_MODULE
 
#define UART4_MODULE
 
#define UART5_MODULE
 
#define UART6_MODULE
 
#define UART7_MODULE
 
#define CAN0_MODULE
 
#define CAN1_MODULE
 
#define OTG_MODULE
 
#define USBD_MODULE
 
#define EADC_MODULE
 
#define I2S0_MODULE
 
#define HSOTG_MODULE
 
#define SC0_MODULE
 
#define SC1_MODULE
 
#define SC2_MODULE
 
#define QSPI1_MODULE
 
#define SPI3_MODULE
 
#define USCI0_MODULE
 
#define USCI1_MODULE
 
#define DAC_MODULE
 
#define CAN2_MODULE
 
#define EPWM0_MODULE
 
#define EPWM1_MODULE
 
#define BPWM0_MODULE
 
#define BPWM1_MODULE
 
#define QEI0_MODULE
 
#define QEI1_MODULE
 
#define TRNG_MODULE
 
#define ECAP0_MODULE
 
#define ECAP1_MODULE
 
#define OPA_MODULE
 
#define EADC1_MODULE
 
#define CLK_PMUCTL_PDMSEL_PD
 
#define CLK_PMUCTL_PDMSEL_LLPD
 
#define CLK_PMUCTL_PDMSEL_FWPD
 
#define CLK_PMUCTL_PDMSEL_SPD0
 
#define CLK_PMUCTL_PDMSEL_SPD1
 
#define CLK_PMUCTL_PDMSEL_DPD
 
#define CLK_PMUCTL_WKTMRIS_128
 
#define CLK_PMUCTL_WKTMRIS_256
 
#define CLK_PMUCTL_WKTMRIS_512
 
#define CLK_PMUCTL_WKTMRIS_1024
 
#define CLK_PMUCTL_WKTMRIS_4096
 
#define CLK_PMUCTL_WKTMRIS_8192
 
#define CLK_PMUCTL_WKTMRIS_16384
 
#define CLK_PMUCTL_WKTMRIS_65536
 
#define CLK_PMUCTL_WKTMRIS_131072
 
#define CLK_PMUCTL_WKTMRIS_262144
 
#define CLK_PMUCTL_WKTMRIS_524288
 
#define CLK_PMUCTL_WKTMRIS_1048576
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_1
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_2
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_4
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_8
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_16
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_32
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_64
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_128
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256
 
#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256
 
#define CLK_DPDWKPIN_DISABLE
 
#define CLK_DPDWKPIN_RISING
 
#define CLK_DPDWKPIN_FALLING
 
#define CLK_DPDWKPIN_BOTHEDGE
 
#define CLK_DPDWKPIN0_DISABLE
 
#define CLK_DPDWKPIN0_RISING
 
#define CLK_DPDWKPIN0_FALLING
 
#define CLK_DPDWKPIN0_BOTHEDGE
 
#define CLK_DPDWKPIN1_DISABLE
 
#define CLK_DPDWKPIN1_RISING
 
#define CLK_DPDWKPIN1_FALLING
 
#define CLK_DPDWKPIN1_BOTHEDGE
 
#define CLK_DPDWKPIN2_DISABLE
 
#define CLK_DPDWKPIN2_RISING
 
#define CLK_DPDWKPIN2_FALLING
 
#define CLK_DPDWKPIN2_BOTHEDGE
 
#define CLK_DPDWKPIN3_DISABLE
 
#define CLK_DPDWKPIN3_RISING
 
#define CLK_DPDWKPIN3_FALLING
 
#define CLK_DPDWKPIN3_BOTHEDGE
 
#define CLK_DPDWKPIN4_DISABLE
 
#define CLK_DPDWKPIN4_RISING
 
#define CLK_DPDWKPIN4_FALLING
 
#define CLK_DPDWKPIN4_BOTHEDGE
 
#define CLK_SPDWKPIN_ENABLE
 
#define CLK_SPDWKPIN_RISING
 
#define CLK_SPDWKPIN_FALLING
 
#define CLK_SPDWKPIN_DEBOUNCEEN
 
#define CLK_SPDWKPIN_DEBOUNCEDIS
 
#define CLK_SPDSRETSEL_NO
 
#define CLK_SPDSRETSEL_16K
 
#define CLK_SPDSRETSEL_32K
 
#define CLK_SPDSRETSEL_64K
 
#define CLK_SPDSRETSEL_128K
 
#define CLK_DISABLE_WKTMR(void)
 
#define CLK_ENABLE_WKTMR(void)
 
#define CLK_DISABLE_DPDWKPIN(void)
 
#define CLK_DISABLE_DPDWKPIN0(void)
 
#define CLK_DISABLE_DPDWKPIN1(void)
 
#define CLK_DISABLE_DPDWKPIN2(void)
 
#define CLK_DISABLE_DPDWKPIN3(void)
 
#define CLK_DISABLE_DPDWKPIN4(void)
 
#define CLK_DISABLE_SPDACMP(void)
 
#define CLK_ENABLE_SPDACMP(void)
 
#define CLK_DISABLE_RTCWK(void)
 
#define CLK_ENABLE_RTCWK(void)
 
#define CLK_TIMEOUT_ERR
 
#define CLK_SET_WKTMR_INTERVAL(u32Interval)
 Set Wake-up Timer Time-out Interval. More...
 
#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel)
 Set De-bounce Sampling Cycle Time. More...
 

Functions

__STATIC_INLINE void CLK_SysTickDelay (uint32_t us)
 This function execute delay function. More...
 
__STATIC_INLINE void CLK_SysTickLongDelay (uint32_t us)
 This function execute long delay function. More...
 
void CLK_DisableCKO (void)
 Disable clock divider output function. More...
 
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable clock divider output module clock, enable clock divider output function and set frequency selection. More...
 
void CLK_PowerDown (void)
 Enter to Power-down mode. More...
 
void CLK_Idle (void)
 Enter to Idle mode. More...
 
uint32_t CLK_GetHXTFreq (void)
 Get external high speed crystal clock frequency. More...
 
uint32_t CLK_GetLXTFreq (void)
 Get external low speed crystal clock frequency. More...
 
uint32_t CLK_GetHCLKFreq (void)
 Get HCLK frequency. More...
 
uint32_t CLK_GetPCLK0Freq (void)
 Get PCLK0 frequency. More...
 
uint32_t CLK_GetPCLK1Freq (void)
 Get PCLK1 frequency. More...
 
uint32_t CLK_GetCPUFreq (void)
 Get CPU frequency. More...
 
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 Set HCLK frequency. More...
 
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider. More...
 
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider. More...
 
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 Set SysTick clock source. More...
 
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 Enable clock source. More...
 
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 Disable clock source. More...
 
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 Enable module clock. More...
 
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 Disable module clock. More...
 
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 Set PLL frequency. More...
 
void CLK_DisablePLL (void)
 Disable PLL. More...
 
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status. More...
 
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter. More...
 
void CLK_DisableSysTick (void)
 Disable System Tick counter. More...
 
void CLK_SetPowerDownMode (uint32_t u32PDMode)
 Power-down mode selected. More...
 
void CLK_EnableDPDWKPin (uint32_t u32TriggerType)
 Set Wake-up pin trigger type at Deep Power down mode. More...
 
uint32_t CLK_GetPMUWKSrc (void)
 Get power manager wake up source. More...
 
void CLK_EnableSPDWKPin (uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
 Set specified GPIO as wake up source at Stand-by Power down mode. More...
 
uint32_t CLK_GetPLLClockFreq (void)
 Get PLL clock frequency. More...
 
uint32_t CLK_GetModuleClockSource (uint32_t u32ModuleIdx)
 Get selected module clock source. More...
 
uint32_t CLK_GetModuleClockDivider (uint32_t u32ModuleIdx)
 Get selected module clock divider number. More...
 

Variables

int32_t g_CLK_i32ErrCode
 

Detailed Description

M480 Series CLK Driver Header File.

Version
V1.0

SPDX-License-Identifier: Apache-2.0

Definition in file clk.h.