M480 BSP V3.05.005
The Board Support Package for M480 Series
Data Fields
TRNG_T Struct Reference

#include <trng_reg.h>

Data Fields

__IO uint32_t CTL
 
__I uint32_t DATA
 
__IO uint32_t ACT
 

Detailed Description

@addtogroup TRNG True Random Number Generator(TRNG)
Memory Mapped Structure for TRNG Controller

Definition at line 24 of file trng_reg.h.

Field Documentation

◆ ACT

TRNG_T::ACT

[0x000c] TRNG Activation Register

ACT

Offset: 0x0C TRNG Activation Register

BitsFieldDescriptions
[6:0]VER
TRNG Version
TRNG version number is dependent on TRNG module.
0x02:(Current Version Number)
[7]ACT
Random Number Generator Activation
After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
0 = TRNG inactive.
1 = TRNG active.
Note: ACT is an enable bit of analog part
When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.

Definition at line 178 of file trng_reg.h.

◆ CTL

TRNG_T::CTL

[0x0000] TRNG Control Register and Status

CTL

Offset: 0x00 TRNG Control Register and Status

BitsFieldDescriptions
[0]TRNGEN
Random Number Generator Enable Bit
This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.
0 = TRNG disabled.
1 = TRNG enabled.
Note: TRNGEN is an enable bit of digital part
When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
[1]DVIF
Data Valid (Read Only)
0 = Data is not valid. Reading from RNGD returns 0x00000000.
1 = Data is valid. A valid random number can be read form RNGD.
This bit is cleared to u20180u2019 by read TRNG_DATA.
[5:2]CLKP
Clock Prescaler
The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)
To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.
0000 = 80 ~ 100 MHz.
0001 = 60 ~ 80 MHz.
0010 = 50 ~60 MHz.
0011 = 40 ~50 MHz.
0100 = 30 ~40 MHz.
0101 = 25 ~30 MHz.
0110 = 20 ~25 MHz.
0111 = 15 ~20 MHz.
1000 = 12 ~15 MHz.
1001 = 9 ~12 MHz.
1010 = 7 ~9 MHz.
1011 = 6 ~7 MHz.
1100 = 5 ~6 MHz.
1101 = 4 ~5 MHz.
1111 = Reserved.
[6]DVIEN
Data Valid Interrupt Enable Bit
0 = Interrupt disabled..
1 = Interrupt enabled.
[7]READY
Random Number Generator Ready (Read Only)
After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
0 = RNG is not ready or was not activated.
1 = RNG is ready to be enabled..
[31:8]Reversed
Reversed

Definition at line 173 of file trng_reg.h.

◆ DATA

TRNG_T::DATA

[0x0004] TRNG Data Register

DATA

Offset: 0x04 TRNG Data Register

BitsFieldDescriptions
[7:0]DATA
Random Number Generator Data (Read Only)
The DATA store the random number generated by TRNG and can be read only once.

Definition at line 174 of file trng_reg.h.


The documentation for this struct was generated from the following file: