M480 BSP V3.05.005
The Board Support Package for M480 Series
clk_reg.h
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1/**************************************************************************/
9#ifndef __CLK_REG_H__
10#define __CLK_REG_H__
11
12#if defined ( __CC_ARM )
13#pragma anon_unions
14#endif
15
26typedef struct
27{
28
29
2223 __IO uint32_t PWRCTL;
2224 __IO uint32_t AHBCLK;
2225 __IO uint32_t APBCLK0;
2226 __IO uint32_t APBCLK1;
2227 __IO uint32_t CLKSEL0;
2228 __IO uint32_t CLKSEL1;
2229 __IO uint32_t CLKSEL2;
2230 __IO uint32_t CLKSEL3;
2231 __IO uint32_t CLKDIV0;
2232 __IO uint32_t CLKDIV1;
2233 __IO uint32_t CLKDIV2;
2234 __IO uint32_t CLKDIV3;
2235 __IO uint32_t CLKDIV4;
2236 __IO uint32_t PCLKDIV;
2238 __I uint32_t RESERVE1[2];
2240 __IO uint32_t PLLCTL;
2242 __I uint32_t RESERVE2[3];
2244 __I uint32_t STATUS;
2246 __I uint32_t RESERVE3[3];
2248 __IO uint32_t CLKOCTL;
2250 __I uint32_t RESERVE4[3];
2252 __IO uint32_t CLKDCTL;
2253 __IO uint32_t CLKDSTS;
2254 __IO uint32_t CDUPB;
2255 __IO uint32_t CDLOWB;
2257 __I uint32_t RESERVE5[4];
2259 __IO uint32_t PMUCTL;
2260 __IO uint32_t PMUSTS;
2261 __IO uint32_t LDOCTL;
2262 __IO uint32_t SWKDBCTL;
2263 __IO uint32_t PASWKCTL;
2264 __IO uint32_t PBSWKCTL;
2265 __IO uint32_t PCSWKCTL;
2266 __IO uint32_t PDSWKCTL;
2267 __IO uint32_t IOPDCTL;
2269} CLK_T;
2270
2276#define CLK_PWRCTL_HXTEN_Pos (0)
2277#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
2279#define CLK_PWRCTL_LXTEN_Pos (1)
2280#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
2282#define CLK_PWRCTL_HIRCEN_Pos (2)
2283#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
2285#define CLK_PWRCTL_LIRCEN_Pos (3)
2286#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
2288#define CLK_PWRCTL_PDWKDLY_Pos (4)
2289#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
2291#define CLK_PWRCTL_PDWKIEN_Pos (5)
2292#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
2294#define CLK_PWRCTL_PDWKIF_Pos (6)
2295#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
2297#define CLK_PWRCTL_PDEN_Pos (7)
2298#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
2300#define CLK_PWRCTL_HXTGAIN_Pos (10)
2301#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)
2303#define CLK_PWRCTL_HXTSELTYP_Pos (12)
2304#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)
2306#define CLK_PWRCTL_HXTTBEN_Pos (13)
2307#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos)
2309#define CLK_PWRCTL_HIRCSTBS_Pos (16)
2310#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos)
2312#define CLK_PWRCTL_HIRC48MEN_Pos (18)
2313#define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos)
2315#define CLK_AHBCLK_PDMACKEN_Pos (1)
2316#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
2318#define CLK_AHBCLK_ISPCKEN_Pos (2)
2319#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
2321#define CLK_AHBCLK_EBICKEN_Pos (3)
2322#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos)
2324#define CLK_AHBCLK_EMACCKEN_Pos (5)
2325#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos)
2327#define CLK_AHBCLK_SDH0CKEN_Pos (6)
2328#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos)
2330#define CLK_AHBCLK_CRCCKEN_Pos (7)
2331#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)
2333#define CLK_AHBCLK_CCAPCKEN_Pos (8)
2334#define CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos)
2336#define CLK_AHBCLK_SENCKEN_Pos (9)
2337#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos)
2339#define CLK_AHBCLK_HSUSBDCKEN_Pos (10)
2340#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos)
2342#define CLK_AHBCLK_CRPTCKEN_Pos (12)
2343#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)
2345#define CLK_AHBCLK_SPIMCKEN_Pos (14)
2346#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos)
2348#define CLK_AHBCLK_FMCIDLE_Pos (15)
2349#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)
2351#define CLK_AHBCLK_USBHCKEN_Pos (16)
2352#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)
2354#define CLK_AHBCLK_SDH1CKEN_Pos (17)
2355#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos)
2357#define CLK_APBCLK0_WDTCKEN_Pos (0)
2358#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)
2360#define CLK_APBCLK0_RTCCKEN_Pos (1)
2361#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)
2363#define CLK_APBCLK0_TMR0CKEN_Pos (2)
2364#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)
2366#define CLK_APBCLK0_TMR1CKEN_Pos (3)
2367#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)
2369#define CLK_APBCLK0_TMR2CKEN_Pos (4)
2370#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)
2372#define CLK_APBCLK0_TMR3CKEN_Pos (5)
2373#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)
2375#define CLK_APBCLK0_CLKOCKEN_Pos (6)
2376#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)
2378#define CLK_APBCLK0_ACMP01CKEN_Pos (7)
2379#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)
2381#define CLK_APBCLK0_I2C0CKEN_Pos (8)
2382#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)
2384#define CLK_APBCLK0_I2C1CKEN_Pos (9)
2385#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)
2387#define CLK_APBCLK0_I2C2CKEN_Pos (10)
2388#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)
2390#define CLK_APBCLK0_QSPI0CKEN_Pos (12)
2391#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos)
2393#define CLK_APBCLK0_SPI0CKEN_Pos (13)
2394#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)
2396#define CLK_APBCLK0_SPI1CKEN_Pos (14)
2397#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)
2399#define CLK_APBCLK0_SPI2CKEN_Pos (15)
2400#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)
2402#define CLK_APBCLK0_UART0CKEN_Pos (16)
2403#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)
2405#define CLK_APBCLK0_UART1CKEN_Pos (17)
2406#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)
2408#define CLK_APBCLK0_UART2CKEN_Pos (18)
2409#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)
2411#define CLK_APBCLK0_UART3CKEN_Pos (19)
2412#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)
2414#define CLK_APBCLK0_UART4CKEN_Pos (20)
2415#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)
2417#define CLK_APBCLK0_UART5CKEN_Pos (21)
2418#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)
2420#define CLK_APBCLK0_UART6CKEN_Pos (22)
2421#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos)
2423#define CLK_APBCLK0_UART7CKEN_Pos (23)
2424#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos)
2426#define CLK_APBCLK0_CAN0CKEN_Pos (24)
2427#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)
2429#define CLK_APBCLK0_CAN1CKEN_Pos (25)
2430#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos)
2432#define CLK_APBCLK0_OTGCKEN_Pos (26)
2433#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)
2435#define CLK_APBCLK0_USBDCKEN_Pos (27)
2436#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)
2438#define CLK_APBCLK0_EADCCKEN_Pos (28)
2439#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)
2441#define CLK_APBCLK0_I2S0CKEN_Pos (29)
2442#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)
2444#define CLK_APBCLK0_HSOTGCKEN_Pos (30)
2445#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos)
2447#define CLK_APBCLK1_SC0CKEN_Pos (0)
2448#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)
2450#define CLK_APBCLK1_SC1CKEN_Pos (1)
2451#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)
2453#define CLK_APBCLK1_SC2CKEN_Pos (2)
2454#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)
2456#define CLK_APBCLK1_QSPI1CKEN_Pos (4)
2457#define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos)
2459#define CLK_APBCLK1_SPI3CKEN_Pos (6)
2460#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos)
2462#define CLK_APBCLK1_USCI0CKEN_Pos (8)
2463#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos)
2465#define CLK_APBCLK1_USCI1CKEN_Pos (9)
2466#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos)
2468#define CLK_APBCLK1_DACCKEN_Pos (12)
2469#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos)
2471#define CLK_APBCLK1_EPWM0CKEN_Pos (16)
2472#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)
2474#define CLK_APBCLK1_EPWM1CKEN_Pos (17)
2475#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)
2477#define CLK_APBCLK1_BPWM0CKEN_Pos (18)
2478#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos)
2480#define CLK_APBCLK1_BPWM1CKEN_Pos (19)
2481#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos)
2483#define CLK_APBCLK1_QEI0CKEN_Pos (22)
2484#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)
2486#define CLK_APBCLK1_QEI1CKEN_Pos (23)
2487#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)
2489#define CLK_APBCLK1_TRNGCKEN_Pos (25)
2490#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos)
2492#define CLK_APBCLK1_ECAP0CKEN_Pos (26)
2493#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)
2495#define CLK_APBCLK1_ECAP1CKEN_Pos (27)
2496#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)
2498#define CLK_APBCLK1_CAN2CKEN_Pos (28)
2499#define CLK_APBCLK1_CAN2CKEN_Msk (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos)
2501#define CLK_APBCLK1_OPACKEN_Pos (30)
2502#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos)
2504#define CLK_APBCLK1_EADC1CKEN_Pos (31)
2505#define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos)
2507#define CLK_CLKSEL0_HCLKSEL_Pos (0)
2508#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
2510#define CLK_CLKSEL0_STCLKSEL_Pos (3)
2511#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
2513#define CLK_CLKSEL0_USBSEL_Pos (8)
2514#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos)
2516#define CLK_CLKSEL0_CCAPSEL_Pos (16)
2517#define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos)
2519#define CLK_CLKSEL0_SDH0SEL_Pos (20)
2520#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos)
2522#define CLK_CLKSEL0_SDH1SEL_Pos (22)
2523#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos)
2525#define CLK_CLKSEL1_WDTSEL_Pos (0)
2526#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
2528#define CLK_CLKSEL1_TMR0SEL_Pos (8)
2529#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
2531#define CLK_CLKSEL1_TMR1SEL_Pos (12)
2532#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
2534#define CLK_CLKSEL1_TMR2SEL_Pos (16)
2535#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)
2537#define CLK_CLKSEL1_TMR3SEL_Pos (20)
2538#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)
2540#define CLK_CLKSEL1_UART0SEL_Pos (24)
2541#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos)
2543#define CLK_CLKSEL1_UART1SEL_Pos (26)
2544#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos)
2546#define CLK_CLKSEL1_CLKOSEL_Pos (28)
2547#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)
2549#define CLK_CLKSEL1_WWDTSEL_Pos (30)
2550#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
2552#define CLK_CLKSEL2_EPWM0SEL_Pos (0)
2553#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos)
2555#define CLK_CLKSEL2_EPWM1SEL_Pos (1)
2556#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos)
2558#define CLK_CLKSEL2_QSPI0SEL_Pos (2)
2559#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos)
2561#define CLK_CLKSEL2_SPI0SEL_Pos (4)
2562#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)
2564#define CLK_CLKSEL2_SPI1SEL_Pos (6)
2565#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)
2567#define CLK_CLKSEL2_BPWM0SEL_Pos (8)
2568#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos)
2570#define CLK_CLKSEL2_BPWM1SEL_Pos (9)
2571#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos)
2573#define CLK_CLKSEL2_SPI2SEL_Pos (10)
2574#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)
2576#define CLK_CLKSEL2_SPI3SEL_Pos (12)
2577#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)
2579#define CLK_CLKSEL3_SC0SEL_Pos (0)
2580#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)
2582#define CLK_CLKSEL3_SC1SEL_Pos (2)
2583#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)
2585#define CLK_CLKSEL3_SC2SEL_Pos (4)
2586#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)
2588#define CLK_CLKSEL3_RTCSEL_Pos (8)
2589#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)
2591#define CLK_CLKSEL3_QSPI1SEL_Pos (12)
2592#define CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos)
2594#define CLK_CLKSEL3_I2S0SEL_Pos (16)
2595#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)
2597#define CLK_CLKSEL3_UART6SEL_Pos (20)
2598#define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos)
2600#define CLK_CLKSEL3_UART7SEL_Pos (22)
2601#define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos)
2603#define CLK_CLKSEL3_UART2SEL_Pos (24)
2604#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos)
2606#define CLK_CLKSEL3_UART3SEL_Pos (26)
2607#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos)
2609#define CLK_CLKSEL3_UART4SEL_Pos (28)
2610#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos)
2612#define CLK_CLKSEL3_UART5SEL_Pos (30)
2613#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos)
2615#define CLK_CLKDIV0_HCLKDIV_Pos (0)
2616#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
2618#define CLK_CLKDIV0_USBDIV_Pos (4)
2619#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos)
2621#define CLK_CLKDIV0_UART0DIV_Pos (8)
2622#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos)
2624#define CLK_CLKDIV0_UART1DIV_Pos (12)
2625#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos)
2627#define CLK_CLKDIV0_EADCDIV_Pos (16)
2628#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos)
2630#define CLK_CLKDIV0_SDH0DIV_Pos (24)
2631#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos)
2633#define CLK_CLKDIV1_SC0DIV_Pos (0)
2634#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos)
2636#define CLK_CLKDIV1_SC1DIV_Pos (8)
2637#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos)
2639#define CLK_CLKDIV1_SC2DIV_Pos (16)
2640#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos)
2642#define CLK_CLKDIV2_I2SDIV_Pos (0)
2643#define CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos)
2645#define CLK_CLKDIV2_EADC1DIV_Pos (24)
2646#define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos)
2648#define CLK_CLKDIV3_CCAPDIV_Pos (0)
2649#define CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos)
2651#define CLK_CLKDIV3_VSENSEDIV_Pos (8)
2652#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos)
2654#define CLK_CLKDIV3_EMACDIV_Pos (16)
2655#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos)
2657#define CLK_CLKDIV3_SDH1DIV_Pos (24)
2658#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos)
2660#define CLK_CLKDIV4_UART2DIV_Pos (0)
2661#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos)
2663#define CLK_CLKDIV4_UART3DIV_Pos (4)
2664#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos)
2666#define CLK_CLKDIV4_UART4DIV_Pos (8)
2667#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos)
2669#define CLK_CLKDIV4_UART5DIV_Pos (12)
2670#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos)
2672#define CLK_CLKDIV4_UART6DIV_Pos (16)
2673#define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos)
2675#define CLK_CLKDIV4_UART7DIV_Pos (20)
2676#define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos)
2678#define CLK_PCLKDIV_APB0DIV_Pos (0)
2679#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos)
2681#define CLK_PCLKDIV_APB1DIV_Pos (4)
2682#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos)
2684#define CLK_PLLCTL_FBDIV_Pos (0)
2685#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
2687#define CLK_PLLCTL_INDIV_Pos (9)
2688#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
2690#define CLK_PLLCTL_OUTDIV_Pos (14)
2691#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
2693#define CLK_PLLCTL_PD_Pos (16)
2694#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
2696#define CLK_PLLCTL_BP_Pos (17)
2697#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
2699#define CLK_PLLCTL_OE_Pos (18)
2700#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
2702#define CLK_PLLCTL_PLLSRC_Pos (19)
2703#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
2705#define CLK_PLLCTL_STBSEL_Pos (23)
2706#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos)
2708#define CLK_STATUS_HXTSTB_Pos (0)
2709#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
2711#define CLK_STATUS_LXTSTB_Pos (1)
2712#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
2714#define CLK_STATUS_PLLSTB_Pos (2)
2715#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
2717#define CLK_STATUS_LIRCSTB_Pos (3)
2718#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
2720#define CLK_STATUS_HIRCSTB_Pos (4)
2721#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
2723#define CLK_STATUS_HIRC48MSTB_Pos (6)
2724#define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos)
2726#define CLK_STATUS_CLKSFAIL_Pos (7)
2727#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
2729#define CLK_CLKOCTL_FREQSEL_Pos (0)
2730#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
2732#define CLK_CLKOCTL_CLKOEN_Pos (4)
2733#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
2735#define CLK_CLKOCTL_DIV1EN_Pos (5)
2736#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
2738#define CLK_CLKOCTL_CLK1HZEN_Pos (6)
2739#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)
2741#define CLK_CLKDCTL_HXTFDEN_Pos (4)
2742#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)
2744#define CLK_CLKDCTL_HXTFIEN_Pos (5)
2745#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)
2747#define CLK_CLKDCTL_LXTFDEN_Pos (12)
2748#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)
2750#define CLK_CLKDCTL_LXTFIEN_Pos (13)
2751#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)
2753#define CLK_CLKDCTL_HXTFQDEN_Pos (16)
2754#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)
2756#define CLK_CLKDCTL_HXTFQIEN_Pos (17)
2757#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)
2759#define CLK_CLKDSTS_HXTFIF_Pos (0)
2760#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)
2762#define CLK_CLKDSTS_LXTFIF_Pos (1)
2763#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)
2765#define CLK_CLKDSTS_HXTFQIF_Pos (8)
2766#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)
2768#define CLK_CDUPB_UPERBD_Pos (0)
2769#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos)
2771#define CLK_CDLOWB_LOWERBD_Pos (0)
2772#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos)
2774#define CLK_PMUCTL_PDMSEL_Pos (0)
2775#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos)
2777#define CLK_PMUCTL_DPDHOLDEN_Pos (3)
2778#define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos)
2780#define CLK_PMUCTL_SRETSEL_Pos (4)
2781#define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos)
2783#define CLK_PMUCTL_WKTMREN_Pos (8)
2784#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos)
2786#define CLK_PMUCTL_WKTMRIS_Pos (9)
2787#define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos)
2789#define CLK_PMUCTL_WKPINEN_Pos (16)
2790#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos)
2792#define CLK_PMUCTL_ACMPSPWK_Pos (18)
2793#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos)
2795#define CLK_PMUCTL_RTCWKEN_Pos (23)
2796#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos)
2798#define CLK_PMUCTL_WKPINEN1_Pos (24)
2799#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos)
2801#define CLK_PMUCTL_WKPINEN2_Pos (26)
2802#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos)
2804#define CLK_PMUCTL_WKPINEN3_Pos (28)
2805#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos)
2807#define CLK_PMUCTL_WKPINEN4_Pos (30)
2808#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos)
2810#define CLK_PMUSTS_PINWK_Pos (0)
2811#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos)
2813#define CLK_PMUSTS_TMRWK_Pos (1)
2814#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos)
2816#define CLK_PMUSTS_RTCWK_Pos (2)
2817#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos)
2819#define CLK_PMUSTS_PINWK1_Pos (3)
2820#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos)
2822#define CLK_PMUSTS_PINWK2_Pos (4)
2823#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos)
2825#define CLK_PMUSTS_PINWK3_Pos (5)
2826#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos)
2828#define CLK_PMUSTS_PINWK4_Pos (6)
2829#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos)
2831#define CLK_PMUSTS_GPAWK_Pos (8)
2832#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos)
2834#define CLK_PMUSTS_GPBWK_Pos (9)
2835#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos)
2837#define CLK_PMUSTS_GPCWK_Pos (10)
2838#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos)
2840#define CLK_PMUSTS_GPDWK_Pos (11)
2841#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos)
2843#define CLK_PMUSTS_LVRWK_Pos (12)
2844#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos)
2846#define CLK_PMUSTS_BODWK_Pos (13)
2847#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos)
2849#define CLK_PMUSTS_ACMPWK_Pos (14)
2850#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos)
2852#define CLK_PMUSTS_CLRWK_Pos (31)
2853#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos)
2855#define CLK_LDOCTL_PDBIASEN_Pos (18)
2856#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos)
2858#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0)
2859#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
2861#define CLK_PASWKCTL_WKEN_Pos (0)
2862#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos)
2864#define CLK_PASWKCTL_PRWKEN_Pos (1)
2865#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos)
2867#define CLK_PASWKCTL_PFWKEN_Pos (2)
2868#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos)
2870#define CLK_PASWKCTL_WKPSEL_Pos (4)
2871#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos)
2873#define CLK_PASWKCTL_DBEN_Pos (8)
2874#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos)
2876#define CLK_PBSWKCTL_WKEN_Pos (0)
2877#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos)
2879#define CLK_PBSWKCTL_PRWKEN_Pos (1)
2880#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos)
2882#define CLK_PBSWKCTL_PFWKEN_Pos (2)
2883#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos)
2885#define CLK_PBSWKCTL_WKPSEL_Pos (4)
2886#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos)
2888#define CLK_PBSWKCTL_DBEN_Pos (8)
2889#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos)
2891#define CLK_PCSWKCTL_WKEN_Pos (0)
2892#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos)
2894#define CLK_PCSWKCTL_PRWKEN_Pos (1)
2895#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos)
2897#define CLK_PCSWKCTL_PFWKEN_Pos (2)
2898#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos)
2900#define CLK_PCSWKCTL_WKPSEL_Pos (4)
2901#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos)
2903#define CLK_PCSWKCTL_DBEN_Pos (8)
2904#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos)
2906#define CLK_PDSWKCTL_WKEN_Pos (0)
2907#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos)
2909#define CLK_PDSWKCTL_PRWKEN_Pos (1)
2910#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos)
2912#define CLK_PDSWKCTL_PFWKEN_Pos (2)
2913#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos)
2915#define CLK_PDSWKCTL_WKPSEL_Pos (4)
2916#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos)
2918#define CLK_PDSWKCTL_DBEN_Pos (8)
2919#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos)
2921#define CLK_IOPDCTL_IOHR_Pos (0)
2922#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /* CLK_CONST */ /* end of CLK register group */ /* end of REGISTER group */
2927
2928#if defined ( __CC_ARM )
2929#pragma no_anon_unions
2930#endif
2931
2932#endif /* __CLK_REG_H__ */
Definition: clk_reg.h:27
__IO uint32_t PWRCTL
Definition: clk_reg.h:2223
__IO uint32_t APBCLK0
Definition: clk_reg.h:2225
__IO uint32_t PASWKCTL
Definition: clk_reg.h:2263
__IO uint32_t CLKDIV4
Definition: clk_reg.h:2235
__IO uint32_t APBCLK1
Definition: clk_reg.h:2226
__IO uint32_t PCLKDIV
Definition: clk_reg.h:2236
__IO uint32_t CLKOCTL
Definition: clk_reg.h:2248
__IO uint32_t CLKDIV1
Definition: clk_reg.h:2232
__IO uint32_t PMUSTS
Definition: clk_reg.h:2260
__IO uint32_t CLKSEL1
Definition: clk_reg.h:2228
__IO uint32_t PDSWKCTL
Definition: clk_reg.h:2266
__IO uint32_t CLKDIV0
Definition: clk_reg.h:2231
__IO uint32_t LDOCTL
Definition: clk_reg.h:2261
__IO uint32_t CLKSEL0
Definition: clk_reg.h:2227
__IO uint32_t PBSWKCTL
Definition: clk_reg.h:2264
__IO uint32_t PMUCTL
Definition: clk_reg.h:2259
__I uint32_t STATUS
Definition: clk_reg.h:2244
__IO uint32_t AHBCLK
Definition: clk_reg.h:2224
__IO uint32_t PCSWKCTL
Definition: clk_reg.h:2265
__IO uint32_t CDUPB
Definition: clk_reg.h:2254
__IO uint32_t CLKDIV3
Definition: clk_reg.h:2234
__IO uint32_t CLKDCTL
Definition: clk_reg.h:2252
__IO uint32_t CLKDSTS
Definition: clk_reg.h:2253
__IO uint32_t CLKDIV2
Definition: clk_reg.h:2233
__IO uint32_t CLKSEL2
Definition: clk_reg.h:2229
__IO uint32_t SWKDBCTL
Definition: clk_reg.h:2262
__IO uint32_t CDLOWB
Definition: clk_reg.h:2255
__IO uint32_t IOPDCTL
Definition: clk_reg.h:2267
__IO uint32_t CLKSEL3
Definition: clk_reg.h:2230
__IO uint32_t PLLCTL
Definition: clk_reg.h:2240