M480 BSP V3.05.005
The Board Support Package for M480 Series
sys.h
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1/**************************************************************************/
10#ifndef __SYS_H__
11#define __SYS_H__
12
13#ifdef __cplusplus
14extern "C"
15{
16#endif
17
18
32/*---------------------------------------------------------------------------------------------------------*/
33/* Module Reset Control Resister constant definitions. */
34/*---------------------------------------------------------------------------------------------------------*/
35#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos)
36#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)
37#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos)
38#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos)
39#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos)
40#define CCAP_RST ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos)
41#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos)
42#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos)
43#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos)
44#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos)
45#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos)
47#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)
48#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)
49#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)
50#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)
51#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)
52#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)
53#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)
54#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)
55#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos)
56#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos)
57#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos)
58#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos)
59#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos)
60#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos)
61#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos)
62#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos)
63#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos)
64#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos)
65#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos)
66#define UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos)
67#define UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos)
68#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos)
69#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos)
70#define OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos)
71#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos)
72#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos)
73#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos)
74#define HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos)
75#define TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos)
77#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos)
78#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos)
79#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos)
80#define QSPI1_RST ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos)
81#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos)
82#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos)
83#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos)
84#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos)
85#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos)
86#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos)
87#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos)
88#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos)
89#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos)
90#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos)
91#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos)
92#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos)
93#define CAN2_RST ((8UL<<24) | SYS_IPRST2_CAN2RST_Pos)
94#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos)
95#define EADC1_RST ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos)
97/*---------------------------------------------------------------------------------------------------------*/
98/* Brown Out Detector Threshold Voltage Selection constant definitions. */
99/*---------------------------------------------------------------------------------------------------------*/
100#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos)
101#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos)
102#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos)
103#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos)
104#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos)
105#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos)
106#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos)
107#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos)
108#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos)
109#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos)
112/*---------------------------------------------------------------------------------------------------------*/
113/* VREFCTL constant definitions. (Write-Protection Register) */
114/*---------------------------------------------------------------------------------------------------------*/
115#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos)
116#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos)
117#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos)
118#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos)
119#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos)
120#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos)
123/*---------------------------------------------------------------------------------------------------------*/
124/* USBPHY constant definitions. (Write-Protection Register) */
125/*---------------------------------------------------------------------------------------------------------*/
126#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos)
127#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos)
128#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos)
129#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos)
130#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos)
131#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos)
132#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos)
134/*---------------------------------------------------------------------------------------------------------*/
135/* PLCTL constant definitions. (Write-Protection Register) */
136/*---------------------------------------------------------------------------------------------------------*/
137#define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos)
138#define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos)
141/*---------------------------------------------------------------------------------------------------------*/
142/* Multi-Function constant definitions. */
143/*---------------------------------------------------------------------------------------------------------*/
144/* How to use below #define?
145Example 1: If user want to set PA.0 as SC0_CLK in initial function,
146 user can issue following command to achieve it.
147
148 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
149
150*/
151/********************* Bit definition of GPA_MFPL register **********************/
152#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos)
153#define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos)
154#define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos)
155#define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos)
156#define SYS_GPA_MFPL_PA0MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos)
157#define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos)
158#define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos)
159#define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos)
160#define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos)
161#define SYS_GPA_MFPL_PA0MFP_CCAP_DATA6 (0x0AUL<<SYS_GPA_MFPL_PA0MFP_Pos)
162#define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos)
163#define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos)
164#define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos)
165#define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos)
166#define SYS_GPA_MFPL_PA1MFP_SPIM_MISO (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos)
167#define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos)
168#define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos)
169#define SYS_GPA_MFPL_PA1MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos)
170#define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos)
171#define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos)
172#define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos)
173#define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos)
174#define SYS_GPA_MFPL_PA1MFP_CCAP_DATA7 (0x0AUL<<SYS_GPA_MFPL_PA1MFP_Pos)
175#define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos)
176#define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos)
177#define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos)
178#define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos)
179#define SYS_GPA_MFPL_PA2MFP_SPIM_CLK (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos)
180#define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos)
181#define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos)
182#define SYS_GPA_MFPL_PA2MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos)
183#define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos)
184#define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos)
185#define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos)
186#define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos)
187#define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS (0x0AUL<<SYS_GPA_MFPL_PA2MFP_Pos)
188#define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos)
189#define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos)
190#define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos)
191#define SYS_GPA_MFPL_PA3MFP_SPIM_SS (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos)
192#define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos)
193#define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos)
194#define SYS_GPA_MFPL_PA3MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos)
195#define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos)
196#define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos)
197#define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos)
198#define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos)
199#define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL (0x0AUL<<SYS_GPA_MFPL_PA3MFP_Pos)
200#define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos)
201#define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos)
202#define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos)
203#define SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1 (0x0FUL<<SYS_GPA_MFPL_PA3MFP_Pos)
204#define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos)
205#define SYS_GPA_MFPL_PA4MFP_SPIM_D3 (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos)
206#define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos)
207#define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos)
208#define SYS_GPA_MFPL_PA4MFP_SD1_CLK (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos)
209#define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos)
210#define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos)
211#define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos)
212#define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos)
213#define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos)
214#define SYS_GPA_MFPL_PA4MFP_UART0_RXD (0x0BUL<<SYS_GPA_MFPL_PA4MFP_Pos)
215#define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos)
216#define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos)
217#define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos)
218#define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos)
219#define SYS_GPA_MFPL_PA5MFP_SPIM_D2 (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos)
220#define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos)
221#define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos)
222#define SYS_GPA_MFPL_PA5MFP_SD1_CMD (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos)
223#define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos)
224#define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos)
225#define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos)
226#define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos)
227#define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos)
228#define SYS_GPA_MFPL_PA5MFP_UART0_TXD (0x0BUL<<SYS_GPA_MFPL_PA5MFP_Pos)
229#define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos)
230#define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos)
231#define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos)
232#define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos)
233#define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos)
234#define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos)
235#define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos)
236#define SYS_GPA_MFPL_PA6MFP_SD1_nCD (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos)
237#define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos)
238#define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos)
239#define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos)
240#define SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1 (0x09UL<<SYS_GPA_MFPL_PA6MFP_Pos)
241#define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos)
242#define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos)
243#define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos)
244#define SYS_GPA_MFPL_PA6MFP_TM3 (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos)
245#define SYS_GPA_MFPL_PA6MFP_INT0 (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos)
246#define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos)
247#define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos)
248#define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos)
249#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos)
250#define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos)
251#define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos)
252#define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos)
253#define SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1 (0x09UL<<SYS_GPA_MFPL_PA7MFP_Pos)
254#define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos)
255#define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos)
256#define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos)
257#define SYS_GPA_MFPL_PA7MFP_TM2 (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos)
258#define SYS_GPA_MFPL_PA7MFP_INT1 (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos)
259/********************* Bit definition of GPA_MFPH register **********************/
260#define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos)
261#define SYS_GPA_MFPH_PA8MFP_OPA1_P (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)
262#define SYS_GPA_MFPH_PA8MFP_EADC1_CH4 (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)
263#define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos)
264#define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos)
265#define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos)
266#define SYS_GPA_MFPH_PA8MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos)
267#define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos)
268#define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos)
269#define SYS_GPA_MFPH_PA8MFP_UART7_RXD (0x08UL<<SYS_GPA_MFPH_PA8MFP_Pos)
270#define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos)
271#define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos)
272#define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos)
273#define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos)
274#define SYS_GPA_MFPH_PA8MFP_INT4 (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos)
275#define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos)
276#define SYS_GPA_MFPH_PA9MFP_OPA1_N (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)
277#define SYS_GPA_MFPH_PA9MFP_EADC1_CH5 (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)
278#define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos)
279#define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos)
280#define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos)
281#define SYS_GPA_MFPH_PA9MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos)
282#define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos)
283#define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos)
284#define SYS_GPA_MFPH_PA9MFP_UART7_TXD (0x08UL<<SYS_GPA_MFPH_PA9MFP_Pos)
285#define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos)
286#define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos)
287#define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos)
288#define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos)
289#define SYS_GPA_MFPH_PA9MFP_SWDH_DAT (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos)
290#define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos)
291#define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)
292#define SYS_GPA_MFPH_PA10MFP_OPA1_O (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)
293#define SYS_GPA_MFPH_PA10MFP_EADC1_CH6 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)
294#define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos)
295#define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos)
296#define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos)
297#define SYS_GPA_MFPH_PA10MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos)
298#define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos)
299#define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos)
300#define SYS_GPA_MFPH_PA10MFP_UART6_RXD (0x08UL<<SYS_GPA_MFPH_PA10MFP_Pos)
301#define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos)
302#define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos)
303#define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos)
304#define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos)
305#define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos)
306#define SYS_GPA_MFPH_PA10MFP_SWDH_CLK (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos)
307#define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos)
308#define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)
309#define SYS_GPA_MFPH_PA11MFP_EADC1_CH7 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)
310#define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos)
311#define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos)
312#define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos)
313#define SYS_GPA_MFPH_PA11MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos)
314#define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos)
315#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos)
316#define SYS_GPA_MFPH_PA11MFP_UART6_TXD (0x08UL<<SYS_GPA_MFPH_PA11MFP_Pos)
317#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos)
318#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos)
319#define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos)
320#define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos)
321#define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos)
322#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos)
323#define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos)
324#define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos)
325#define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos)
326#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos)
327#define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos)
328#define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos)
329#define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos)
330#define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos)
331#define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos)
332#define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos)
333#define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos)
334#define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos)
335#define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos)
336#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos)
337#define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos)
338#define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos)
339#define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos)
340#define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos)
341#define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos)
342#define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos)
343#define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos)
344#define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos)
345#define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos)
346#define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos)
347#define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos)
348#define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos)
349#define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos)
350#define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos)
351#define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos)
352#define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos)
353#define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos)
354#define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos)
355#define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos)
356#define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos)
357#define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos)
358#define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos)
359/********************* Bit definition of GPB_MFPL register **********************/
360#define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos)
361#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)
362#define SYS_GPB_MFPL_PB0MFP_EADC1_CH8 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)
363#define SYS_GPB_MFPL_PB0MFP_OPA0_P (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)
364#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos)
365#define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos)
366#define SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPB_MFPL_PB0MFP_Pos)
367#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos)
368#define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos)
369#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos)
370#define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos)
371#define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos)
372#define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos)
373#define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos)
374#define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)
375#define SYS_GPB_MFPL_PB1MFP_OPA0_N (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)
376#define SYS_GPB_MFPL_PB1MFP_EADC1_CH9 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)
377#define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos)
378#define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos)
379#define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos)
380#define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos)
381#define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos)
382#define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos)
383#define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos)
384#define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos)
385#define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos)
386#define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos)
387#define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos)
388#define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos)
389#define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos)
390#define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)
391#define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)
392#define SYS_GPB_MFPL_PB2MFP_OPA0_O (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)
393#define SYS_GPB_MFPL_PB2MFP_EADC1_CH10 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)
394#define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos)
395#define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos)
396#define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos)
397#define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos)
398#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos)
399#define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos)
400#define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos)
401#define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos)
402#define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos)
403#define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos)
404#define SYS_GPB_MFPL_PB2MFP_I2C1_SDA (0x0CUL<<SYS_GPB_MFPL_PB2MFP_Pos)
405#define SYS_GPB_MFPL_PB2MFP_TM3 (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos)
406#define SYS_GPB_MFPL_PB2MFP_INT3 (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos)
407#define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos)
408#define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)
409#define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)
410#define SYS_GPB_MFPL_PB3MFP_EADC1_CH11 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)
411#define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos)
412#define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos)
413#define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1 (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos)
414#define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos)
415#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos)
416#define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos)
417#define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos)
418#define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos)
419#define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos)
420#define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos)
421#define SYS_GPB_MFPL_PB3MFP_I2C1_SCL (0x0CUL<<SYS_GPB_MFPL_PB3MFP_Pos)
422#define SYS_GPB_MFPL_PB3MFP_TM2 (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos)
423#define SYS_GPB_MFPL_PB3MFP_INT2 (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos)
424#define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos)
425#define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)
426#define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)
427#define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos)
428#define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos)
429#define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos)
430#define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos)
431#define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos)
432#define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos)
433#define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos)
434#define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos)
435#define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos)
436#define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos)
437#define SYS_GPB_MFPL_PB4MFP_UART2_RXD (0x0CUL<<SYS_GPB_MFPL_PB4MFP_Pos)
438#define SYS_GPB_MFPL_PB4MFP_TM1 (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos)
439#define SYS_GPB_MFPL_PB4MFP_INT1 (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos)
440#define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos)
441#define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)
442#define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)
443#define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos)
444#define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos)
445#define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos)
446#define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos)
447#define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos)
448#define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos)
449#define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos)
450#define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos)
451#define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos)
452#define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos)
453#define SYS_GPB_MFPL_PB5MFP_UART2_TXD (0x0CUL<<SYS_GPB_MFPL_PB5MFP_Pos)
454#define SYS_GPB_MFPL_PB5MFP_TM0 (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos)
455#define SYS_GPB_MFPL_PB5MFP_INT0 (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos)
456#define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos)
457#define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos)
458#define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos)
459#define SYS_GPB_MFPL_PB6MFP_EMAC_PPS (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos)
460#define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos)
461#define SYS_GPB_MFPL_PB6MFP_CAN1_RXD (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos)
462#define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos)
463#define SYS_GPB_MFPL_PB6MFP_SD1_CLK (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos)
464#define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos)
465#define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos)
466#define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos)
467#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos)
468#define SYS_GPB_MFPL_PB6MFP_INT4 (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos)
469#define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos)
470#define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos)
471#define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos)
472#define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos)
473#define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos)
474#define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos)
475#define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos)
476#define SYS_GPB_MFPL_PB7MFP_CAN1_TXD (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos)
477#define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos)
478#define SYS_GPB_MFPL_PB7MFP_SD1_CMD (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos)
479#define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos)
480#define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos)
481#define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos)
482#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos)
483#define SYS_GPB_MFPL_PB7MFP_INT5 (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos)
484#define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos)
485#define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos)
486/********************* Bit definition of GPB_MFPH register **********************/
487#define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos)
488#define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos)
489#define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos)
490#define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos)
491#define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos)
492#define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos)
493#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos)
494#define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos)
495#define SYS_GPB_MFPH_PB8MFP_UART7_RXD (0x08UL<<SYS_GPB_MFPH_PB8MFP_Pos)
496#define SYS_GPB_MFPH_PB8MFP_I2C0_SDA (0x09UL<<SYS_GPB_MFPH_PB8MFP_Pos)
497#define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos)
498#define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos)
499#define SYS_GPB_MFPH_PB8MFP_CAN2_RXD (0x0CUL<<SYS_GPB_MFPH_PB8MFP_Pos)
500#define SYS_GPB_MFPH_PB8MFP_INT6 (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos)
501#define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos)
502#define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos)
503#define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos)
504#define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos)
505#define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos)
506#define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos)
507#define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos)
508#define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos)
509#define SYS_GPB_MFPH_PB9MFP_UART7_TXD (0x08UL<<SYS_GPB_MFPH_PB9MFP_Pos)
510#define SYS_GPB_MFPH_PB9MFP_I2C0_SCL (0x09UL<<SYS_GPB_MFPH_PB9MFP_Pos)
511#define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos)
512#define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos)
513#define SYS_GPB_MFPH_PB9MFP_CAN2_TXD (0x0CUL<<SYS_GPB_MFPH_PB9MFP_Pos)
514#define SYS_GPB_MFPH_PB9MFP_INT7 (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos)
515#define SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC (0x0EUL<<SYS_GPB_MFPH_PB9MFP_Pos)
516#define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos)
517#define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)
518#define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos)
519#define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos)
520#define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos)
521#define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos)
522#define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos)
523#define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos)
524#define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos)
525#define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos)
526#define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos)
527#define SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC (0x0CUL<<SYS_GPB_MFPH_PB10MFP_Pos)
528#define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos)
529#define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos)
530#define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos)
531#define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos)
532#define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos)
533#define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos)
534#define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos)
535#define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos)
536#define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos)
537#define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos)
538#define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos)
539#define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos)
540#define SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD (0x0CUL<<SYS_GPB_MFPH_PB11MFP_Pos)
541#define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos)
542#define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos)
543#define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)
544#define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)
545#define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)
546#define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)
547#define SYS_GPB_MFPH_PB12MFP_EADC1_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)
548#define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos)
549#define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos)
550#define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos)
551#define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos)
552#define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos)
553#define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos)
554#define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos)
555#define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos)
556#define SYS_GPB_MFPH_PB12MFP_CCAP_SCLK (0x0AUL<<SYS_GPB_MFPH_PB12MFP_Pos)
557#define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos)
558#define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3 (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos)
559#define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos)
560#define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos)
561#define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)
562#define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)
563#define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)
564#define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)
565#define SYS_GPB_MFPH_PB13MFP_EADC1_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)
566#define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos)
567#define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos)
568#define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos)
569#define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos)
570#define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos)
571#define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos)
572#define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos)
573#define SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK (0x0AUL<<SYS_GPB_MFPH_PB13MFP_Pos)
574#define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos)
575#define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2 (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos)
576#define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos)
577#define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos)
578#define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)
579#define SYS_GPB_MFPH_PB14MFP_EADC1_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)
580#define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos)
581#define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos)
582#define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos)
583#define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos)
584#define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos)
585#define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos)
586#define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos)
587#define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos)
588#define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1 (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos)
589#define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos)
590#define SYS_GPB_MFPH_PB14MFP_CLKO (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos)
591#define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0FUL<<SYS_GPB_MFPH_PB14MFP_Pos)
592#define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos)
593#define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)
594#define SYS_GPB_MFPH_PB15MFP_EADC1_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)
595#define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos)
596#define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos)
597#define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos)
598#define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos)
599#define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos)
600#define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos)
601#define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos)
602#define SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1 (0x0AUL<<SYS_GPB_MFPH_PB15MFP_Pos)
603#define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos)
604#define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0 (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos)
605#define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos)
606#define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos)
607#define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos)
608/********************* Bit definition of GPC_MFPL register **********************/
609#define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos)
610#define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos)
611#define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos)
612#define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos)
613#define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos)
614#define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos)
615#define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos)
616#define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos)
617#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos)
618#define SYS_GPC_MFPL_PC0MFP_CAN2_RXD (0x0AUL<<SYS_GPC_MFPL_PC0MFP_Pos)
619#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos)
620#define SYS_GPC_MFPL_PC0MFP_CCAP_DATA0 (0x0DUL<<SYS_GPC_MFPL_PC0MFP_Pos)
621#define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos)
622#define SYS_GPC_MFPL_PC0MFP_EADC1_ST (0x0FUL<<SYS_GPC_MFPL_PC0MFP_Pos)
623#define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos)
624#define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos)
625#define SYS_GPC_MFPL_PC1MFP_SPIM_MISO (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos)
626#define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos)
627#define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos)
628#define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos)
629#define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos)
630#define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos)
631#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos)
632#define SYS_GPC_MFPL_PC1MFP_CAN2_TXD (0x0AUL<<SYS_GPC_MFPL_PC1MFP_Pos)
633#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos)
634#define SYS_GPC_MFPL_PC1MFP_CCAP_DATA1 (0x0DUL<<SYS_GPC_MFPL_PC1MFP_Pos)
635#define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos)
636#define SYS_GPC_MFPL_PC1MFP_EADC0_ST (0x0FUL<<SYS_GPC_MFPL_PC1MFP_Pos)
637#define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos)
638#define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos)
639#define SYS_GPC_MFPL_PC2MFP_SPIM_CLK (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos)
640#define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos)
641#define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos)
642#define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos)
643#define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos)
644#define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos)
645#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos)
646#define SYS_GPC_MFPL_PC2MFP_CAN1_RXD (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos)
647#define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos)
648#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos)
649#define SYS_GPC_MFPL_PC2MFP_CCAP_DATA2 (0x0DUL<<SYS_GPC_MFPL_PC2MFP_Pos)
650#define SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0 (0x0EUL<<SYS_GPC_MFPL_PC2MFP_Pos)
651#define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos)
652#define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos)
653#define SYS_GPC_MFPL_PC3MFP_SPIM_SS (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos)
654#define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos)
655#define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos)
656#define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos)
657#define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos)
658#define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos)
659#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos)
660#define SYS_GPC_MFPL_PC3MFP_CAN1_TXD (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos)
661#define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos)
662#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos)
663#define SYS_GPC_MFPL_PC3MFP_CCAP_DATA3 (0x0DUL<<SYS_GPC_MFPL_PC3MFP_Pos)
664#define SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0 (0x0EUL<<SYS_GPC_MFPL_PC3MFP_Pos)
665#define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos)
666#define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos)
667#define SYS_GPC_MFPL_PC4MFP_SPIM_D3 (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos)
668#define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos)
669#define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos)
670#define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos)
671#define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos)
672#define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos)
673#define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos)
674#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos)
675#define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos)
676#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos)
677#define SYS_GPC_MFPL_PC4MFP_CCAP_DATA4 (0x0DUL<<SYS_GPC_MFPL_PC4MFP_Pos)
678#define SYS_GPC_MFPL_PC4MFP_QSPI1_CLK (0x0EUL<<SYS_GPC_MFPL_PC4MFP_Pos)
679#define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos)
680#define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos)
681#define SYS_GPC_MFPL_PC5MFP_SPIM_D2 (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos)
682#define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos)
683#define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos)
684#define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos)
685#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos)
686#define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos)
687#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos)
688#define SYS_GPC_MFPL_PC5MFP_CCAP_DATA5 (0x0DUL<<SYS_GPC_MFPL_PC5MFP_Pos)
689#define SYS_GPC_MFPL_PC5MFP_QSPI1_SS (0x0EUL<<SYS_GPC_MFPL_PC5MFP_Pos)
690#define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos)
691#define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos)
692#define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos)
693#define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos)
694#define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos)
695#define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos)
696#define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos)
697#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos)
698#define SYS_GPC_MFPL_PC6MFP_UART6_RXD (0x09UL<<SYS_GPC_MFPL_PC6MFP_Pos)
699#define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos)
700#define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos)
701#define SYS_GPC_MFPL_PC6MFP_TM1 (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos)
702#define SYS_GPC_MFPL_PC6MFP_INT2 (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos)
703#define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos)
704#define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos)
705#define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos)
706#define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos)
707#define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos)
708#define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos)
709#define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos)
710#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos)
711#define SYS_GPC_MFPL_PC7MFP_UART6_TXD (0x09UL<<SYS_GPC_MFPL_PC7MFP_Pos)
712#define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos)
713#define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos)
714#define SYS_GPC_MFPL_PC7MFP_TM0 (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos)
715#define SYS_GPC_MFPL_PC7MFP_INT3 (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos)
716/********************* Bit definition of GPC_MFPH register **********************/
717#define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos)
718#define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos)
719#define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos)
720#define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos)
721#define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos)
722#define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos)
723#define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos)
724#define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos)
725#define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos)
726#define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos)
727#define SYS_GPC_MFPH_PC9MFP_UART6_nCTS (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos)
728#define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos)
729#define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos)
730#define SYS_GPC_MFPH_PC9MFP_CAN1_RXD (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos)
731#define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos)
732#define SYS_GPC_MFPH_PC9MFP_EADC1_ST (0x0EUL<<SYS_GPC_MFPH_PC9MFP_Pos)
733#define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos)
734#define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos)
735#define SYS_GPC_MFPH_PC10MFP_UART6_nRTS (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos)
736#define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos)
737#define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos)
738#define SYS_GPC_MFPH_PC10MFP_CAN1_TXD (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos)
739#define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos)
740#define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos)
741#define SYS_GPC_MFPH_PC10MFP_EADC1_ST (0x0EUL<<SYS_GPC_MFPH_PC10MFP_Pos)
742#define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos)
743#define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos)
744#define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos)
745#define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos)
746#define SYS_GPC_MFPH_PC11MFP_UART6_RXD (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos)
747#define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos)
748#define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos)
749#define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos)
750#define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos)
751#define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos)
752#define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos)
753#define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos)
754#define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos)
755#define SYS_GPC_MFPH_PC12MFP_UART6_TXD (0x05UL<<SYS_GPC_MFPH_PC12MFP_Pos)
756#define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos)
757#define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos)
758#define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos)
759#define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos)
760#define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos)
761#define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos)
762#define SYS_GPC_MFPH_PC13MFP_EADC1_CH3 (0x01UL<<SYS_GPC_MFPH_PC13MFP_Pos)
763#define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos)
764#define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos)
765#define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos)
766#define SYS_GPC_MFPH_PC13MFP_CAN1_TXD (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos)
767#define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos)
768#define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos)
769#define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos)
770#define SYS_GPC_MFPH_PC13MFP_CLKO (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos)
771#define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos)
772#define SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos)
773#define SYS_GPC_MFPH_PC14MFP_EBI_AD11 (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos)
774#define SYS_GPC_MFPH_PC14MFP_SC1_nCD (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos)
775#define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos)
776#define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0 (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos)
777#define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos)
778#define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos)
779#define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos)
780#define SYS_GPC_MFPH_PC14MFP_TM1 (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos)
781#define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos)
782#define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos)
783/********************* Bit definition of GPD_MFPL register **********************/
784#define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos)
785#define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos)
786#define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos)
787#define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos)
788#define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos)
789#define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos)
790#define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos)
791#define SYS_GPD_MFPL_PD0MFP_TM2 (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos)
792#define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos)
793#define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos)
794#define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos)
795#define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos)
796#define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos)
797#define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos)
798#define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos)
799#define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos)
800#define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos)
801#define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos)
802#define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos)
803#define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos)
804#define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos)
805#define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos)
806#define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos)
807#define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos)
808#define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos)
809#define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos)
810#define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos)
811#define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos)
812#define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos)
813#define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos)
814#define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos)
815#define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos)
816#define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos)
817#define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos)
818#define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos)
819#define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos)
820#define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos)
821#define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos)
822#define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos)
823#define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos)
824#define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos)
825#define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos)
826#define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos)
827#define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos)
828#define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos)
829#define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos)
830#define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos)
831#define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos)
832#define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos)
833#define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos)
834#define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos)
835#define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos)
836#define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos)
837#define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos)
838#define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos)
839/********************* Bit definition of GPD_MFPH register **********************/
840#define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos)
841#define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos)
842#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos)
843#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos)
844#define SYS_GPD_MFPH_PD8MFP_UART7_RXD (0x05UL<<SYS_GPD_MFPH_PD8MFP_Pos)
845#define SYS_GPD_MFPH_PD8MFP_CAN2_RXD (0x06UL<<SYS_GPD_MFPH_PD8MFP_Pos)
846#define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos)
847#define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos)
848#define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos)
849#define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos)
850#define SYS_GPD_MFPH_PD9MFP_UART7_TXD (0x05UL<<SYS_GPD_MFPH_PD9MFP_Pos)
851#define SYS_GPD_MFPH_PD9MFP_CAN2_TXD (0x06UL<<SYS_GPD_MFPH_PD9MFP_Pos)
852#define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos)
853#define SYS_GPD_MFPH_PD10MFP_OPA2_P (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos)
854#define SYS_GPD_MFPH_PD10MFP_EADC1_CH0 (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos)
855#define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos)
856#define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos)
857#define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos)
858#define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos)
859#define SYS_GPD_MFPH_PD10MFP_INT7 (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos)
860#define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos)
861#define SYS_GPD_MFPH_PD11MFP_EADC1_CH1 (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos)
862#define SYS_GPD_MFPH_PD11MFP_OPA2_N (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos)
863#define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos)
864#define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos)
865#define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos)
866#define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos)
867#define SYS_GPD_MFPH_PD11MFP_INT6 (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos)
868#define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos)
869#define SYS_GPD_MFPH_PD12MFP_OPA2_O (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos)
870#define SYS_GPD_MFPH_PD12MFP_EADC1_CH2 (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos)
871#define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos)
872#define SYS_GPD_MFPH_PD12MFP_CAN1_RXD (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos)
873#define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos)
874#define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos)
875#define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos)
876#define SYS_GPD_MFPH_PD12MFP_CLKO (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos)
877#define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos)
878#define SYS_GPD_MFPH_PD12MFP_INT5 (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos)
879#define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos)
880#define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos)
881#define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos)
882#define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos)
883#define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos)
884#define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos)
885#define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos)
886#define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos)
887#define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos)
888#define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos)
889#define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos)
890#define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos)
891/********************* Bit definition of GPE_MFPL register **********************/
892#define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos)
893#define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos)
894#define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos)
895#define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos)
896#define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos)
897#define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos)
898#define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos)
899#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos)
900#define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos)
901#define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos)
902#define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos)
903#define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos)
904#define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos)
905#define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos)
906#define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos)
907#define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos)
908#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos)
909#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos)
910#define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos)
911#define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos)
912#define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos)
913#define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos)
914#define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos)
915#define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos)
916#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos)
917#define SYS_GPE_MFPL_PE2MFP_UART6_nCTS (0x08UL<<SYS_GPE_MFPL_PE2MFP_Pos)
918#define SYS_GPE_MFPL_PE2MFP_UART7_RXD (0x09UL<<SYS_GPE_MFPL_PE2MFP_Pos)
919#define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos)
920#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos)
921#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos)
922#define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos)
923#define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos)
924#define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos)
925#define SYS_GPE_MFPL_PE3MFP_SPIM_MISO (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos)
926#define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos)
927#define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos)
928#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos)
929#define SYS_GPE_MFPL_PE3MFP_UART6_nRTS (0x08UL<<SYS_GPE_MFPL_PE3MFP_Pos)
930#define SYS_GPE_MFPL_PE3MFP_UART7_TXD (0x09UL<<SYS_GPE_MFPL_PE3MFP_Pos)
931#define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos)
932#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos)
933#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos)
934#define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos)
935#define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos)
936#define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos)
937#define SYS_GPE_MFPL_PE4MFP_SPIM_CLK (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos)
938#define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos)
939#define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos)
940#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos)
941#define SYS_GPE_MFPL_PE4MFP_UART6_RXD (0x08UL<<SYS_GPE_MFPL_PE4MFP_Pos)
942#define SYS_GPE_MFPL_PE4MFP_UART7_nCTS (0x09UL<<SYS_GPE_MFPL_PE4MFP_Pos)
943#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos)
944#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos)
945#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos)
946#define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos)
947#define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos)
948#define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos)
949#define SYS_GPE_MFPL_PE5MFP_SPIM_SS (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos)
950#define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos)
951#define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos)
952#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos)
953#define SYS_GPE_MFPL_PE5MFP_UART6_TXD (0x08UL<<SYS_GPE_MFPL_PE5MFP_Pos)
954#define SYS_GPE_MFPL_PE5MFP_UART7_nRTS (0x09UL<<SYS_GPE_MFPL_PE5MFP_Pos)
955#define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos)
956#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos)
957#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos)
958#define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos)
959#define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos)
960#define SYS_GPE_MFPL_PE6MFP_SPIM_D3 (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos)
961#define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos)
962#define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos)
963#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos)
964#define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos)
965#define SYS_GPE_MFPL_PE6MFP_CAN1_RXD (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos)
966#define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos)
967#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos)
968#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos)
969#define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos)
970#define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos)
971#define SYS_GPE_MFPL_PE7MFP_SPIM_D2 (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos)
972#define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos)
973#define SYS_GPE_MFPL_PE7MFP_CAN1_TXD (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos)
974#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos)
975#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos)
976#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos)
977/********************* Bit definition of GPE_MFPH register **********************/
978#define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos)
979#define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos)
980#define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos)
981#define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos)
982#define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos)
983#define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos)
984#define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos)
985#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos)
986#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos)
987#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos)
988#define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos)
989#define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos)
990#define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos)
991#define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos)
992#define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos)
993#define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos)
994#define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos)
995#define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos)
996#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos)
997#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos)
998#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos)
999#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos)
1000#define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1001#define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1002#define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1003#define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1004#define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1005#define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1006#define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos)
1007#define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos)
1008#define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos)
1009#define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos)
1010#define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos)
1011#define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1012#define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1013#define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1014#define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1015#define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1016#define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1017#define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1018#define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos)
1019#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos)
1020#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos)
1021#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos)
1022#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos)
1023#define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1024#define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1025#define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1026#define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1027#define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1028#define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1029#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)
1030#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos)
1031#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos)
1032#define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos)
1033#define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1034#define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1035#define SYS_GPE_MFPH_PE13MFP_EMAC_PPS (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1036#define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1037#define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1038#define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos)
1039#define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos)
1040#define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos)
1041#define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos)
1042#define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos)
1043#define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1044#define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1045#define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1046#define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1047#define SYS_GPE_MFPH_PE14MFP_SD1_nCD (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1048#define SYS_GPE_MFPH_PE14MFP_UART6_TXD (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos)
1049#define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos)
1050#define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos)
1051#define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos)
1052#define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos)
1053#define SYS_GPE_MFPH_PE15MFP_UART6_RXD (0x06UL<<SYS_GPE_MFPH_PE15MFP_Pos)
1054/********************* Bit definition of GPF_MFPL register **********************/
1055#define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos)
1056#define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos)
1057#define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos)
1058#define SYS_GPF_MFPL_PF0MFP_UART0_TXD (0x04UL<<SYS_GPF_MFPL_PF0MFP_Pos)
1059#define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos)
1060#define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos)
1061#define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos)
1062#define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos)
1063#define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos)
1064#define SYS_GPF_MFPL_PF1MFP_UART0_RXD (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos)
1065#define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos)
1066#define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos)
1067#define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos)
1068#define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos)
1069#define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos)
1070#define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos)
1071#define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos)
1072#define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos)
1073#define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos)
1074#define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos)
1075#define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos)
1076#define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos)
1077#define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos)
1078#define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos)
1079#define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos)
1080#define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos)
1081#define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos)
1082#define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos)
1083#define SYS_GPF_MFPL_PF4MFP_EPWM0_CH1 (0x07UL<<SYS_GPF_MFPL_PF4MFP_Pos)
1084#define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos)
1085#define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos)
1086#define SYS_GPF_MFPL_PF4MFP_EADC1_ST (0x0BUL<<SYS_GPF_MFPL_PF4MFP_Pos)
1087#define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1088#define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1089#define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1090#define SYS_GPF_MFPL_PF5MFP_EPWM0_CH0 (0x07UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1091#define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1092#define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos)
1093#define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos)
1094#define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos)
1095#define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1096#define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1097#define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1098#define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1099#define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1100#define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1101#define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1102#define SYS_GPF_MFPL_PF6MFP_CAN2_RXD (0x08UL<<SYS_GPF_MFPL_PF6MFP_Pos)
1103#define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos)
1104#define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1105#define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1106#define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1107#define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1108#define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1109#define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1110#define SYS_GPF_MFPL_PF7MFP_CCAP_DATA0 (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1111#define SYS_GPF_MFPL_PF7MFP_CAN2_TXD (0x08UL<<SYS_GPF_MFPL_PF7MFP_Pos)
1112#define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos)
1113/********************* Bit definition of GPF_MFPH register **********************/
1114#define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1115#define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1116#define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1117#define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1118#define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1119#define SYS_GPF_MFPH_PF8MFP_UART5_nCTS (0x06UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1120#define SYS_GPF_MFPH_PF8MFP_CCAP_DATA1 (0x07UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1121#define SYS_GPF_MFPH_PF8MFP_CAN1_RXD (0x08UL<<SYS_GPF_MFPH_PF8MFP_Pos)
1122#define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos)
1123#define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1124#define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1125#define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1126#define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1127#define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1128#define SYS_GPF_MFPH_PF9MFP_UART5_nRTS (0x06UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1129#define SYS_GPF_MFPH_PF9MFP_CCAP_DATA2 (0x07UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1130#define SYS_GPF_MFPH_PF9MFP_CAN1_TXD (0x08UL<<SYS_GPF_MFPH_PF9MFP_Pos)
1131#define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos)
1132#define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1133#define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1134#define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1135#define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1136#define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1137#define SYS_GPF_MFPH_PF10MFP_UART5_RXD (0x06UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1138#define SYS_GPF_MFPH_PF10MFP_CCAP_DATA3 (0x07UL<<SYS_GPF_MFPH_PF10MFP_Pos)
1139#define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos)
1140#define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos)
1141#define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos)
1142#define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos)
1143#define SYS_GPF_MFPH_PF11MFP_UART5_TXD (0x06UL<<SYS_GPF_MFPH_PF11MFP_Pos)
1144#define SYS_GPF_MFPH_PF11MFP_CCAP_DATA4 (0x07UL<<SYS_GPF_MFPH_PF11MFP_Pos)
1145#define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos)
1146#define SYS_GPF_MFPH_PF11MFP_TM3 (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos)
1147/********************* Bit definition of GPG_MFPL register **********************/
1148#define SYS_GPG_MFPL_PG0MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1149#define SYS_GPG_MFPL_PG0MFP_EBI_ADR8 (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1150#define SYS_GPG_MFPL_PG0MFP_I2C0_SCL (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1151#define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1152#define SYS_GPG_MFPL_PG0MFP_UART2_RXD (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1153#define SYS_GPG_MFPL_PG0MFP_CAN1_TXD (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1154#define SYS_GPG_MFPL_PG0MFP_UART1_TXD (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos)
1155#define SYS_GPG_MFPL_PG1MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1156#define SYS_GPG_MFPL_PG1MFP_EBI_ADR9 (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1157#define SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1158#define SYS_GPG_MFPL_PG1MFP_I2C0_SDA (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1159#define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1160#define SYS_GPG_MFPL_PG1MFP_UART2_TXD (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1161#define SYS_GPG_MFPL_PG1MFP_CAN1_RXD (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1162#define SYS_GPG_MFPL_PG1MFP_UART1_RXD (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos)
1163#define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1164#define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1165#define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1166#define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1167#define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1168#define SYS_GPG_MFPL_PG2MFP_CCAP_DATA7 (0x07UL<<SYS_GPG_MFPL_PG2MFP_Pos)
1169#define SYS_GPG_MFPL_PG2MFP_TM0 (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos)
1170#define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1171#define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1172#define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1173#define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1174#define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1175#define SYS_GPG_MFPL_PG3MFP_CCAP_DATA6 (0x07UL<<SYS_GPG_MFPL_PG3MFP_Pos)
1176#define SYS_GPG_MFPL_PG3MFP_TM1 (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos)
1177#define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos)
1178#define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos)
1179#define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos)
1180#define SYS_GPG_MFPL_PG4MFP_CCAP_DATA5 (0x07UL<<SYS_GPG_MFPL_PG4MFP_Pos)
1181#define SYS_GPG_MFPL_PG4MFP_TM2 (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos)
1182#define SYS_GPG_MFPL_PG5MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos)
1183#define SYS_GPG_MFPL_PG5MFP_EBI_nCS1 (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos)
1184#define SYS_GPG_MFPL_PG5MFP_SPI3_SS (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos)
1185#define SYS_GPG_MFPL_PG5MFP_SC1_PWR (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos)
1186#define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3 (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos)
1187#define SYS_GPG_MFPL_PG6MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos)
1188#define SYS_GPG_MFPL_PG6MFP_EBI_nCS2 (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos)
1189#define SYS_GPG_MFPL_PG6MFP_SPI3_CLK (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos)
1190#define SYS_GPG_MFPL_PG6MFP_SC1_RST (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos)
1191#define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2 (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos)
1192#define SYS_GPG_MFPL_PG7MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos)
1193#define SYS_GPG_MFPL_PG7MFP_EBI_nWRL (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos)
1194#define SYS_GPG_MFPL_PG7MFP_SPI3_MISO (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos)
1195#define SYS_GPG_MFPL_PG7MFP_SC1_DAT (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos)
1196#define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1 (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos)
1197/********************* Bit definition of GPG_MFPH register **********************/
1198#define SYS_GPG_MFPH_PG8MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos)
1199#define SYS_GPG_MFPH_PG8MFP_EBI_nWRH (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos)
1200#define SYS_GPG_MFPH_PG8MFP_SPI3_MOSI (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos)
1201#define SYS_GPG_MFPH_PG8MFP_SC1_CLK (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos)
1202#define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0 (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos)
1203#define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1204#define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1205#define SYS_GPG_MFPH_PG9MFP_SD1_DAT3 (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1206#define SYS_GPG_MFPH_PG9MFP_SPIM_D2 (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1207#define SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1 (0x05UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1208#define SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK (0x07UL<<SYS_GPG_MFPH_PG9MFP_Pos)
1209#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos)
1210#define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1211#define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1212#define SYS_GPG_MFPH_PG10MFP_SD1_DAT2 (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1213#define SYS_GPG_MFPH_PG10MFP_SPIM_D3 (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1214#define SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1 (0x05UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1215#define SYS_GPG_MFPH_PG10MFP_CCAP_SCLK (0x07UL<<SYS_GPG_MFPH_PG10MFP_Pos)
1216#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos)
1217#define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1218#define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1219#define SYS_GPG_MFPH_PG11MFP_SD1_DAT1 (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1220#define SYS_GPG_MFPH_PG11MFP_SPIM_SS (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1221#define SYS_GPG_MFPH_PG11MFP_QSPI1_SS (0x05UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1222#define SYS_GPG_MFPH_PG11MFP_UART7_TXD (0x06UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1223#define SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD (0x07UL<<SYS_GPG_MFPH_PG11MFP_Pos)
1224#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos)
1225#define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1226#define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1227#define SYS_GPG_MFPH_PG12MFP_SD1_DAT0 (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1228#define SYS_GPG_MFPH_PG12MFP_SPIM_CLK (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1229#define SYS_GPG_MFPH_PG12MFP_QSPI1_CLK (0x05UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1230#define SYS_GPG_MFPH_PG12MFP_UART7_RXD (0x06UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1231#define SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC (0x07UL<<SYS_GPG_MFPH_PG12MFP_Pos)
1232#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos)
1233#define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1234#define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1235#define SYS_GPG_MFPH_PG13MFP_SD1_CMD (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1236#define SYS_GPG_MFPH_PG13MFP_SPIM_MISO (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1237#define SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0 (0x05UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1238#define SYS_GPG_MFPH_PG13MFP_UART6_TXD (0x06UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1239#define SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC (0x07UL<<SYS_GPG_MFPH_PG13MFP_Pos)
1240#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos)
1241#define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1242#define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1243#define SYS_GPG_MFPH_PG14MFP_SD1_CLK (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1244#define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1245#define SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0 (0x05UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1246#define SYS_GPG_MFPH_PG14MFP_UART6_RXD (0x06UL<<SYS_GPG_MFPH_PG14MFP_Pos)
1247#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos)
1248#define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)
1249#define SYS_GPG_MFPH_PG15MFP_SD1_nCD (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos)
1250#define SYS_GPG_MFPH_PG15MFP_CLKO (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos)
1251#define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos)
1252/********************* Bit definition of GPH_MFPL register **********************/
1253#define SYS_GPH_MFPL_PH0MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos)
1254#define SYS_GPH_MFPL_PH0MFP_EBI_ADR7 (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos)
1255#define SYS_GPH_MFPL_PH0MFP_UART5_TXD (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos)
1256#define SYS_GPH_MFPL_PH0MFP_TM0_EXT (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos)
1257#define SYS_GPH_MFPL_PH1MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos)
1258#define SYS_GPH_MFPL_PH1MFP_EBI_ADR6 (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos)
1259#define SYS_GPH_MFPL_PH1MFP_UART5_RXD (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos)
1260#define SYS_GPH_MFPL_PH1MFP_TM1_EXT (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos)
1261#define SYS_GPH_MFPL_PH2MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos)
1262#define SYS_GPH_MFPL_PH2MFP_EBI_ADR5 (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos)
1263#define SYS_GPH_MFPL_PH2MFP_UART5_nRTS (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos)
1264#define SYS_GPH_MFPL_PH2MFP_UART4_TXD (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos)
1265#define SYS_GPH_MFPL_PH2MFP_I2C0_SCL (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos)
1266#define SYS_GPH_MFPL_PH2MFP_TM2_EXT (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos)
1267#define SYS_GPH_MFPL_PH3MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1268#define SYS_GPH_MFPL_PH3MFP_EBI_ADR4 (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1269#define SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1270#define SYS_GPH_MFPL_PH3MFP_UART5_nCTS (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1271#define SYS_GPH_MFPL_PH3MFP_UART4_RXD (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1272#define SYS_GPH_MFPL_PH3MFP_I2C0_SDA (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos)
1273#define SYS_GPH_MFPL_PH3MFP_TM3_EXT (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos)
1274#define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos)
1275#define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos)
1276#define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos)
1277#define SYS_GPH_MFPL_PH4MFP_UART7_nRTS (0x04UL<<SYS_GPH_MFPL_PH4MFP_Pos)
1278#define SYS_GPH_MFPL_PH4MFP_UART6_TXD (0x05UL<<SYS_GPH_MFPL_PH4MFP_Pos)
1279#define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos)
1280#define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos)
1281#define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos)
1282#define SYS_GPH_MFPL_PH5MFP_UART7_nCTS (0x04UL<<SYS_GPH_MFPL_PH5MFP_Pos)
1283#define SYS_GPH_MFPL_PH5MFP_UART6_RXD (0x05UL<<SYS_GPH_MFPL_PH5MFP_Pos)
1284#define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos)
1285#define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos)
1286#define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos)
1287#define SYS_GPH_MFPL_PH6MFP_UART7_TXD (0x04UL<<SYS_GPH_MFPL_PH6MFP_Pos)
1288#define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos)
1289#define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos)
1290#define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos)
1291#define SYS_GPH_MFPL_PH7MFP_UART7_RXD (0x04UL<<SYS_GPH_MFPL_PH7MFP_Pos)
1292/********************* Bit definition of GPH_MFPH register **********************/
1293#define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1294#define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1295#define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1296#define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1297#define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1298#define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1299#define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1300#define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1301#define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos)
1302#define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos)
1303#define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1304#define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1305#define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1306#define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1307#define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1308#define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1309#define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1310#define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1311#define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos)
1312#define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos)
1313#define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1314#define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1315#define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1316#define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1317#define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1318#define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1319#define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1320#define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos)
1321#define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos)
1322#define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos)
1323#define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos)
1324#define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos)
1325#define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos)
1326#define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /* end of group SYS_EXPORTED_CONSTANTS */
1329
1330
1343#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
1344
1353#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
1354
1363#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
1364
1373#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
1374
1383#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
1384
1394#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
1395
1404#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
1405
1414#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
1415
1424#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
1425
1442#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
1443
1452#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
1453
1462#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
1463
1472#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
1473
1482#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
1483
1492#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
1493
1502#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
1503
1512#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
1513
1522#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
1523
1532#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
1533
1542#define SYS_DISABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0x5AA5):(SYS->PORDISAN = 0x5AA5))
1543
1552#define SYS_ENABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0):(SYS->PORDISAN = 0))
1553
1569#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
1570
1571
1572/*---------------------------------------------------------------------------------------------------------*/
1573/* static inline functions */
1574/*---------------------------------------------------------------------------------------------------------*/
1575/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
1576__STATIC_INLINE void SYS_UnlockReg(void);
1577__STATIC_INLINE void SYS_LockReg(void);
1578
1586__STATIC_INLINE void SYS_UnlockReg(void)
1587{
1588 do
1589 {
1590 SYS->REGLCTL = 0x59UL;
1591 SYS->REGLCTL = 0x16UL;
1592 SYS->REGLCTL = 0x88UL;
1593 }
1594 while(SYS->REGLCTL == 0UL);
1595}
1596
1604__STATIC_INLINE void SYS_LockReg(void)
1605{
1606 SYS->REGLCTL = 0UL;
1607}
1608
1609
1610void SYS_ClearResetSrc(uint32_t u32Src);
1611uint32_t SYS_GetBODStatus(void);
1612uint32_t SYS_GetResetSrc(void);
1613uint32_t SYS_IsRegLocked(void);
1614uint32_t SYS_ReadPDID(void);
1615void SYS_ResetChip(void);
1616void SYS_ResetCPU(void);
1617void SYS_ResetModule(uint32_t u32ModuleIndex);
1618void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
1619void SYS_DisableBOD(void);
1620void SYS_SetPowerLevel(uint32_t u32PowerLevel);
1621void SYS_SetVRef(uint32_t u32VRefCTL);
1622 /* end of group SYS_EXPORTED_FUNCTIONS */
1624 /* end of group SYS_Driver */
1626 /* end of group Standard_Driver */
1628
1629
1630#ifdef __cplusplus
1631}
1632#endif
1633
1634#endif /* __SYS_H__ */
1635
1636/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
#define SYS
Definition: M480.h:367
void SYS_ResetCPU(void)
Reset chip with CPU reset.
Definition: sys.c:114
uint32_t SYS_GetBODStatus(void)
Get Brown-out detector output status.
Definition: sys.c:56
__STATIC_INLINE void SYS_LockReg(void)
Enable register write-protection function.
Definition: sys.h:1604
void SYS_SetVRef(uint32_t u32VRefCTL)
Set Reference Voltage.
Definition: sys.c:268
uint32_t SYS_GetResetSrc(void)
Get reset status register value.
Definition: sys.c:67
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
Enable and configure Brown-out detector function.
Definition: sys.c:216
void SYS_ResetModule(uint32_t u32ModuleIndex)
Reset selected module.
Definition: sys.c:184
uint32_t SYS_ReadPDID(void)
Get product ID.
Definition: sys.c:90
void SYS_SetPowerLevel(uint32_t u32PowerLevel)
Set Power Level.
Definition: sys.c:249
void SYS_DisableBOD(void)
Disable Brown-out detector function.
Definition: sys.c:235
uint32_t SYS_IsRegLocked(void)
Check if register is locked nor not.
Definition: sys.c:79
__STATIC_INLINE void SYS_UnlockReg(void)
Disable register write-protection function.
Definition: sys.h:1586
void SYS_ClearResetSrc(uint32_t u32Src)
Clear reset source.
Definition: sys.c:44
void SYS_ResetChip(void)
Reset chip with chip reset.
Definition: sys.c:102