Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
DMA_CRC_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t CTL
 
__IO uint32_t DMASAR
 
uint32_t RESERVE0 [1]
 
__IO uint32_t DMABCR
 
uint32_t RESERVE1 [1]
 
__I uint32_t DMACSAR
 
uint32_t RESERVE2 [1]
 
__I uint32_t DMACBCR
 
__IO uint32_t DMAIER
 
__IO uint32_t DMAISR
 
uint32_t RESERVE3 [22]
 
__IO uint32_t WDATA
 
__IO uint32_t SEED
 
__I uint32_t CHECKSUM
 

Detailed Description

@addtogroup DMA Direct Memory Access Controller(DMA)
Memory Mapped Structure for DMA Controller

Definition at line 1719 of file Nano1X2Series.h.

Field Documentation

◆ CHECKSUM

__I uint32_t DMA_CRC_T::CHECKSUM

CHECKSUM

Offset: 0x88 DMA CRC Check Sum Register

Bits Field Descriptions
[31:0] CRC_CHECKSUM CRC Checksum Register
This field indicates the CRC checksum

Definition at line 1912 of file Nano1X2Series.h.

◆ CTL

__IO uint32_t DMA_CRC_T::CTL

CTL

Offset: 0x00 DMA CRC Control Register

Bits Field Descriptions
[0] CRCCEN CRC Channel Enable
Setting this bit to 1 enables CRC's operation.
When operating in CRC DMA mode (TRIG_EN = 1), if user clear this bit, the DMA operation will be continuous until all CRC DMA operation done, and the TRIG_EN bit will asserted until all CRC DMA operation done.
But in this case, the CRC_DMAISR [BLKD_IF] flag will inactive, user can read CRC result by reading CRC_CHECKSUM register when TRIG_EN = 0.
When operating in CRC DMA mode (TRIG_EN = 1), if user want to stop the transfer immediately, user can write 1 to CRC_RST bit to stop the transmission.
[1] CRC_RST CRC Engine Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal CRC state machine and internal buffer.
The contents of control register will not be cleared.
This bit will be auto cleared after few clock cycles.
Note: When operating in CPU PIO mode, setting this bit will reload the initial seed value
[23] TRIG_EN Trigger Enable
0 = No effect.
1 = CRC DMA data read or write transfer Enabled.
Note1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register.
Note2: When CRC DMA transfer completed, this bit will be cleared automatically.
Note3: If the bus error occurs, all CRC DMA transfer will be stopped.
Software must reset all DMA channel, and then trigger again.
[24] WDATA_RVS Write Data Order Reverse
0 = No bit order reverse for CRC write data in.
1 = Bit order reverse for CRC write data in (per byre).
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
[25] CHECKSUM_RVS Checksum Reverse
0 = No bit order reverse for CRC checksum.
1 = Bit order reverse for CRC checksum.
Note: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
[26] WDATA_COM Write Data Complement
0 = No bit order reverse for CRC write data in.
1 = 1's complement for CRC write data in.
[27] CHECKSUM_COM Checksum Complement
0 = No bit order reverse for CRC checksum.
1 = 1's complement for CRC checksum.
[29:28] CPU_WDLEN CPU Write Data Length
When operating in CPU PIO mode (CRCCEN= 1, TRIG_EN = 0), this field indicates the write data length.
00 = The data length is 8-bit mode
01 = The data length is 16-bit mode
10 = The data length is 32-bit mode
11 = Reserved
Note1: This field is only used for CPU PIO mode.
Note2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0], and if the data length is 16 bit mode, the valid data is CRC_WDATA [15:0].
[31:30] CRC_MODE CRC Polynomial Mode
00 = CRC-CCITT Polynomial Mode
01 = CRC-8 Polynomial Mode
10 = CRC-16 Polynomial Mode
11 = CRC-32 Polynomial Mode

Definition at line 1776 of file Nano1X2Series.h.

◆ DMABCR

__IO uint32_t DMA_CRC_T::DMABCR

DMABCR

Offset: 0x0C DMA CRC Transfer Byte Count Register

Bits Field Descriptions
[15:0] CRC_DMABCR CRC DMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of CRC DMA

Definition at line 1803 of file Nano1X2Series.h.

◆ DMACBCR

__I uint32_t DMA_CRC_T::DMACBCR

DMACBCR

Offset: 0x1C DMA CRC Current Transfer Byte Count Register

Bits Field Descriptions
[15:0] CRC_DMACBCR CRC DMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of CRC_DMA.
Note: CRC_RST will clear this register value.

Definition at line 1832 of file Nano1X2Series.h.

◆ DMACSAR

__I uint32_t DMA_CRC_T::DMACSAR

DMACSAR

Offset: 0x14 DMA CRC Current Source Address Register

Bits Field Descriptions
[31:0] CRC_DMACSAR CRC DMA Current Source Address Register (Read Only)
This field indicates the source address where the CRC DMA transfer is just occurring.

Definition at line 1817 of file Nano1X2Series.h.

◆ DMAIER

__IO uint32_t DMA_CRC_T::DMAIER

DMAIER

Offset: 0x20 DMA CRC Interrupt Enable Register

Bits Field Descriptions
[0] TABORT_IE CRC DMA Read/Write Target Abort Interrupt Enable
0 = Target abort interrupt generation Disabled during CRC DMA transfer.
1 = Target abort interrupt generation Enabled during CRC DMA transfer.
[1] BLKD_IE CRC DMA Transfer Done Interrupt Enable
0 = Interrupt generator Disabled during CRC DMA transfer done.
1 = Interrupt generator Enabled during CRC DMA transfer done.

Definition at line 1848 of file Nano1X2Series.h.

◆ DMAISR

__IO uint32_t DMA_CRC_T::DMAISR

DMAISR

Offset: 0x24 DMA CRC Interrupt Status Register

Bits Field Descriptions
[0] TABORT_IF CRC DMA Read/Write Target Abort Interrupt Flag
0 = No bus ERROR response received.
1 = Bus ERROR response received.
Software can write 1 to clear this bit to zero
Note: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not.
If bus master received ERROR response, it means that target abort is happened.
DMA will stop transfer and respond this event to software then go to IDLE state.
When target abort occurred, software must reset DMA, and then transfer those data again.
[1] BLKD_IF Block Transfer Done Interrupt Flag
This bit indicates that CRC DMA has finished all transfer.
0 = Not finished yet.
1 = Done.
Software can write 1 to clear this bit to zero

Definition at line 1871 of file Nano1X2Series.h.

◆ DMASAR

__IO uint32_t DMA_CRC_T::DMASAR

DMASAR

Offset: 0x04 DMA CRC Source Address Register

Bits Field Descriptions
[31:0] CRC_DMASAR CRC DMA Transfer Source Address Register
This field indicates a 32-bit source address of CRC DMA.
Note : The source address must be word alignment

Definition at line 1789 of file Nano1X2Series.h.

◆ RESERVE0

uint32_t DMA_CRC_T::RESERVE0[1]

Definition at line 1790 of file Nano1X2Series.h.

◆ RESERVE1

uint32_t DMA_CRC_T::RESERVE1[1]

Definition at line 1804 of file Nano1X2Series.h.

◆ RESERVE2

uint32_t DMA_CRC_T::RESERVE2[1]

Definition at line 1818 of file Nano1X2Series.h.

◆ RESERVE3

uint32_t DMA_CRC_T::RESERVE3[22]

Definition at line 1872 of file Nano1X2Series.h.

◆ SEED

__IO uint32_t DMA_CRC_T::SEED

SEED

Offset: 0x84 DMA CRC Seed Register

Bits Field Descriptions
[31:0] CRC_SEED CRC Seed Register
This field indicates the CRC seed value.

Definition at line 1900 of file Nano1X2Series.h.

◆ WDATA

__IO uint32_t DMA_CRC_T::WDATA

WDATA

Offset: 0x80 DMA CRC Write Data Register

Bits Field Descriptions
[31:0] CRC_WDATA CRC Write Data Register
When operating in CPU PIO (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0) mode, software can write data to this field to perform CRC operation;.
When operating in CRC DMA mode (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0), this field will be used for DMA internal buffer.
Note1: When operating in CRC DMA mode, so don't filled any data in this field.
Note2:The CRC_CTL [WDATA_COM] and CRC_CTL [WDATA_RVS] bit setting will affected this field; For example, if WDATA_RVS = 1, if the write data in CRC_WDATA register is 0xAABBCCDD, the read data from CRC_WDATA register will be 0x55DD33BB

Definition at line 1888 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: