Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
WDT_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t CTL
 
__IO uint32_t IER
 
__IO uint32_t ISR
 

Detailed Description

@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller

Definition at line 10305 of file Nano1X2Series.h.

Field Documentation

◆ CTL

__IO uint32_t WDT_T::CTL

CTL

Offset: 0x00 Watchdog Timer Control Register

Bits Field Descriptions
[0] WTR Clear Watchdog Timer
This is a protected register. Please refer to open lock sequence to program it.
Set this bit will clear the Watchdog timer.
0 = No effect.
1 = Reset the contents of the Watchdog timer.
Note: This bit will be auto cleared after few clock cycles.
[1] WTRE Watchdog Timer Reset Function Enable
This is a protected register. Please refer to open lock sequence to program it.
Setting this bit will enable the Watchdog timer reset function.
0 = Watchdog timer reset function Disabled.
1 = Watchdog timer reset function Enabled.
[2] WTWKE Watchdog Timer Wake-Up Function Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Watchdog timer Wake-up CPU function Disabled.
1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode.
[3] WTE Watchdog Timer Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Watchdog timer Disabled (this action will reset the internal counter).
1 = Watchdog timer Enabled.
[6:4] WTIS Watchdog Timer Interval Selection
This is a protected register. Please refer to open lock sequence to program it.
These three bits select the time-out interval for the Watchdog timer.
This count is free running counter.
[9:8] WTRDSEL Watchdog Timer Reset Delay Select
When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened.
Software can select a suitable value of watchdog reset delay period for different watchdog timeout period.
00 = Watchdog reset delay period is 1026 watchdog clock
01 = Watchdog reset delay period is 130 watchdog clock
10 = Watchdog reset delay period is 18 watchdog clock
11 = Watchdog reset delay period is 3 watchdog clock
This register will be reset if watchdog reset happened

Definition at line 10348 of file Nano1X2Series.h.

◆ IER

__IO uint32_t WDT_T::IER

IER

Offset: 0x04 Watchdog Timer Interrupt Enable Register

Bits Field Descriptions
[0] WDT_IE Watchdog Timer Interrupt Enable
0 = Watchdog timer interrupt Disabled.
1 = Watchdog timer interrupt Enabled.

Definition at line 10361 of file Nano1X2Series.h.

◆ ISR

__IO uint32_t WDT_T::ISR

ISR

Offset: 0x08 Watchdog Timer Interrupt Status Register

Bits Field Descriptions
[0] IS Watchdog Timer Interrupt Status
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.
If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed.
0 = Watchdog timer interrupt did not occur.
1 = Watchdog timer interrupt occurs.
Note: This bit is read only, but can be cleared by writing "1" to it.
[1] RST_IS Watchdog Timer Reset Status
When the Watchdog timer initiates a reset, the hardware will set this bit.
This flag can be read by software to determine the source of reset.
Software is responsible to clear it manually by writing "1" to it.
If WTRE is disabled, then the Watchdog timer has no effect on this bit.
0 = Watchdog timer reset did not occur.
1 = Watchdog timer reset occurs.
Note: This bit is read only, but can be cleared by writing "1" to it.
[2] WAKE_IS Watchdog Timer Wake-Up Status
If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high.
It must be cleared by software with a write "1" to this bit.
0 = Watchdog timer does not cause system wake-up.
1 = Wake system up from power-down mode by Watchdog time-out.
Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS.
Note2: After one engine clock, this bit can be cleared by writing "1" to it

Definition at line 10392 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: