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Nano102_112 Series BSP
V3.03.002
The Board Support Package for Nano102_112 Series
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Macros | |
#define | SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) |
#define | SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) |
#define | SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) |
#define | SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) |
#define | SPI_SLAVE (SPI_CTL_SLAVE_Msk) |
#define | SPI_MASTER (0x0) |
#define | SPI_SS0 (0x1) |
#define | SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) |
#define | SPI_SS0_ACTIVE_LOW (0x0) |
#define | SPI_SS1 (0x2) |
#define | SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) |
#define | SPI_SS1_ACTIVE_LOW (0x0) |
#define | SPI_IE_MASK (0x01) |
#define | SPI_SSTA_INTEN_MASK (0x04) |
#define | SPI_FIFO_TX_INTEN_MASK (0x08) |
#define | SPI_FIFO_RX_INTEN_MASK (0x10) |
#define | SPI_FIFO_RXOVR_INTEN_MASK (0x20) |
#define | SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) |
#define SPI_FIFO_RXOVR_INTEN_MASK (0x20) |
#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) |
#define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) |
#define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) |
#define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) |
#define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) |
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) |
#define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) |
#define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) |