#include <Nano1X2Series.h>
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__IO uint32_t | INIR |
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__O uint32_t | AER |
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__IO uint32_t | FCR |
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__IO uint32_t | TLR |
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__IO uint32_t | CLR |
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__IO uint32_t | TSSR |
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__IO uint32_t | DWR |
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__IO uint32_t | TAR |
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__IO uint32_t | CAR |
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__I uint32_t | LIR |
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__IO uint32_t | RIER |
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__IO uint32_t | RIIR |
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__IO uint32_t | TTR |
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uint32_t | RESERVE0 [2] |
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__IO uint32_t | SPRCTL |
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__IO uint32_t | SPR [20] |
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@addtogroup RTC Real Time Clock Controller(RTC)
Memory Mapped Structure for RTC Controller
Definition at line 7071 of file Nano1X2Series.h.
◆ AER
AER
Offset: 0x04 RTC Access Enable Register
Bits | Field | Descriptions |
[15:0] | AER | RTC Register Access Enable Password (Write Only) |
| | Enable RTC access after write 0xA965. Otherwise disable RTC access. |
[16] | ENF | RTC Register Access Enable Flag (Read Only) |
| | 0 = RTC register read/write disable. |
| | 1 = RTC register read/write enable. |
| | This bit will be set after AER[15:0] register is load a 0xA965, and be clear automatically 512 RTC clocks or AER[15:0] is not 0xA965. |
Definition at line 7107 of file Nano1X2Series.h.
◆ CAR
CAR
Offset: 0x20 Calendar Alarm Register
Bits | Field | Descriptions |
[3:0] | 1DAY | 1 Day Calendar Digit of Alarm Setting (0~9) |
[5:4] | 10DAY | 10 Day Calendar Digit of Alarm Setting (0~3) |
[11:8] | 1MON | 1 Month Calendar Digit of Alarm Setting (0~9) |
[12] | 10MON | 10 Month Calendar Digit of Alarm Setting (0~1) |
[19:16] | 1YEAR | 1 Year Calendar Digit of Alarm Setting (0~9) |
[23:20] | 10YEAR | 10 Year Calendar Digit of Alarm Setting (0~9) |
Definition at line 7216 of file Nano1X2Series.h.
◆ CLR
CLR
Offset: 0x10 Calendar Loading Register
Bits | Field | Descriptions |
[3:0] | 1DAY | 1 Day Calendar Digit (0~9) |
[5:4] | 10DAY | 10 Day Calendar Digit (0~3) |
[11:8] | 1MON | 1 Month Calendar Digit (0~9) |
[12] | 10MON | 10 Month Calendar Digit (0~1) |
[19:16] | 1YEAR | 1 Year Calendar Digit (0~9) |
[23:20] | 10YEAR | 10 Year Calendar Digit (0~9) |
Definition at line 7152 of file Nano1X2Series.h.
◆ DWR
DWR
Offset: 0x18 Day of the Week Register
Bits | Field | Descriptions |
[2:0] | DWR | Day Of The Week Register |
| | 000 = Sunday. |
| | 001 = Monday. |
| | 010 = Tuesday. |
| | 011 = Wednesday. |
| | 100 = Thursday. |
| | 101 = Friday. |
| | 110 = Saturday. |
Definition at line 7184 of file Nano1X2Series.h.
◆ FCR
FCR
Offset: 0x08 RTC Frequency Compensation Register
Bits | Field | Descriptions |
[21:0] | FCR | Frequency Compensation Register |
| | FCR = 32768 * 0x200000 / (LXT period). |
| | LXT period: the clock period (Hz) of LXT. |
Definition at line 7120 of file Nano1X2Series.h.
◆ INIR
__IO uint32_t RTC_T::INIR |
INIR
Offset: 0x00 RTC Initiation Register
Bits | Field | Descriptions |
[0] | ACTIVE | RTC Active Status (Read Only) |
| | 0 = RTC is at reset state. |
| | 1 = RTC is at normal active state. |
[31:1] | INIR | RTC Initiation (Write Only) |
| | When RTC block is powered on, RTC is at reset state. |
| | User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. |
| | Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. |
| | The INIR is a write-only field and read value will be always "0". |
Definition at line 7091 of file Nano1X2Series.h.
◆ LIR
LIR
Offset: 0x24 Leap Year Indicator Register
Bits | Field | Descriptions |
[0] | LIR | Leap Year Indication REGISTER (Read Only) |
| | 0 = This year is not a leap year. |
| | 1 = This year is leap year. |
Definition at line 7229 of file Nano1X2Series.h.
◆ RESERVE0
uint32_t RTC_T::RESERVE0[2] |
◆ RIER
__IO uint32_t RTC_T::RIER |
RIER
Offset: 0x28 RTC Interrupt Enable Register
Bits | Field | Descriptions |
[0] | AIER | Alarm Interrupt Enable |
| | 0 = RTC Alarm Interrupt is disabled. |
| | 1 = RTC Alarm Interrupt is enabled. |
[1] | TIER | Time Tick Interrupt And Wake-Up By Tick Enable |
| | 0 = RTC Time Tick Interrupt is disabled. |
| | 1 = RTC Time Tick Interrupt is enabled. |
[2] | SNOOPIER | Snooper Pin Event Detection Interrupt Enable |
| | 0 = Snooper Pin Event Detection Interrupt is disabled. |
| | 1 = Snooper Pin Event Detection Interrupt is enabled. |
Definition at line 7248 of file Nano1X2Series.h.
◆ RIIR
__IO uint32_t RTC_T::RIIR |
RIIR
Offset: 0x2C RTC Interrupt Indication Register
Bits | Field | Descriptions |
[0] | AIS | RTC Alarm Interrupt Status |
| | RTC unit will set AIS to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. |
| | When this bit is set and AIER is also high, RTC will generate an interrupt to CPU. |
| | This bit is cleared by writing "1" to it through software. |
| | 0 = RCT Alarm Interrupt condition never occurred. |
| | 1 = RTC Alarm Interrupt is requested if AIER (RTC_RIER[0])=1. |
[1] | TIS | RTC Time Tick Interrupt Status |
| | RTC unit will set this bit to high periodically in the period selected by TTR (RTC_TTR[2:0]). |
| | When this bit is set and TIER (RTC_RIER[1]) is also high, RTC will generate an interrupt to CPU. |
| | This bit is cleared by writing "1" to it through software. |
| | 0 = RCT Time Tick Interrupt condition never occurred. |
| | 1 = RTC Time Tick Interrupt is requested. |
[2] | SNOOPIF | Snooper Pin Event Detection Interrupt Flag |
| | When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set. |
| | While this bit is set and SNOOPIER (RTC_RIER[2]) is also high, RTC will generate an interrupt to CPU. |
| | Write "1" to clear this bit to "0". |
| | 0 = Snooper pin event defined by SNOOPEDGE (RTC_SPRCTL[1]) never detected. |
| | 1 = Snooper pin event defined by SNOOPEDGE (RTC_SPRCTL[1]) detected. |
Definition at line 7276 of file Nano1X2Series.h.
◆ SPR
__IO uint32_t RTC_T::SPR[20] |
SPR0
Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
Bits | Field | Descriptions |
[31:0] | SPARE | SPARE |
| | This field is used to store back-up information defined by software. |
| | This field will be cleared by hardware automatically once a snooper pin event is detected. |
Definition at line 7338 of file Nano1X2Series.h.
◆ SPRCTL
__IO uint32_t RTC_T::SPRCTL |
SPRCTL
Offset: 0x3C RTC Spare Functional Control Register
Bits | Field | Descriptions |
[0] | SNOOPEN | Snooper Pin Event Detection Enable |
| | This bit enables the snooper pin event detection. |
| | When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to "0" by hardware automatically. |
| | And, the SNOOPIF will also be set. |
| | In addition, RTC will also generate wake-up event to wake system up. |
| | 0 = Snooper pin event detection function Disabled. |
| | 1 = Snooper pin event detection function Enabled. |
[1] | SNOOPEDGE | Snooper Active Edge Selection |
| | This bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers. |
| | 0 = Rising edge of snooper pin generates snooper pin detected event. |
| | 1 = Falling edge of snooper pin generates snooper pin detected event. |
Definition at line 7325 of file Nano1X2Series.h.
◆ TAR
TAR
Offset: 0x1C Time Alarm Register
Bits | Field | Descriptions |
[3:0] | 1SEC | 1 Sec Time Digit of Alarm Setting (0~9) |
[6:4] | 10SEC | 10 Sec Time Digit of Alarm Setting (0~5) |
[11:8] | 1MIN | 1 Min Time Digit of Alarm Setting (0~9) |
[14:12] | 10MIN | 10 Min Time Digit of Alarm Setting (0~5) |
[19:16] | 1HR | 1 Hour Time Digit of Alarm Setting (0~9) |
[21:20] | 10HR | 10 Hour Time Digit of Alarm Setting (0~2) |
Definition at line 7200 of file Nano1X2Series.h.
◆ TLR
TLR
Offset: 0x0C Time Loading Register
Bits | Field | Descriptions |
[3:0] | 1SEC | 1 Sec Time Digit (0~9) |
[6:4] | 10SEC | 10 Sec Time Digit (0~5) |
[11:8] | 1MIN | 1 Min Time Digit (0~9) |
[14:12] | 10MIN | 10 Min Time Digit (0~5) |
[19:16] | 1HR | 1 Hour Time Digit (0~9) |
[21:20] | 10HR | 10 Hour Time Digit (0~2) |
Definition at line 7136 of file Nano1X2Series.h.
◆ TSSR
__IO uint32_t RTC_T::TSSR |
TSSR
Offset: 0x14 Time Scale Selection Register
Bits | Field | Descriptions |
[0] | 24hr_12hr | 24-Hour / 12-Hour Mode Selection |
| | It indicates that TLR and TAR are in 24-hour mode or 12-hour mode |
| | 0 = select 12-hour time scale with AM and PM indication. |
| | 1 = select 24-hour time scale. |
Definition at line 7166 of file Nano1X2Series.h.
◆ TTR
TTR
Offset: 0x30 RTC Time Tick Register
Bits | Field | Descriptions |
[2:0] | TTR | Time Tick Register |
| | The RTC time tick period for Periodic Time Tick Interrupt request. |
| | 000 = 1 tick/second. |
| | 001 = 1/2 tick/second. |
| | 010 = 1/4 tick/second. |
| | 011 = 1/8 tick/second. |
| | 100 = 1/16 tick/second. |
| | 101 = 1/32 tick/second. |
| | 110 = 1/64 tick/second. |
| | 111 = 1/128 tick/second. |
| | Note: This register can be read back after the RTC is active by AER. |
[3] | TWKE | RTC Timer Wake-Up CPU Function Enable |
| | If TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit. |
| | 0 = Time Tick wake-up CPU function Disabled. |
| | 1 = Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick. |
| | Note: Tick timer setting follows the TTR ( RTC_TTR[2:0]) description. |
Definition at line 7302 of file Nano1X2Series.h.
The documentation for this struct was generated from the following file: