Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
GPIO_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t PMD
 
__IO uint32_t OFFD
 
__IO uint32_t DOUT
 
__IO uint32_t DMASK
 
__I uint32_t PIN
 
__IO uint32_t DBEN
 
__IO uint32_t IMD
 
__IO uint32_t IER
 
__IO uint32_t ISRC
 
__IO uint32_t PUEN
 

Detailed Description

@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller

Definition at line 4074 of file Nano1X2Series.h.

Field Documentation

◆ DBEN

__IO uint32_t GPIO_T::DBEN

DBEN

Offset: 0x14 GPIO Port De-bounce Enable Register

Bits Field Descriptions
[15:0] DBEN GPIO Port [X] Pin [N] Input Signal De-Bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
0 = The GPIO port [x] Pin [n] input signal de-bounce function is disabled.
1 = The GPIO port [x] Pin [n] input signal de-bounce function is enabled.
The de-bounce function is valid for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.

Definition at line 4294 of file Nano1X2Series.h.

◆ DMASK

__IO uint32_t GPIO_T::DMASK

DMASK

Offset: 0x0C GPIO Port Data Output Write Mask Register

Bits Field Descriptions
[15:0] DMASK GPIO Port [X] Pin [N] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n].
When set the DMASK[n] to "1", the corresponding DOUT[n] bit is protected.
The write signal is masked, write data to the protect bit is ignored.
0 = The corresponding GPIO_DOUT bit [n] can be updated.
1 = The corresponding GPIO_DOUT bit [n] is protected.
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT.
If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.

Definition at line 4262 of file Nano1X2Series.h.

◆ DOUT

__IO uint32_t GPIO_T::DOUT

DOUT

Offset: 0x08 GPIO Port Data Output Value Register

Bits Field Descriptions
[15:0] DOUT GPIO Port [X] Pin [N] Output Value
Each of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode
0 = GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set.
1 = GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set.
Note: For GPIOF_DOUT, bits [15:6] are reserved.

Definition at line 4243 of file Nano1X2Series.h.

◆ IER

__IO uint32_t GPIO_T::IER

IER

Offset: 0x1C GPIO Port Interrupt Enable Register

Bits Field Descriptions
[0] FIER0 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[1] FIER1 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[2] FIER2 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[3] FIER3 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[4] FIER4 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[5] FIER5 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[6] FIER6 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[7] FIER7 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[8] FIER8 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[9] FIER9 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[10] FIER10 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[11] FIER11 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[12] FIER12 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[13] FIER13 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[14] FIER14 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[15] FIER15 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
Set bit "1" also enable the pin wake-up function.
When set the FIER[n] bit "1":
If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
Note: For GPIOF_IER, bits [15:6] are reserved.
[16] RIER0 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[17] RIER1 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[18] RIER2 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[19] RIER3 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[20] RIER4 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[21] RIER5 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[22] RIER6 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[23] RIER7 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[24] RIER8 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[25] RIER9 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[26] RIER10 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[27] RIER11 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[28] RIER12 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[29] RIER13 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[30] RIER14 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.
[31] RIER15 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
Set bit "1" also enable the pin wake-up function.
When set the RIER[x] bit "1":
If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
1 = PIN[x] level-high or low-to-high interrupt Enabled.
0 = PIN[x] level-high or low-to-high interrupt Disabled.
Note: For GPIOF_IE, bits [31:22] are reserved.

Definition at line 4613 of file Nano1X2Series.h.

◆ IMD

__IO uint32_t GPIO_T::IMD

IMD

Offset: 0x18 GPIO Port Interrupt Mode Control Register

Bits Field Descriptions
[15:0] IMD GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control
IMD[n] used to control the interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source is control de-bounce.
If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER.
If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
The de-bounce function is valid for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_IMD, bits [15:6] are reserved.

Definition at line 4315 of file Nano1X2Series.h.

◆ ISRC

__IO uint32_t GPIO_T::ISRC

ISRC

Offset: 0x20 GPIO Port Interrupt Trigger Source Status Register

Bits Field Descriptions
[15:0] ISRC GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator
Read :
1 = Port x[n] generate an interrupt.
0 = No interrupt at Port x[n].
Write:
1 = Clear the correspond pending interrupt.
0 = No action.
Note: For GPIOF_ISRC, bits [15:6] are reserved.

Definition at line 4631 of file Nano1X2Series.h.

◆ OFFD

__IO uint32_t GPIO_T::OFFD

OFFD

Offset: 0x04 GPIO Port Pin OFF Digital Enable Register

Bits Field Descriptions
[31:16] OFFD GPIO Port [X] Pin [N] Digital Input Path Disable
Determine if the digital input path of GPIO port [x] pin [n] is disabled.
0 = Digital input path of GPIO port [x] pin [n] Enabled.
1 = Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low).
Note: For GPIOF_OFFD, bits [31:22] are reserved.

Definition at line 4228 of file Nano1X2Series.h.

◆ PIN

__I uint32_t GPIO_T::PIN

PIN

Offset: 0x10 GPIO Port Pin Value Register

Bits Field Descriptions
[15:0] PIN GPIO Port [X] Pin [N] Value
The value read from each of these bit reflects the actual status of the respective GPI/O pin
Note: For GPIOF_PIN, bits [15:6] are reserved.

Definition at line 4275 of file Nano1X2Series.h.

◆ PMD

__IO uint32_t GPIO_T::PMD

PMD

Offset: 0x00 GPIO Port Pin I/O Mode Control Register

Bits Field Descriptions
[1:0] PMD0 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[3:2] PMD1 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[5:4] PMD2 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[7:6] PMD3 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[9:8] PMD4 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[11:10] PMD5 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[13:12] PMD6 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[15:14] PMD7 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[17:16] PMD8 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[19:18] PMD9 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[21:20] PMD10 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[23:22] PMD11 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[25:24] PMD12 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[27:26] PMD13 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[29:28] PMD14 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
[31:30] PMD15 GPIO Port [X] Pin [N] Mode Control
Determine the I/O type of GPIO port [x] pin [n]
00 = GPIO port [x] pin [n] is in INPUT mode.
01 = GPIO port [x] pin [n] is in OUTPUT mode.
10 = GPIO port [x] pin [n] is in Open-Drain mode.
11 = Reserved.
Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
For GPIOF_PMD, PMD6 ~ PMD15 are reserved.

Definition at line 4213 of file Nano1X2Series.h.

◆ PUEN

__IO uint32_t GPIO_T::PUEN

PUEN

Offset: 0x24 GPIO Port Pull-Up Enable Register

Bits Field Descriptions
[15:0] PUEN GPIO Port [X] Pin [N] Pull-Up Enable Register
Read :
1 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled.
0 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled.
Note: For GPIOF_PUEN, bits [15:6] are reserved.

Definition at line 4646 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: