Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
system_Nano1X2Series.c
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1 /******************************************************************************
2  * @file system_Nano1X2Series.c
3  * @version V1.00
4  * $Revision: 6 $
5  * $Date: 13/12/16 4:27p $
6  * @brief Nano1X2 series system clock init code and assert handler
7  *
8  * @note
9  * SPDX-License-Identifier: Apache-2.0
10  * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
11 *****************************************************************************/
12 
13 #include <stdint.h>
14 #include "Nano1X2Series.h"
15 
16 
17 /*----------------------------------------------------------------------------
18  Clock Variable definitions
19  *----------------------------------------------------------------------------*/
20 uint32_t SystemCoreClock = __HSI;
21 uint32_t CyclesPerUs = (__HSI / 1000000);
28 uint32_t SysGet_PLLClockFreq(void)
29 {
30  uint32_t u32Freq =0, u32PLLSrc;
31  uint32_t u32SRC_N,u32PLL_M,u32PllReg;
32 
33  u32PllReg = CLK->PLLCTL;
34 
35  if (u32PllReg & CLK_PLLCTL_PD)
36  return 0; /* PLL is in power down mode */
37 
38  if (u32PllReg & CLK_PLLCTL_PLL_SRC_HIRC)
39  {
40  if(CLK->PLLCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
41  u32PLLSrc =__HIRC16M;
42  else
43  u32PLLSrc =__HIRC12M;
44  }
45  else
46  u32PLLSrc = __HXT;
47 
48  u32SRC_N = (u32PllReg & CLK_PLLCTL_PLL_SRC_N_Msk) >> CLK_PLLCTL_PLL_SRC_N_Pos;
49  u32PLL_M = (u32PllReg & CLK_PLLCTL_PLL_MLP_Msk) >> CLK_PLLCTL_PLL_MLP_Pos;
50 
51  u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
52 
53  return u32Freq;
54 }
55 
56 
62 uint32_t SysGet_HCLKFreq(void)
63 {
64 
65  uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
66 
67  u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
68 
69  if (u32ClkSel == CLK_CLKSEL0_HCLK_S_HXT) /* external HXT crystal clock */
70  {
71  u32Freqout = __HXT;
72  }
73  else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LXT) /* external LXT crystal clock */
74  {
75  u32Freqout = __LXT;
76  }
77  else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_PLL) /* PLL clock */
78  {
79  u32Freqout = SysGet_PLLClockFreq();
80  }
81  else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LIRC) /* internal LIRC oscillator clock */
82  {
83  u32Freqout = __LIRC;
84  }
85  else /* internal HIRC oscillator clock */
86  {
88  u32Freqout = __HIRC16M;
89  else
90  u32Freqout = __HIRC12M;
91 
92  }
93  u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_N_Msk) + 1 ;
94 
95  return (u32Freqout/u32AHBDivider);
96 }
97 
98 
107 {
108 
110  CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
111 }
112 
113 #if USE_ASSERT
114 
126 void AssertError(uint8_t * file, uint32_t line)
127 {
128 
129  printf("[%s] line %d : wrong parameters.\r\n", file, line);
130 
131  /* Infinite loop */
132  while(1) ;
133 }
134 #endif
135 
136 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
#define CLK_PLLCTL_PLL_SRC_N_Pos
#define __HSI
#define CLK
Pointer to CLK register structure.
#define CLK_PLLCTL_PLL_MLP_Msk
#define __LIRC
uint32_t SysGet_PLLClockFreq(void)
Calculate current PLL clock frequency.
#define __LXT
#define CLK_PWRCTL_HIRC_FSEL_Msk
void SystemCoreClockUpdate(void)
This function is used to update the variable SystemCoreClock and must be called whenever the core clo...
#define __HIRC16M
#define __HIRC12M
#define CLK_CLKSEL0_HCLK_S_PLL
Definition: clk.h:124
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
#define CLK_CLKSEL0_HCLK_S_Msk
#define CLK_PLLCTL_PLL_MLP_Pos
uint32_t CyclesPerUs
#define CLK_CLKSEL0_HCLK_S_LIRC
Definition: clk.h:125
#define CLK_PLLCTL_PD
Definition: clk.h:97
uint32_t SysGet_HCLKFreq(void)
Get current HCLK clock frequency.
#define CLK_PLLCTL_PLL_SRC_HIRC
Definition: clk.h:99
#define CLK_PLLCTL_PLL_SRC_N_Msk
#define CLK_CLKSEL0_HCLK_S_HXT
Definition: clk.h:122
#define CLK_CLKSEL0_HCLK_S_LXT
Definition: clk.h:123
#define __HXT
#define CLK_CLKDIV0_HCLK_N_Msk
uint32_t SystemCoreClock