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Nano102_112 Series BSP
V3.03.002
The Board Support Package for Nano102_112 Series
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Nano102/112 series CLK driver header file. More...
Go to the source code of this file.
Macros | |
#define | FREQ_32MHZ 32000000 |
#define | FREQ_16MHZ 16000000 |
#define | CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001) |
#define | CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002) |
#define | CLK_PWRCTL_HIRC_EN ((uint32_t)0x00000004) |
#define | CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008) |
#define | CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010) |
#define | CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020) |
#define | CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040) |
#define | CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100) |
#define | CLK_PWRCTL_HXT_GAIN_8M ((uint32_t)0x00000000) |
#define | CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000400) |
#define | CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000800) |
#define | CLK_PWRCTL_HXT_GAIN_16M ((uint32_t)0x00000C00) |
#define | CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001) |
#define | CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002) |
#define | CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004) |
#define | CLK_AHBCLK_EBI_EN ((uint32_t)0x00000008) |
#define | CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010) |
#define | CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020) |
#define | CLK_APBCLK_WDT_EN ((uint32_t)0x00000001) |
#define | CLK_APBCLK_RTC_EN ((uint32_t)0x00000002) |
#define | CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004) |
#define | CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008) |
#define | CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010) |
#define | CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020) |
#define | CLK_APBCLK_FDIV_EN ((uint32_t)0x00000040) |
#define | CLK_APBCLK_SC2_EN ((uint32_t)0x00000080) |
#define | CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100) |
#define | CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200) |
#define | CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000) |
#define | CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000) |
#define | CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000) |
#define | CLK_APBCLK_UART0_EN ((uint32_t)0x00010000) |
#define | CLK_APBCLK_UART1_EN ((uint32_t)0x00020000) |
#define | CLK_APBCLK_PWM0_CH01_EN ((uint32_t)0x00100000) |
#define | CLK_APBCLK_PWM0_CH23_EN ((uint32_t)0x00200000) |
#define | CLK_APBCLK_DAC_EN ((uint32_t)0x02000000) |
#define | CLK_APBCLK_LCD_EN ((uint32_t)0x04000000) |
#define | CLK_APBCLK_USBD_EN ((uint32_t)0x08000000) |
#define | CLK_APBCLK_ADC_EN ((uint32_t)0x10000000) |
#define | CLK_APBCLK_I2S_EN ((uint32_t)0x20000000) |
#define | CLK_APBCLK_SC0_EN ((uint32_t)0x40000000) |
#define | CLK_APBCLK_SC1_EN ((uint32_t)0x80000000) |
#define | CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001) |
#define | CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002) |
#define | CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004) |
#define | CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008) |
#define | CLK_CLKSTATUS_HIRC_STB ((uint32_t)0x00000010) |
#define | CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080) |
#define | CLK_PLLCTL_PD ((uint32_t)0x00010000) |
#define | CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000)) |
#define | CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000)) |
#define | CLK_PLL_SRC_N(x) (((x)-1)<<8) |
#define | CLK_PLL_MLP(x) ((x)<<0) |
#define | CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32)) |
#define | CLK_PLLCTL_28MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28)) |
#define | CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24)) |
#define | CLK_PLLCTL_22MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22)) |
#define | CLK_PLLCTL_16MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16)) |
#define | CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) |
#define | CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) |
#define | CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) |
#define | CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) |
#define | CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) |
#define | CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) |
#define | CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) |
#define | CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) |
#define | CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) |
#define | CLK_CLKSEL1_ADC_S_HCLK (0x4UL<<CLK_CLKSEL1_ADC_S_Pos) |
#define | CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR1_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR1_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_TMR0_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR0_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
#define | CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
#define | CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) |
#define | CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) |
#define | CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) |
#define | CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) |
#define | CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) |
#define | CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) |
#define | CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) |
#define | CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) |
#define | CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) |
#define | CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) |
#define | CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) |
#define | CLK_CLKSEL2_SC_S_HCLK (0x3UL<<CLK_CLKSEL2_SC_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR2_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR2_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_TMR3_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR3_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV0_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV0_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV0_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV0_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV_S_HXT CLK_CLKSEL2_FRQDIV0_S_HXT |
#define | CLK_CLKSEL2_FRQDIV_S_LXT CLK_CLKSEL2_FRQDIV0_S_LXT |
#define | CLK_CLKSEL2_FRQDIV_S_HCLK CLK_CLKSEL2_FRQDIV0_S_HCLK |
#define | CLK_CLKSEL2_FRQDIV_S_HIRC CLK_CLKSEL2_FRQDIV0_S_HIRC |
#define | CLK_CLKSEL2_FRQDIV1_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV1_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV1_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) |
#define | CLK_CLKSEL2_FRQDIV1_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) |
#define | CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) |
#define | CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) |
#define | CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) |
#define | CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) |
#define | CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) |
#define | CLK_TMR3_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR3_N_Pos) & CLK_CLKDIV1_TMR3_N_Msk) |
#define | CLK_TMR2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR2_N_Pos) & CLK_CLKDIV1_TMR2_N_Msk) |
#define | CLK_TMR1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR1_N_Pos) & CLK_CLKDIV1_TMR1_N_Msk) |
#define | CLK_TMR0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR0_N_Pos) & CLK_CLKDIV1_TMR0_N_Msk) |
#define | CLK_CLKSEL0_STCLKSEL_HCLK (1) |
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) |
#define | CLK_FRQDIV_EN ((uint32_t)0x00000010) |
#define | CLK_WK_INTSTS_IS ((uint32_t)0x00000001) |
#define | MODULE_APBCLK(x) ((x >>31) & 0x1) |
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3) |
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) |
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) |
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3) |
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) |
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) |
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) |
#define | MODULE_NoMsk 0x0 |
#define | NA MODULE_NoMsk |
#define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) |
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) |
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) |
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) |
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) |
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) |
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) |
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) |
#define | TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) |
#define | SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) |
#define | EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) |
#define | ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) |
#define | DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) |
#define | GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) |
#define | SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) |
#define | SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) |
#define | ADC_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(19<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) |
#define | LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) |
#define | PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) |
#define | PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) |
#define | UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) |
#define | UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) |
#define | SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) |
#define | SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) |
#define | ACMP_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_ACMP_EN_Pos ) |
#define | I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) |
#define | I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) |
#define | FDIV1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV1_EN_Pos ) |
#define | FDIV0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV0_EN_Pos ) |
#define | TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) |
#define | TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) |
#define | TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) |
#define | TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) |
#define | RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) |
#define | WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) |
#define | FDIV_MODULE FDIV0_MODULE |
Functions | |
void | CLK_DisableCKO (void) |
This function disable frequency output function. More... | |
void | CLK_DisableCKO0 (void) |
This function disable frequency output function. More... | |
void | CLK_DisableCKO1 (void) |
This function disable frequency output function(1). More... | |
void | CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More... | |
void | CLK_EnableCKO0 (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More... | |
void | CLK_EnableCKO1 (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. (1) More... | |
void | CLK_PowerDown (void) |
This function let system enter to Power-down mode. More... | |
void | CLK_Idle (void) |
This function let system enter to Idle mode. More... | |
uint32_t | CLK_GetHXTFreq (void) |
This function get external high frequency crystal frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_GetLXTFreq (void) |
This function get external low frequency crystal frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_GetHCLKFreq (void) |
This function get HCLK frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_GetPCLKFreq (void) |
This function get PCLK frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_GetCPUFreq (void) |
This function get CPU frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_GetPLLClockFreq (void) |
This function get PLL frequency. The frequency unit is Hz. More... | |
uint32_t | CLK_SetCoreClock (uint32_t u32Hclk) |
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz. More... | |
void | CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
This function set HCLK clock source and HCLK clock divider. More... | |
void | CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
This function set selected module clock source and module clock divider. More... | |
void | CLK_SetSysTickClockSrc (uint32_t u32ClkSrc) |
void | CLK_EnableXtalRC (uint32_t u32ClkMask) |
This function enable clock source. More... | |
void | CLK_DisableXtalRC (uint32_t u32ClkMask) |
This function disable clock source. More... | |
void | CLK_EnableModuleClock (uint32_t u32ModuleIdx) |
This function enable module clock. More... | |
void | CLK_DisableModuleClock (uint32_t u32ModuleIdx) |
This function disable module clock. More... | |
uint32_t | CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq) |
This function set PLL frequency. More... | |
void | CLK_DisablePLL (void) |
This function disable PLL. More... | |
void | CLK_SysTickDelay (uint32_t us) |
This function execute delay function. More... | |
void | CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count) |
Enable System Tick counter. More... | |
void | CLK_DisableSysTick (void) |
Disable System Tick counter. More... | |
uint32_t | CLK_WaitClockReady (uint32_t u32ClkMask) |
This function check selected clock source status. More... | |
Nano102/112 series CLK driver header file.
Definition in file clk.h.