#include <Nano1X2Series.h>
Definition at line 1917 of file Nano1X2Series.h.
◆ DSSR0
__IO uint32_t DMA_GCR_T::DSSR0 |
DSSR0
Offset: 0x04 DMA Service Selection Control Register 0
Bits | Field | Descriptions |
[12:8] | CH1_SEL | Channel 1 Selection |
| | This filed defines which peripheral is connected to PDMA channel 1. |
| | User can configure the peripheral by setting CH1_SEL. |
| | 00000 = Connect to SPI0_TX. |
| | 00001 = Connect to SPI1_TX. |
| | 00010 = Connect to UART0_TX. |
| | 00011 = Connect to UART1_TX. |
| | 00100 = Reserved. |
| | 00101 = Reserved. |
| | 00110 = Reserved. |
| | 00111 = Reserved. |
| | 01000 = Reserved. |
| | 01001 = Connect to TMR0. |
| | 01010 = Connect to TMR1. |
| | 01011 = Connect to TMR2. |
| | 01100 = Connect to TMR3. |
| | 10000 = Connect to SPI0_RX. |
| | 10001 = Connect to SPI1_RX. |
| | 10010 = Connect to UART0_RX. |
| | 10011 = Connect to UART1_RX. |
| | 10100 = Reserved. |
| | 10101 = Reserved. |
| | 10110 = Connect to ADC. |
| | 10111 = Reserved. |
| | 11000 = Reserved. |
| | 11001 = Connect to PWM0_CH0. |
| | 11010 = Connect to PWM0_CH2. |
| | 11011 = Reserved. |
| | 11100 = Reserved. |
| | Others = Disable to connected any peripheral. |
[20:16] | CH2_SEL | Channel 2 Selection |
| | This filed defines which peripheral is connected to PDMA channel 2. |
| | User can configure the peripheral setting by CH2_SEL. |
| | The channel configuration is the same as CH1_SEL field. |
| | Please refer to the explanation of CH1_SEL. |
[28:24] | CH3_SEL | Channel 3 Selection |
| | This filed defines which peripheral is connected to PDMA channel 3. |
| | User can configure the peripheral setting by CH3_SEL. |
| | The channel configuration is the same as CH1_SEL field. |
| | Please refer to the explanation of CH1_SEL. |
Definition at line 1994 of file Nano1X2Series.h.
◆ DSSR1
__IO uint32_t DMA_GCR_T::DSSR1 |
DSSR1
Offset: 0x08 DMA Service Selection Control Register 1
Bits | Field | Descriptions |
[4:0] | CH4_SEL | Channel 4 Selection |
| | This filed defines which peripheral is connected to PDMA channel 4. |
| | User can configure the peripheral by setting CH4_SEL. |
| | 00000 = Connect to SPI0_TX. |
| | 00001 = Connect to SPI1_TX. |
| | 00010 = Connect to UART0_TX. |
| | 00011 = Connect to UART1_TX. |
| | 00100 = Reserved. |
| | 00101 = Reserved. |
| | 00110 = Reserved. |
| | 00111 = Reserved. |
| | 01000 = Reserved. |
| | 01001 = Connect to TMR0. |
| | 01010 = Connect to TMR1. |
| | 01011 = Connect to TMR2. |
| | 01100 = Connect to TMR3. |
| | 10000 = Connect to SPI0_RX. |
| | 10001 = Connect to SPI1_RX. |
| | 10010 = Connect to UART0_RX. |
| | 10011 = Connect to UART1_RX. |
| | 10100 = Reserved. |
| | 10101 = Reserved. |
| | 10110 = Connect to ADC. |
| | 10111 = Reserved. |
| | 11000 = Reserved. |
| | 11001 = Connect to PWM0_CH0. |
| | 11010 = Connect to PWM0_CH2. |
| | 11011 = Reserved. |
| | 11100 = Reserved. |
| | Others = Disable to connected any peripheral. |
Definition at line 2034 of file Nano1X2Series.h.
◆ GCRCSR
__IO uint32_t DMA_GCR_T::GCRCSR |
GCRCSR
Offset: 0x00 DMA Global Control Register
Bits | Field | Descriptions |
[9] | CLK1_EN | PDMA Controller Channel 1 Clock Enable Control |
| | 0 = Disabled. |
| | 1 = Enabled. |
[10] | CLK2_EN | PDMA Controller Channel 2 Clock Enable Control |
| | 0 = Disabled. |
| | 1 = Enabled. |
[11] | CLK3_EN | PDMA Controller Channel 3 Clock Enable Control |
| | 0 = Disabled. |
| | 1 = Enabled. |
[12] | CLK4_EN | PDMA Controller Channel 4 Clock Enable Control |
| | 0 = Disabled. |
| | 1 = Enabled. |
[24] | CRC_CLK_EN | CRC Controller Clock Enable Control |
| | 0 = Disabled. |
| | 1 = Enabled. |
Definition at line 1944 of file Nano1X2Series.h.
◆ GCRISR
__I uint32_t DMA_GCR_T::GCRISR |
GCRISR
Offset: 0x0C DMA Global Interrupt Status Register
Bits | Field | Descriptions |
[1] | INTR1 | Interrupt Status Of Channel 1 (Read Only) |
| | This bit is the interrupt status of PDMA channel1. |
[2] | INTR2 | Interrupt Status Of Channel 2 (Read Only) |
| | This bit is the interrupt status of PDMA channel2. |
| | Note: This bit is read only |
[3] | INTR3 | Interrupt Status Of Channel 3 (Read Only) |
| | This bit is the interrupt status of PDMA channel3. |
[4] | INTR4 | Interrupt Status Of Channel 4 (Read Only) |
| | This bit is the interrupt status of PDMA channel4. |
[16] | INTRCRC | Interrupt Status Of CRC Controller (Read Only) |
| | This bit is the interrupt status of CRC controller |
Definition at line 2055 of file Nano1X2Series.h.
The documentation for this struct was generated from the following file: