NANO100_BSP V3.04.002
The Board Support Package for Nano100BN Series
crc.c
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1/**************************************************************************/
12#include "Nano100Series.h"
13
14
15
41void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
42{
44 PDMACRC->SEED = u32Seed;
45 PDMACRC->CTL = u32Mode | u32Attribute | u32DataLen | DMA_CRC_CTL_CRCCEN_Msk;
46 /* When operated in CPU PIO mode, setting RST bit will reload the initial seed value (CRC_SEED register) */
48}
49
60void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount)
61{
62 PDMACRC->DMASAR = u32SrcAddr;
63 PDMACRC->DMABCR = u32ByteCount;
65}
66
76uint32_t CRC_GetChecksum(void)
77{
78 switch (PDMACRC->CTL & DMA_CRC_CTL_CRC_MODE_Msk)
79 {
80 case CRC_CCITT:
81 case CRC_16:
82 return (PDMACRC->CHECKSUM & 0xffff);
83
84 case CRC_32:
85 return (PDMACRC->CHECKSUM);
86
87 case CRC_8:
88 return (PDMACRC->CHECKSUM & 0xff);
89
90 default:
91 return 0;
92 }
93}
94
95 /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
97 /* end of group NANO100_CRC_Driver */
99 /* end of group NANO100_Device_Driver */
101
102/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
#define DMA_CRC_CTL_CRC_MODE_Msk
#define DMA_CRC_CTL_CRCCEN_Msk
#define DMA_CRC_CTL_CRC_RST_Msk
#define DMA_GCR_GCRCSR_CRC_CLK_EN_Msk
#define DMA_CRC_CTL_TRIG_EN_Msk
#define CRC_CCITT
Definition: crc.h:36
#define CRC_16
Definition: crc.h:38
#define CRC_8
Definition: crc.h:37
#define CRC_32
Definition: crc.h:39
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
CRC Open.
Definition: crc.c:41
uint32_t CRC_GetChecksum(void)
Get CRC Checksum.
Definition: crc.c:76
void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount)
CRC Start DMA transfer.
Definition: crc.c:60
#define PDMACRC
Pointer to PDMA CRC register structure.
#define PDMAGCR
Pointer to PDMA global control register structure.