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MINI55_BSP V3.02.004
The Board Support Package for Mini55 Series MCU
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Modules | |
CLK Exported Functions | |
Macros | |
#define | CLK_PWRCTL_XTL12M 0x01UL |
#define | CLK_PWRCTL_HXT 0x01UL |
#define | CLK_PWRCTL_XTL32K 0x02UL |
#define | CLK_PWRCTL_LXT 0x02UL |
#define | CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL |
#define | CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL |
#define | CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL |
#define | CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL |
#define | CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL |
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL |
#define | CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL |
#define | CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) |
#define | CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL |
#define | CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL |
#define | CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL |
#define | CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL |
#define | CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL |
#define | CLK_CLKSEL1_SPISEL_HXTorLXT 0x00000000UL |
#define | CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL |
#define | CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL |
#define | CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL |
#define | CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL |
#define | CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL |
#define | CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL |
#define | CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL |
#define | CLK_CLKSEL1_UART0SEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_UART0SEL_HIRC 0x02000000UL |
#define | CLK_CLKSEL1_UART1SEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL1_UART1SEL_HIRC 0x08000000UL |
#define | CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL |
#define | CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL |
#define | CLK_CLKSEL2_FDIVSEL_XTAL 0x00000000UL |
#define | CLK_CLKSEL2_FDIVSEL_HXT 0x00000000UL |
#define | CLK_CLKSEL2_FDIVSEL_LXT 0x00000000UL |
#define | CLK_CLKSEL2_FDIVSEL_HCLK 0x00000008UL |
#define | CLK_CLKSEL2_FDIVSEL_HIRC 0x0000000CUL |
#define | CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL |
#define | CLK_CLKDIV_ADC(x) (((x)-1) << 16) |
#define | CLK_CLKDIV_UART(x) (((x)-1) << 8) |
#define | CLK_CLKDIV_UART0(x) (((x)-1) << 8) |
#define | CLK_CLKDIV_UART1(x) (((x)-1) << 12) |
#define | CLK_CLKDIV_HCLK(x) ((x)-1) |
#define | MODULE_APBCLK(x) ((x >>31) & 0x1) |
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3) |
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) |
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) |
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3) |
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) |
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) |
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) |
#define | MODULE_NoMsk 0x0 |
#define | NA MODULE_NoMsk |
#define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) |
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) |
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) |
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) |
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) |
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) |
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) |
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) |
#define | WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDTCKEN_Pos ) |
#define | TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0CKEN_Pos) |
#define | TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1CKEN_Pos) |
#define | FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_CLKOCKEN_Pos) |
#define | I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2CCKEN_Pos) |
#define | SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPICKEN_Pos) |
#define | UART0_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART0CKEN_Pos) |
#define | UART1_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(26<<20)|(0x0<<18)|(0x0F<<10)|(12<<5)|CLK_APBCLK_UART1CKEN_Pos) |
#define | PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH01CKEN_Pos) |
#define | PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH23CKEN_Pos) |
#define | PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH45CKEN_Pos) |
#define | ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADCCKEN_Pos) |
#define | ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMPCKEN_Pos) |
#define ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMPCKEN_Pos) |
#define ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADCCKEN_Pos) |
#define CLK_CLKDIV_ADC | ( | x | ) | (((x)-1) << 16) |
#define CLK_CLKDIV_HCLK | ( | x | ) | ((x)-1) |
#define CLK_CLKDIV_UART | ( | x | ) | (((x)-1) << 8) |
#define CLK_CLKDIV_UART0 | ( | x | ) | (((x)-1) << 8) |
#define CLK_CLKDIV_UART1 | ( | x | ) | (((x)-1) << 12) |
#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL |
#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL |
#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL |
#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) |
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL |
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL |
#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL |
#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL |
#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL |
#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL |
#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL |
#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL |
#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL |
#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL |
#define CLK_CLKSEL1_SPISEL_HXTorLXT 0x00000000UL |
#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL |
#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL |
#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL |
#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL |
#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL |
#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL |
#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL |
#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL |
#define CLK_CLKSEL1_UART0SEL_HIRC 0x02000000UL |
#define CLK_CLKSEL1_UART0SEL_XTAL 0x00000000UL |
#define CLK_CLKSEL1_UART1SEL_HIRC 0x08000000UL |
#define CLK_CLKSEL1_UART1SEL_XTAL 0x00000000UL |
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL |
#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL |
#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL |
#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL |
#define CLK_CLKSEL2_FDIVSEL_HCLK 0x00000008UL |
#define CLK_CLKSEL2_FDIVSEL_HIRC 0x0000000CUL |
#define CLK_CLKSEL2_FDIVSEL_HXT 0x00000000UL |
#define CLK_CLKSEL2_FDIVSEL_LXT 0x00000000UL |
#define CLK_CLKSEL2_FDIVSEL_XTAL 0x00000000UL |
#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL |
#define CLK_PWRCTL_HXT 0x01UL |
#define CLK_PWRCTL_LXT 0x02UL |
#define CLK_PWRCTL_XTL12M 0x01UL |
#define CLK_PWRCTL_XTL32K 0x02UL |
#define FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_CLKOCKEN_Pos) |
#define I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2CCKEN_Pos) |
#define MODULE_APBCLK | ( | x | ) | ((x >>31) & 0x1) |
#define MODULE_APBCLK_ENC | ( | x | ) | (((x) & 0x01) << 31) |
#define MODULE_CLKDIV | ( | x | ) | ((x >>18) & 0x3) |
#define MODULE_CLKDIV_ENC | ( | x | ) | (((x) & 0x03) << 18) |
#define MODULE_CLKDIV_Msk | ( | x | ) | ((x >>10) & 0xff) |
#define MODULE_CLKDIV_Msk_ENC | ( | x | ) | (((x) & 0xff) << 10) |
#define MODULE_CLKDIV_Pos | ( | x | ) | ((x >>5 ) & 0x1f) |
#define MODULE_CLKDIV_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 5) |
#define MODULE_CLKSEL | ( | x | ) | ((x >>29) & 0x3) |
#define MODULE_CLKSEL_ENC | ( | x | ) | (((x) & 0x03) << 29) |
#define MODULE_CLKSEL_Msk | ( | x | ) | ((x >>25) & 0xf) |
#define MODULE_CLKSEL_Msk_ENC | ( | x | ) | (((x) & 0x0f) << 25) |
#define MODULE_CLKSEL_Pos | ( | x | ) | ((x >>20) & 0x1f) |
#define MODULE_CLKSEL_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 20) |
#define MODULE_IP_EN_Pos | ( | x | ) | ((x >>0 ) & 0x1f) |
#define MODULE_IP_EN_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 0) |
#define NA MODULE_NoMsk |
#define PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH01CKEN_Pos) |
#define PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH23CKEN_Pos) |
#define PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH45CKEN_Pos) |
#define SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPICKEN_Pos) |
#define TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0CKEN_Pos) |
#define TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1CKEN_Pos) |
#define UART0_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART0CKEN_Pos) |
#define UART1_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(26<<20)|(0x0<<18)|(0x0F<<10)|(12<<5)|CLK_APBCLK_UART1CKEN_Pos) |
#define WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDTCKEN_Pos ) |