Mini51 BSP  V3.02.002
The Board Support Package for Mini51 Series
Data Fields
PWM_T Struct Reference

#include <Mini51Series.h>

Data Fields

__IO uint32_t PPR
 
__IO uint32_t CSR
 
__IO uint32_t PCR
 
__IO uint32_t CNR [6]
 
__IO uint32_t CMR [6]
 
__IO uint32_t PIER
 
__IO uint32_t PIIR
 
__IO uint32_t POE
 
__IO uint32_t PFBCON
 
__IO uint32_t PDZIR
 
__IO uint32_t TRGCON0
 
__IO uint32_t TRGCON1
 
__IO uint32_t TRGSTS0
 
__IO uint32_t TRGSTS1
 
__IO uint32_t PHCHG
 
__IO uint32_t PHCHGNXT
 
__IO uint32_t PHCHGMASK
 
__IO uint32_t INTACCUCTL
 

Detailed Description

@addtogroup PWM Pulse Width Modulation Controller(PWM)
Memory Mapped Structure for PWM Controller

Definition at line 4794 of file Mini51Series.h.

Field Documentation

◆ CMR

PWM_T::CMR

CMR

Offset: 0x24 ~ 0x38 PWM Comparator Register

BitsFieldDescriptions
[15:0]CMRn
PWM Comparator Bits
CMR determines the PWM duty. n = 0, 1..5.
Edge-aligned mode:
PWM frequency = HCLK/((prescale+1)*(clock divider))/(CNRn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMRn+1)/(CNRn+1).
CMRn >= CNRn: PWM output is always high.
CMRn < CNRn: PWM low width = (CNRn-CMRn) unit; PWM high width = (CMR+1) unit.
CMRn = 0: PWM low width = (CNRn) unit; PWM high width = 1 unit.
Center-aligned mode:
PWM frequency = HCLK/((prescale+1)*(clock divider)) /(2*CNRn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CNRn - CMRn)/(CNRn+1).
CMRn >= CNRn: PWM output is always low.
CMRn < CNRn: PWM low width = (CMRn + 1) * 2 unit; PWM high width = (CNRn - CMRn) * 2 unit.
CMRn = 0: PWM low width = 2 unit; PWM high width = (CNRn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CMRn will take effect in next PWM cycle.

Definition at line 6656 of file Mini51Series.h.

◆ CNR

PWM_T::CNR

CNR

Offset: 0x0C ~ 0x20 PWM Counter Register

BitsFieldDescriptions
[15:0]CNRn
PWM Counter/Timer Loaded Value
CNRn determines the PWM period. n = 0, 1..5.
Edge-aligned mode:
PWM frequency = HCLK/((prescale+1)*(clock divider))/(CNRn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CMRn+1)/(CNRn+1).
CMRn >= CNRn: PWM output is always high.
CMRn < CNRn: PWM low width = (CNRn-CMRn) unit; PWM high width = (CMR+1) unit.
CMRn = 0: PWM low width = (CNRn) unit; PWM high width = 1 unit.
Center-aligned mode:
PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*CNRn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel.
Duty ratio = (CNRn - CMRn)/(CNRn+1).
CMRn >= CNRn: PWM output is always low.
CMRn < CNRn: PWM low width = (CMRn + 1) * 2 unit; PWM high width = (CNRn - CMRn) * 2 unit.
CMRn = 0: PWM low width = 2 unit; PWM high width = (CNRn) * 2 unit.
(Unit = One PWM clock cycle).
Note: Any write to CNRn will take effect in next PWM cycle.

Definition at line 6655 of file Mini51Series.h.

◆ CSR

PWM_T::CSR

CSR

Offset: 0x04 PWM Clock Select Register

BitsFieldDescriptions
[2:0]CSR0
Timer 0 Clock Source Selection
Select clock input for PWM timer.
(Table is the same as CSR5.)
[6:4]CSR1
Timer 1 Clock Source Selection
Select clock input for PWM timer.
(Table is the same as CSR5.)
[10:8]CSR2
Timer 2 Clock Source Selection
Select clock input for PWM timer.
(Table is the same as CSR5.)
[14:12]CSR3
Timer 3 Clock Source Selection
Select clock input for PWM timer.
(Table is the same as CSR5.)
[18:16]CSR4
Timer 4 Clock Source Selection
Select clock input for PWM timer.
(Table is the same as CSR5.)
[22:20]CSR5
Timer 5 Clock Source Selection
Select clock input for PWM timer.
000 = Input Clock Divided by 2.
001 = Input Clock Divided by 4.
010 = Input Clock Divided by 8.
011 = Input Clock Divided by 16.
100 = Input Clock Divided by 1.

Definition at line 6653 of file Mini51Series.h.

◆ INTACCUCTL

PWM_T::INTACCUCTL

INTACCUCTL

Offset: 0x84 Period Interrupt Accumulation Control Register

BitsFieldDescriptions
[0]INTACCUEN0
Interrupt Accumulation Function Enable Control
0 = Disabled.
1 = Enabled.
[7:4]PERIODCNT
Interrupt Accumulation Bits
When INTACCUEN0 is set, PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero, the PWM0 interrupt will occurred and PERIODCNT will reload itself.

Definition at line 6672 of file Mini51Series.h.

◆ PCR

PWM_T::PCR

PCR

Offset: 0x08 PWM Control Register

BitsFieldDescriptions
[0]CH0EN
PWM-timer 0 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[1]DB_MODE
PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)
0 = Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter.
The timer can still be re-started from where it stops.
1 = Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced).
[2]CH0INV
PWM-timer 0 Output Inverter Enable Control
0 = Inverter Disabled.
1 = Inverter Enabled.
[3]CH0MOD
PWM-timer 0 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR0 and CMR0 cleared.
[4]CH1EN
PWM-timer 1 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[6]CH1INV
PWM-timer 1 Output Inverter ON/OFF
0 = Inverter OFF.
1 = Inverter ON.
[7]CH1MOD
PWM-timer 1 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR1 and CMR1 cleared.
[8]CH2EN
PWM-timer 2 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[10]CH2INV
PWM-timer 2 Output Inverter Enable Control
0 = Inverter Disabled.
1 = Inverter Enabled.
[11]CH2MOD
PWM-timer 2 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR2 and CMR2 cleared.
[12]CH3EN
PWM-timer 3 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[14]CH3INV
PWM-timer 3 Output Inverter Enable Control
0 = Inverter Disabled.
1 = Inverter Enabled.
[15]CH3MOD
PWM-timer 3 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR3 and CMR3 cleared.
[16]CH4EN
PWM-timer 4 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[18]CH4INV
PWM-timer 4 Output Inverter Enable Control
0 = Inverter Disabled.
1 = Inverter Enabled.
[19]CH4MOD
PWM-timer 4 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR4 and CMR4 cleared.
[20]CH5EN
PWM-timer 5 Enable/Disable Start Run
0 = Corresponding PWM-timer running Stopped.
1 = Corresponding PWM-timer start run Enabled.
[22]CH5INV
PWM-timer 5 Output Inverter Enable Control
0 = Inverter Disabled.
1 = Inverter Enabled.
[23]CH5MOD
PWM-timer 5 Auto-reload/One-shot Mode
0 = One-shot mode.
1 = Auto-reload mode.
Note: If there is a rising transition at this bit, it will cause CNR5 and CMR5 cleared.
[24]DZEN01
Dead-zone 0 Generator Enable Control (PWM0 And PWM1 Pair For PWM Group)
0 = Disabled.
1 = Enabled.
Note: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
[25]DZEN23
Dead-zone 2 Generator Enable Control (PWM2 And PWM3 Pair For PWM Group)
0 = Disabled.
1 = Enabled.
Note: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
[26]DZEN45
Dead-zone 4 Generator Enable Control (PWM4 And PWM5 Pair For PWM Group)
0 = Disabled.
1 = Enabled.
Note: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
[27]CLRPWM
Clear PWM Counter Control Bit
0 = Do not clear PWM counter.
1 = All 16-bit PWM counters cleared to 0x0000.
Note: It is automatically cleared by hardware.
[29:28]PWMMOD
PWM Operating Mode Selection
00 = Independent mode.
01 = Complementary mode.
10 = Synchronized mode.
11 = Reserved.
[30]GRP
Group Bit
0 = The signals timing of all PWM channels are independent.
1 = Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and also unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1.
[31]PWMTYPE
PWM Aligned Type Selection Bit
0 = Edge-aligned type.
1 = Center-aligned type.

Definition at line 6654 of file Mini51Series.h.

◆ PDZIR

PWM_T::PDZIR

PDZIR

Offset: 0x64 PWM Dead-zone Interval Register

BitsFieldDescriptions
[7:0]DZI01
Dead-zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding CSR bits.
[15:8]DZI23
Dead-zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding CSR bits.
[23:16]DZI45
Dead-zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding CSR bits.

Definition at line 6664 of file Mini51Series.h.

◆ PFBCON

PWM_T::PFBCON

PFBCON

Offset: 0x60 PWM Fault Brake Control Register

BitsFieldDescriptions
[0]BKEN0
Enable BKP0 Pin Trigger Fault Brake Function 0
0 = Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1).
1 = Enabling a falling at BKP0 pin can trigger brake function 0.
[1]BKEN1
Enable BKP1 Pin Trigger Fault Brake Function 1
0 = Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0).
1 = Enabling a falling at BKP1 pin can trigger brake function 1.
[2]CPO0BKEN
BKP1 Fault Brake Function Source Selection
0 = EINT1 as one brake source in BKP1.
1 = CPO0 as one brake source in BKP1.
[3]CPO1BKEN
BKP0 Fault Brake Function Source Selection
0 = EINT0 as one brake source in BKP0.
1 = CPO1 as one brake source in BKP0.
[7]BKF
PWM Fault Brake Event Flag (Write 1 Clear)
0 = PWM output initial state when fault brake conditions asserted.
1 = PWM output fault brake state when fault brake conditions asserted.
Software can write 1 to clear this bit and must clear this bit before restart PWM counter.
[24]PWMBKO0
PWM Channel 0 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[25]PWMBKO1
PWM Channel 1 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[26]PWMBKO2
PWM Channel 2 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[27]PWMBKO3
PWM Channel 3 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[28]PWMBKO4
PWM Channel 4 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[29]PWMBKO5
PWM Channel 5 Brake Output Select Bit
0 = PWM output low when fault brake conditions asserted.
1 = PWM output high when fault brake conditions asserted.
[30]D6BKO6
D6 Brake Output Select Bit
0 = D6 output low when fault brake conditions asserted.
1 = D6 output high when fault brake conditions asserted.
[31]D7BKO7
D7 Brake Output Select Bit
0 = D7 output low when fault brake conditions asserted.
1 = D7 output high when fault brake conditions asserted.

Definition at line 6663 of file Mini51Series.h.

◆ PHCHG

PWM_T::PHCHG

PHCHG

Offset: 0x78 Phase Change Register

BitsFieldDescriptions
[0]D0
D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0
0 = Output low.
1 = Output high.
[1]D1
D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1
0 = Output low.
1 = Output high.
[2]D2
D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2
0 = Output low.
1 = Output high.
[3]D3
D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3
0 = Output low.
1 = Output high.
[4]D4
D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4
0 = Output low.
1 = Output high.
[5]D5
D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5
0 = Output low.
1 = Output high.
[6]D6
D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6
0 = Output low.
1 = Output high.
[7]D7
D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7
0 = Output low.
1 = Output high.
[8]PWM0
PWM Channel 0 Output Enable Control
0 = Output D0 specified in bit 0 of PHCHG register.
1 = Output the original channel 0 waveform.
[9]PWM1
PWM Channel 1 Output Enable Control
0 = Output D1 specified in bit 1 of PHCHG register.
1 = Output the original channel 1 waveform.
[10]PWM2
PWM Channel 2 Output Enable Control
0 = Output D2 specified in bit 2 of PHCHG register.
1 = Output the original channel 2 waveform.
[11]PWM3
PWM Channel 3 Output Enable Control
0 = Output D3 specified in bit 3 of PHCHG register.
1 = Output the original channel 3 waveform.
[12]PWM4
PWM Channel 4 Output Enable Control
0 = Output D4 specified in bit 4 of PHCHG register.
1 = Output the original channel 4 waveform.
[13]PWM5
PWM Channel 5 Output Enable Control
0 = Output D5 specified in bit 5 of PHCHG register.
1 = Output the original channel 5 waveform.
[14]ACCNT0
Hardware Auto Clear CE0 When ACMP0 Trigger It
0 = Enabled.
1 = Disabled.
[15]ACCNT1
Hardware Auto Clear CE1 When ACMP1 Trigger It
0 = Enabled.
1 = Disabled.
[16]CH01TOFF1
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: only for PWM0,PWM1,PWM2,PWM3.
[17]CH11TOFF1
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[18]CH21TOFF1
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[19]CH31TOFF1
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[21:20]CMP1SEL
CMP1SEL
Select the positive input source of ACMP1.
00 = Select P3.1 as the input of ACMP1.
01 = Select P3.2 as the input of ACMP1.
10 = Select P3.3 as the input of ACMP1.
11 = Select P3.4 as the input of ACMP1.
[22]T1
Timer1 Trigger PWM Function Enable Control
0 = Disabled.
1 = Enabled.
When this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
[23]CE1
ACMP1 Trigger Function Enable Control
0 = Disabled.
1 = Enabled.
Note: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
[24]CH01TOFF0
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[25]CH11TOFF0
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[26]CH21TOFF0
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[27]CH31TOFF0
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[29:28]CMP0SEL
CMP0SEL
Select the positive input source of ACMP0.
00 = Select P1.5 as the input of ACMP0.
01 = Select P1.0 as the input of ACMP0.
10 = Select P1.2 as the input of ACMP0.
11 = Select P1.3 as the input of ACMP0.
[30]T0
Timer0 Trigger PWM Function Enable Control
0 = Disabled.
1 = Enabled.
When this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
[31]CE0
ACMP0 Trigger Function Enable Control
0 = Disabled.
1 = Enabled.
Note: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.

Definition at line 6669 of file Mini51Series.h.

◆ PHCHGMASK

PWM_T::PHCHGMASK

PHCHGMASK

Offset: 0x80 Phase Change MASK Register

BitsFieldDescriptions
[6]MASK6
MASK For D6
0 = Original GPIO P0.1.
1 = D6.
[7]MASK7
MASK For D7
0 = Original GPIO P0.0.
1 = D7.
[8]CMPMASK0
MASK For ACMP0
0 = The input of ACMP is controlled by CMP0CR.
1 = The input of ACMP is controlled by CMP0SEL of PHCHG register.
Note: Register CMP0CR is describe in Comparator Controller chapter
[9]CMPMASK1
MASK For ACMP1
0 = The input of ACMP is controlled by CMP1CR.
1 = The input of ACMP is controlled by CMP1SEL of PHCHG register.
Note: Register CMP1CR is describe in Comparator Controller chapter

Definition at line 6671 of file Mini51Series.h.

◆ PHCHGNXT

PWM_T::PHCHGNXT

PHCHGNXT

Offset: 0x7C Next Phase Change Register

BitsFieldDescriptions
[0]D0
D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0
0 = Output low.
1 = Output high.
[1]D1
D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1
0 = Output low.
1 = Output high.
[2]D2
D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2
0 = Output low.
1 = Output high.
[3]D3
D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3
0 = Output low.
1 = Output high.
[4]D4
D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4
0 = Output low.
1 = Output high.
[5]D5
D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5
0 = Output low.
1 = Output high.
[6]D6
D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6
0 = Output low.
1 = Output high.
[7]D7
D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7
0 = Output low.
1 = Output high.
[8]PWM0
PWM Channel 0 Output Enable Control
0 = Output D0 specified in bit 0 of PHCHG register.
1 = Output the original channel 0 waveform.
[9]PWM1
PWM Channel 1 Output Enable Control
0 = Output D1 specified in bit 1 of PHCHG register.
1 = Output the original channel 1 waveform.
[10]PWM2
PWM Channel 2 Output Enable Control
0 = Output D2 specified in bit 2 of PHCHG register.
1 = Output the original channel 2 waveform.
[11]PWM3
PWM Channel 3 Output Enable Control
0 = Output D3 specified in bit 3 of PHCHG register.
1 = Output the original channel 3 waveform.
[12]PWM4
PWM Channel 4 Output Enable Control
0 = Output D4 specified in bit 4 of PHCHG register.
1 = Output the original channel 4 waveform.
[13]PWM5
PWM Channel 5 Output Enable Control
0 = Output D5 specified in bit 5 of PHCHG register.
1 = Output the original channel 5 waveform.
[14]ACCNT0
Hardware Auto Clear CE0 When ACMP0 Trigger It
0 = Enabled.
1 = Disabled.
[15]ACCNT1
Hardware Auto Clear CE1 When ACMP1 Trigger It
0 = Enabled.
1 = Disabled.
[16]CH01TOFF1
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: only for PWM0,PWM1,PWM2,PWM3.
[17]CH11TOFF1
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[18]CH21TOFF1
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[19]CH31TOFF1
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[21:20]CMP1SEL
CMP1SEL
Select the positive input source of ACMP1.
00 = Select P3.1 as the input of ACMP1.
01 = Select P3.2 as the input of ACMP1.
10 = Select P3.3 as the input of ACMP1.
11 = Select P3.4 as the input of ACMP1.
[22]T1
Timer1 Trigger PWM Function Enable Control
0 = Disabled.
1 = Enabled.
When this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
[23]CE1
ACMP1 Trigger Function Enable Control
0 = Disabled.
1 = Enabled.
Note: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
[24]CH01TOFF0
Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[25]CH11TOFF0
Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[26]CH21TOFF0
Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[27]CH31TOFF0
Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application
0 = Disabled.
1 = Enabled.
Note: Only for PWM0, PWM1, PWM2, PWM3.
[29:28]CMP0SEL
CMP0SEL
Select the positive input source of ACMP0.
00 = Select P1.5 as the input of ACMP0.
01 = Select P1.0 as the input of ACMP0.
10 = Select P1.2 as the input of ACMP0.
11 = Select P1.3 as the input of ACMP0.
[30]T0
Timer0 Trigger PWM Function Enable Control
0 = Disabled.
1 = Enabled.
When this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
[31]CE0
ACMP0 Trigger Function Enable Control
0 = Disabled.
1 = Enabled.
Note: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.

Definition at line 6670 of file Mini51Series.h.

◆ PIER

PWM_T::PIER

PIER

Offset: 0x54 PWM Interrupt Enable Control Register

BitsFieldDescriptions
[0]PWMPIE0
PWM Channel 0 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[1]PWMPIE1
PWM Channel 1 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[2]PWMPIE2
PWM Channel 2 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[3]PWMPIE3
PWM Channel 3 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[4]PWMPIE4
PWM Channel 4 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[5]PWMPIE5
PWM Channel 5 Period Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[8]PWMDIE0
PWM Channel 0 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[9]PWMDIE1
PWM Channel 1 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[10]PWMDIE2
PWM Channel 2 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[11]PWMDIE3
PWM Channel 3 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[12]PWMDIE4
PWM Channel 4 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[13]PWMDIE5
PWM Channel 5 Duty Interrupt Enable Control
0 = Disabled.
1 = Enabled.
[16]BRKIE
Fault Brake0 And 1 Interrupt Enable Control
0 = Disabling flags BKF0 and BKF1 to trigger PWM interrupt.
1 = Enabling flags BKF0 and BKF1 can trigger PWM interrupt.
[17]INT_TYPE
PWM Interrupt Type Selection Bit
0 = PWMPIFn will be set if PWM counter underflows.
1 = PWMPIFn will be set if PWM counter matches CNRn register.
Note: This bit is effective when PWM in central align mode only.

Definition at line 6660 of file Mini51Series.h.

◆ PIIR

PWM_T::PIIR

PIIR

Offset: 0x58 PWM Interrupt Indication Register

BitsFieldDescriptions
[0]PWMPIF0
PWM Channel 0 Period Interrupt Flag
Flag is set by hardware when PWM0 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[1]PWMPIF1
PWM Channel 1 Period Interrupt Flag
Flag is set by hardware when PWM1 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[2]PWMPIF2
PWM Channel 2 Period Interrupt Flag
Flag is set by hardware when PWM2 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[3]PWMPIF3
PWM Channel 3 Period Interrupt Flag
Flag is set by hardware when PWM3 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[4]PWMPIF4
PWM Channel 4 Period Interrupt Flag
Flag is set by hardware when PWM4 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[5]PWMPIF5
PWM Channel 5 Period Interrupt Flag
Flag is set by hardware when PWM5 down counter reaches zero.
Note: Software can write 1 to clear this bit.
[8]PWMDIF0
PWM Channel 0 Duty Interrupt Flag
Flag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction.
Note: Software can write 1 to clear this bit.
[9]PWMDIF1
PWM Channel 1 Duty Interrupt Flag
Flag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction.
Note: Software can write 1 to clear this bit.
[10]PWMDIF2
PWM Channel 2 Duty Interrupt Flag
Flag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction.
Note: Software can write 1 to clear this bit.
[11]PWMDIF3
PWM Channel 3 Duty Interrupt Flag
Flag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction.
Note: Software can write 1 to clear this bit.
[12]PWMDIF4
PWM Channel 4 Duty Interrupt Flag
Flag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction.
Note: Software can write 1 to clear this bit.
[13]PWMDIF5
PWM Channel 5 Duty Interrupt Flag
Flag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction.
Note: Software can write 1 to clear this bit.
[16]BKF0
PWM Brake0 Flag
0 = PWM Brake does not recognize a falling signal at BKP0.
1 = When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high.
Note: Software can write 1 to clear this bit.
[17]BKF1
PWM Brake1 Flag
0 = PWM Brake does not recognize a falling signal at BKP1.
1 = When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high.
Note: Software can write 1 to clear this bit.

Definition at line 6661 of file Mini51Series.h.

◆ POE

PWM_T::POE

POE

Offset: 0x5C PWM Output Enable for Channel 0~5

BitsFieldDescriptions
[0]PWM0
PWM Channel 0 Output Enable Control
0 = PWM channel 0 output to pin Disabled.
1 = PWM channel 0 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[1]PWM1
PWM Channel 1 Output Enable Control
0 = PWM channel 1 output to pin Disabled.
1 = PWM channel 1 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[2]PWM2
PWM Channel 2 Output Enable Control
0 = PWM channel 2 output to pin Disabled.
1 = PWM channel 2 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[3]PWM3
PWM Channel 3 Output Enable Control
0 = PWM channel 3 output to pin Disabled.
1 = PWM channel 3 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[4]PWM4
PWM Channel 4 Output Enable Control
0 = PWM channel 4 output to pin Disabled.
1 = PWM channel 4 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.
[5]PWM5
PWM Channel 5 Output Enable Control
0 = PWM channel 5 output to pin Disabled.
1 = PWM channel 5 output to pin Enabled.
Note: The corresponding GPIO pin must be switched to PWM function.

Definition at line 6662 of file Mini51Series.h.

◆ PPR

PWM_T::PPR

PPR

Offset: 0x00 PWM Pre-scale Register

BitsFieldDescriptions
[7:0]CP01
Clock Prescaler 0 For PWM Counter 0 And 1
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.
If CP01 = 0, the clock prescaler 0 output clock will be stopped.
So the corresponding PWM counter will also be stopped.
[15:8]CP23
Clock Prescaler 2 For PWM Counter 2 And 3
Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.
If CP23 = 0, the clock prescaler 2 output clock will be stopped.
So the corresponding PWM counter will also be stopped.
[23:16]CP45
Clock Prescaler 4 For PWM Counter 4 And 5
Clock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.
If CP45 = 0, the clock prescaler 4 output clock will be stopped.
So the corresponding PWM counter will also be stopped.

Definition at line 6652 of file Mini51Series.h.

◆ TRGCON0

PWM_T::TRGCON0

TRGCON0

Offset: 0x68 PWM Trigger Control Register 0

BitsFieldDescriptions
[0]CM0TRGREN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[1]CNT0TRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CNR0
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[2]CM0TRGFEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[3]P0TRGEN
Enable PWM Trigger ADC Function While Channel0's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[8]CM1TRGREN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[9]CNT1TRGEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CNR1
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[10]CM1TRGFEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[11]P1TRGEN
Enable PWM Trigger ADC Function While Channel1's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[16]CM2TRGREN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[17]CNT2TRGEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CNR2
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[18]CM2TRGFEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[19]P2TRGEN
Enable PWM Trigger ADC Function While Channel2's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[24]CM3TRGREN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[25]CNT3TRGEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CNR3
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[26]CM3TRGFEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[27]P3TRGEN
Enable PWM Trigger ADC Function While Channel3's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.

Definition at line 6665 of file Mini51Series.h.

◆ TRGCON1

PWM_T::TRGCON1

TRGCON1

Offset: 0x6C PWM Trigger Control Register 1

BitsFieldDescriptions
[0]CM4TRGREN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[1]CNT4TRGEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CNR4
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[2]CM4TRGFEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[3]P4TRGEN
Enable PWM Trigger ADC Function While Channel4's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[8]CM5TRGREN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Up-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[9]CNT5TRGEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CNR5
0 = Disabled.
1 = Enabled.
Note: This bit is only valid for PWM in center aligned mode.
When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
[10]CM5TRGFEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Down-count Direction
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.
[11]P5TRGEN
Enable PWM Trigger ADC Function While Channel5's Counter Matching 0
0 = Disabled.
1 = Enabled.
Note: This bit is valid for both center aligned mode and edged aligned mode.

Definition at line 6666 of file Mini51Series.h.

◆ TRGSTS0

PWM_T::TRGSTS0

TRGSTS0

Offset: 0x70 PWM Trigger Status Register 0

BitsFieldDescriptions
[0]CMR0FLAG_R
ADC Trigger Flag By Counting Up To CMR
Note: Software can write 1 to clear this bit.
[1]CNT0FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
[2]CMR0FLAG_F
ADC Trigger Flag By Counting Down To CMR
Note: Software can write 1 to clear this bit.
[3]PERID0FLAG
ADC Trigger Flag By Period
Note: Software can write 1 to clear this bit.
[8]CMR1FLAG_R
ADC Trigger Flag By Counting Up To CMR
Note: Software can write 1 to clear this bit.
[9]CNT1FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
[10]CMR1FLAG_F
ADC Trigger Flag By Counting Down To CMR
Note: Software can write 1 to clear this bit.
[11]PERID1FLAG
ADC Trigger Flag By Period
Note: Software can write 1 to clear this bit.
[16]CMR2FLAG_R
ADC Trigger Flag By Counting Up To CMR
Note: Software can write 1 to clear this bit.
[17]CNT2FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
[18]CMR2FLAG_F
ADC Trigger Flag By Counting Down To CMR
Note: Software can write 1 to clear this bit.
[19]PERID2FLAG
ADC Trigger Flag By Period
Note: Software can write 1 to clear this bit.
[24]CMR3FLAG_R
When Counter Counting Up To CMR, This Bit Will Be Set For Trigger ADC
Note: Software can write 1 to clear this bit.
[25]CNT3FLAG
When Counter Counting To CNR, This Bit Will Be Set For Trigger ADC
Note: Software can write 1 to clear this bit.
[26]CMR3FLAG_F
When Counter Counting Down To CMR, This Bit Will Be Set For Trigger ADC
Note: Software can write 1 to clear this bit.
[27]PERID3FLAG
When Counter Counting To Period, This Bit Will Be Set For Trigger ADC
Note: Software can write 1 to clear this bit.

Definition at line 6667 of file Mini51Series.h.

◆ TRGSTS1

PWM_T::TRGSTS1

TRGSTS1

Offset: 0x74 PWM Trigger Status Register 1

BitsFieldDescriptions
[0]CMR4FLAG_R
ADC Trigger Flag By Counting Up To CMR
Note: Software can write 1 to clear this bit.
[1]CNT4FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
[2]CMR4FLAG_F
ADC Trigger Flag By Counting Down To CMR
Note: Software can write 1 to clear this bit.
[3]PERID4FLAG
ADC Trigger Flag By Period
Note: Software can write 1 to clear this bit.
[8]CMR5FLAG_R
ADC Trigger Flag By Counting Up To CMR
Note: Software can write 1 to clear this bit.
[9]CNT5FLAG
ADC Trigger Flag By Counting To CNR
Note: Software can write 1 to clear this bit.
[10]CMR5FLAG_F
ADC Trigger Flag By Counting Down To CMR
Note: Software can write 1 to clear this bit.
[11]PERID5FLAG
ADC Trigger Flag By Period
Note: Software can write 1 to clear this bit.

Definition at line 6668 of file Mini51Series.h.


The documentation for this struct was generated from the following file: