M480 BSP V3.05.005
The Board Support Package for M480 Series
Data Fields
I2C_T Struct Reference

#include <i2c_reg.h>

Data Fields

__IO uint32_t CTL0
 
__IO uint32_t ADDR0
 
__IO uint32_t DAT
 
__I uint32_t STATUS0
 
__IO uint32_t CLKDIV
 
__IO uint32_t TOCTL
 
__IO uint32_t ADDR1
 
__IO uint32_t ADDR2
 
__IO uint32_t ADDR3
 
__IO uint32_t ADDRMSK0
 
__IO uint32_t ADDRMSK1
 
__IO uint32_t ADDRMSK2
 
__IO uint32_t ADDRMSK3
 
__IO uint32_t WKCTL
 
__IO uint32_t WKSTS
 
__IO uint32_t CTL1
 
__IO uint32_t STATUS1
 
__IO uint32_t TMCTL
 
__IO uint32_t BUSCTL
 
__IO uint32_t BUSTCTL
 
__IO uint32_t BUSSTS
 
__IO uint32_t PKTSIZE
 
__I uint32_t PKTCRC
 
__IO uint32_t BUSTOUT
 
__IO uint32_t CLKTOUT
 

Detailed Description

@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller

Definition at line 26 of file i2c_reg.h.

Field Documentation

◆ ADDR0

I2C_T::ADDR0

[0x0004] I2C Slave Address Register0

ADDR0

Offset: 0x04 I2C Slave Address Register0

BitsFieldDescriptions
[0]GC
General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[10:1]ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode
In the slave mode, the seven most significant bits must be loaded with the chip's own address
The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address can not be used.

Definition at line 1047 of file i2c_reg.h.

◆ ADDR1

I2C_T::ADDR1

[0x0018] I2C Slave Address Register1

ADDR1

Offset: 0x18 I2C Slave Address Register1

BitsFieldDescriptions
[0]GC
General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[10:1]ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode
In the slave mode, the seven most significant bits must be loaded with the chip's own address
The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address can not be used.

Definition at line 1052 of file i2c_reg.h.

◆ ADDR2

I2C_T::ADDR2

[0x001c] I2C Slave Address Register2

ADDR2

Offset: 0x1C I2C Slave Address Register2

BitsFieldDescriptions
[0]GC
General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[10:1]ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode
In the slave mode, the seven most significant bits must be loaded with the chip's own address
The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address can not be used.

Definition at line 1053 of file i2c_reg.h.

◆ ADDR3

I2C_T::ADDR3

[0x0020] I2C Slave Address Register3

ADDR3

Offset: 0x20 I2C Slave Address Register3

BitsFieldDescriptions
[0]GC
General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[10:1]ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode
In the slave mode, the seven most significant bits must be loaded with the chip's own address
The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address can not be used.

Definition at line 1054 of file i2c_reg.h.

◆ ADDRMSK0

I2C_T::ADDRMSK0

[0x0024] I2C Slave Address Mask Register0

ADDRMSK0

Offset: 0x24 I2C Slave Address Mask Register0

BitsFieldDescriptions
[10:1]ADDRMSK
I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function can not use address mask.

Definition at line 1055 of file i2c_reg.h.

◆ ADDRMSK1

I2C_T::ADDRMSK1

[0x0028] I2C Slave Address Mask Register1

ADDRMSK1

Offset: 0x28 I2C Slave Address Mask Register1

BitsFieldDescriptions
[10:1]ADDRMSK
I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function can not use address mask.

Definition at line 1056 of file i2c_reg.h.

◆ ADDRMSK2

I2C_T::ADDRMSK2

[0x002c] I2C Slave Address Mask Register2

ADDRMSK2

Offset: 0x2C I2C Slave Address Mask Register2

BitsFieldDescriptions
[10:1]ADDRMSK
I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function can not use address mask.

Definition at line 1057 of file i2c_reg.h.

◆ ADDRMSK3

I2C_T::ADDRMSK3

[0x0030] I2C Slave Address Mask Register3

ADDRMSK3

Offset: 0x30 I2C Slave Address Mask Register3

BitsFieldDescriptions
[10:1]ADDRMSK
I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function can not use address mask.

Definition at line 1058 of file i2c_reg.h.

◆ BUSCTL

I2C_T::BUSCTL

[0x0050] I2C Bus Management Control Register

BUSCTL

Offset: 0x50 I2C Bus Management Control Register

BitsFieldDescriptions
[0]ACKMEN
Acknowledge Control by Manual
In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0 = Slave byte control Disabled.
1 = Slave byte control Enabled
The 9th bit can response the ACK or NACK according the received data by user
When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
[1]PECEN
Packet Error Checking Calculation Enable Bit
0 = Packet Error Checking Calculation Disabled.
1 = Packet Error Checking Calculation Enabled.
Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
[2]BMDEN
Bus Management Device Default Address Enable Bit
0 = Device default address Disable
When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
1 = Device default address Enabled
When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
[3]BMHEN
Bus Management Host Enable Bit
0 = Host function Disabled.
1 = Host function Enabled.
[4]ALERTEN
Bus Management Alert Enable Bit
Device Mode (BMHEN=0).
0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
Host Mode (BMHEN=1).
0 = BM_ALERT pin not supported.
1 = BM_ALERT pin supported.
[5]SCTLOSTS
Suspend/Control Data Output Status
0 = The output of SUSCON pin is low.
1 = The output of SUSCON pin is high.
[6]SCTLOEN
Suspend or Control Pin Output Enable Bit
0 = The SUSCON pin in input.
1 = The output enable is active on the SUSCON pin.
[7]BUSEN
BUS Enable Bit
0 = The system management function is Disabled.
1 = The system management function is Enable.
Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
[8]PECTXEN
Packet Error Checking Byte Transmission/Reception
0 = No PEC transfer.
1 = PEC transmission is requested.
Note: This bit has no effect in slave mode when ACKMEN=0.
[9]TIDLE
Timer Check in Idle State
The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
This bit is used to define which condition is enabled.
0 = The BUSTOUT is used to calculate the clock low period in bus active.
1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
[10]PECCLR
PEC Clear at Repeat Start
The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled.
[11]ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
[12]BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
0 = Indicates the byte count done interrupt is Disabled.
1 = Indicates the byte count done interrupt is Enabled.
Note: This bit is used in PECEN=1.
[13]PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
0 = Indicates the PEC transfer done interrupt is Disabled.
1 = Indicates the PEC transfer done interrupt is Enabled.
Note: This bit is used in PECEN=1.

Definition at line 1067 of file i2c_reg.h.

◆ BUSSTS

I2C_T::BUSSTS

[0x0058] I2C Bus Management Status Register

BUSSTS

Offset: 0x58 I2C Bus Management Status Register

BitsFieldDescriptions
[0]BUSY
Bus Busy
Indicates that a communication is in progress on the bus
It is set by hardware when a START condition is detected
It is cleared by hardware when a STOP condition is detected
0 = The bus is IDLE (both SCLK and SDA High).
1 = The bus is busy.
[1]BCDONE
Byte Count Transmission/Receive Done
0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
Note: Software can write 1 to clear this bit.
[2]PECERR
PEC Error in Reception
0 = Indicates the PEC value equal the received PEC data packet.
1 = Indicates the PEC value doesn't match the receive PEC data packet.
Note: Software can write 1 to clear this bit.
[3]ALERT
SMBus Alert Status
Device Mode (BMHEN =0).
0 = Indicates SMBALERT pin state is low.
1 = Indicates SMBALERT pin state is high.
Host Mode (BMHEN =1).
0 = No SMBALERT event.
1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
Note:
1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
2. Software can write 1 to clear this bit.
[4]SCTLDIN
Bus Suspend or Control Signal Input Status
0 = The input status of SUSCON pin is 0.
1 = The input status of SUSCON pin is 1.
[5]BUSTO
Bus Time-out Status
0 = Indicates that there is no any time-out or external clock time-out.
1 = Indicates that a time-out or external clock time-out occurred.
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
[6]CLKTO
Clock Low Cumulate Time-out Status
0 = Indicates that the cumulative clock low is no any time-out.
1 = Indicates that the cumulative clock low time-out occurred.
Note: Software can write 1 to clear this bit.
[7]PECDONE
PEC Byte Transmission/Receive Done
0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
Note: Software can write 1 to clear this bit.

Definition at line 1069 of file i2c_reg.h.

◆ BUSTCTL

I2C_T::BUSTCTL

[0x0054] I2C Bus Management Timer Control Register

BUSTCTL

Offset: 0x54 I2C Bus Management Timer Control Register

BitsFieldDescriptions
[0]BUSTOEN
Bus Time Out Enable Bit
0 = Indicates the bus clock low time-out detection is Disabled.
1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
[1]CLKTOEN
Cumulative Clock Low Time Out Enable Bit
0 = Indicates the cumulative clock low time-out detection is Disabled.
1 = Indicates the cumulative clock low time-out detection is Enabled.
For Master, it calculates the period from START to ACK
For Slave, it calculates the period from START to STOP
[2]BUSTOIEN
Time-out Interrupt Enable Bit
BUSY =1.
0 = Indicates the SCLK low time-out interrupt is Disabled.
1 = Indicates the SCLK low time-out interrupt is Enabled.
BUSY =0.
0 = Indicates the bus IDLE time-out interrupt is Disabled.
1 = Indicates the bus IDLE time-out interrupt is Enabled.
[3]CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
0 = Indicates the clock time out interrupt is Disabled.
1 = Indicates the clock time out interrupt is Enabled.
[4]TORSTEN
Time Out Reset Enable Bit
0 = Indicates the I2C state machine reset is Disable.
1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)

Definition at line 1068 of file i2c_reg.h.

◆ BUSTOUT

I2C_T::BUSTOUT

[0x0064] I2C Bus Management Timer Register

BUSTOUT

Offset: 0x64 I2C Bus Management Timer Register

BitsFieldDescriptions
[7:0]BUSTO
Bus Management Time-out Value
Indicate the bus time-out value in bus is IDLE or SCLK low.
Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.

Definition at line 1072 of file i2c_reg.h.

◆ CLKDIV

I2C_T::CLKDIV

[0x0010] I2C Clock Divided Register

CLKDIV

Offset: 0x10 I2C Clock Divided Register

BitsFieldDescriptions
[9:0]DIVIDER
I2C Clock Divided
Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
Note: The minimum value of I2C_CLKDIV is 4.

Definition at line 1050 of file i2c_reg.h.

◆ CLKTOUT

I2C_T::CLKTOUT

[0x0068] I2C Bus Management Clock Low Timer Register

CLKTOUT

Offset: 0x68 I2C Bus Management Clock Low Timer Register

BitsFieldDescriptions
[7:0]CLKTO
Bus Clock Low Timer
The field is used to configure the cumulative clock extension time-out.
Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.

Definition at line 1073 of file i2c_reg.h.

◆ CTL0

I2C_T::CTL0

[0x0000] I2C Control Register 0

CTL0

Offset: 0x00 I2C Control Register 0

BitsFieldDescriptions
[2]AA
Assert Acknowledge Control
When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
[3]SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
SI must be cleared by software
Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
[4]STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
This bit will be cleared by hardware automatically.
[5]STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
[6]I2CEN
I2C Controller Enable Bit
Set to enable I2C serial function controller
When I2CEN=1 the I2C serial function enable
The multi-function pin function must set to SDA, and SCL of I2C function first.
0 = I2C controller Disabled.
1 = I2C controller Enabled.
[7]INTEN
Enable Interrupt
0 = I2C interrupt Disabled.
1 = I2C interrupt Enabled.

Definition at line 1046 of file i2c_reg.h.

◆ CTL1

I2C_T::CTL1

[0x0044] I2C Control Register 1

CTL1

Offset: 0x44 I2C Control Register 1

BitsFieldDescriptions
[0]TXPDMAEN
PDMA Transmit Channel Available
0 = Transmit PDMA function disable.
1 = Transmit PDMA function enable.
[1]RXPDMAEN
PDMA Receive Channel Available
0 = Receive PDMA function disable.
1 = Receive PDMA function enable.
[2]PDMARST
PDMA Reset
0 = No effect.
1 = Reset the I2C request to PDMA.
[8]PDMASTR
PDMA Stretch Bit
0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
(only master TX)
[9]ADDR10EN
Address 10-bit Function Enable
0 = Address match 10-bit function is disabled.
1 = Address match 10-bit function is enabled.

Definition at line 1064 of file i2c_reg.h.

◆ DAT

I2C_T::DAT

[0x0008] I2C Data Register

DAT

Offset: 0x08 I2C Data Register

BitsFieldDescriptions
[7:0]DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.

Definition at line 1048 of file i2c_reg.h.

◆ PKTCRC

I2C_T::PKTCRC

[0x0060] I2C Packet Error Checking Byte Value Register

PKTCRC

Offset: 0x60 I2C Packet Error Checking Byte Value Register

BitsFieldDescriptions
[7:0]PECCRC
Packet Error Checking Byte Value
This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
It is read only.

Definition at line 1071 of file i2c_reg.h.

◆ PKTSIZE

I2C_T::PKTSIZE

[0x005c] I2C Packet Error Checking Byte Number Register

PKTSIZE

Offset: 0x5C I2C Packet Error Checking Byte Number Register

BitsFieldDescriptions
[8:0]PLDSIZE
Transfer Byte Number
The transmission or receive byte number in one transaction when the PECEN is set
The maximum transaction or receive byte is 256 Bytes.
Notice: The byte number counting includes address, command code, and data frame.

Definition at line 1070 of file i2c_reg.h.

◆ STATUS0

I2C_T::STATUS0

[0x000c] I2C Status Register 0

STATUS0

Offset: 0x0C I2C Status Register 0

BitsFieldDescriptions
[7:0]STATUS
I2C Status
The three least significant bits are always 0
The five most significant bits contain the status code
There are 28 possible status codes
When the content of I2C_STATUS is F8H, no serial interrupt is requested
Others I2C_STATUS values correspond to defined I2C states
When each of these states is entered, a status interrupt is requested (SI = 1)
A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
In addition, states 00H stands for a Bus Error
A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.

Definition at line 1049 of file i2c_reg.h.

◆ STATUS1

I2C_T::STATUS1

[0x0048] I2C Status Register 1

STATUS1

Offset: 0x48 I2C Status Register 1

BitsFieldDescriptions
[0]ADMAT0
I2C Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used
This bit will set to 1, and software can write 1 to clear this bit.
[1]ADMAT1
I2C Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used
This bit will set to 1, and software can write 1 to clear this bit.
[2]ADMAT2
I2C Address 2 Match Status Register
When address 2 is matched, hardware will inform which address used
This bit will set to 1, and software can write 1 to clear this bit.
[3]ADMAT3
I2C Address 3 Match Status Register
When address 3 is matched, hardware will inform which address used
This bit will set to 1, and software can write 1 to clear this bit.
[8]ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus
It is set by hardware when a START condition is detected
It is cleared by hardware when a STOP condition is detected.
0 = The bus is IDLE (both SCLK and SDA High).
1 = The bus is busy.
Note:This bit is read only.

Definition at line 1065 of file i2c_reg.h.

◆ TMCTL

I2C_T::TMCTL

[0x004c] I2C Timing Configure Control Register

TMCTL

Offset: 0x4C I2C Timing Configure Control Register

BitsFieldDescriptions
[8:0]STCTL
Setup Time Configure Control Register
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
The delay setup time is numbers of peripheral clock = STCTL x PCLK.
Note: Setup time setting should not make SCL output less than three PCLKs.
[24:16]HTCTL
Hold Time Configure Control Register
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
The delay hold time is numbers of peripheral clock = HTCTL x PCLK.

Definition at line 1066 of file i2c_reg.h.

◆ TOCTL

I2C_T::TOCTL

[0x0014] I2C Time-out Control Register

TOCTL

Offset: 0x14 I2C Time-out Control Register

BitsFieldDescriptions
[0]TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
[1]TOCDIV4
Time-out Counter Input Clock Divided by 4
When Enabled, The time-out period is extend 4 times.
0 = Time-out period is extend 4 times Disabled.
1 = Time-out period is extend 4 times Enabled.
[2]TOCEN
Time-out Counter Enable Bit
When Enabled, the 14-bit time-out counter will start counting when SI is clear
Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
0 = Time-out counter Disabled.
1 = Time-out counter Enabled.

Definition at line 1051 of file i2c_reg.h.

◆ WKCTL

I2C_T::WKCTL

[0x003c] I2C Wake-up Control Register

WKCTL

Offset: 0x3C I2C Wake-up Control Register

BitsFieldDescriptions
[0]WKEN
I2C Wake-up Enable Bit
0 = I2C wake-up function Disabled.
1 = I2C wake-up function Enabled.
[7]NHDBUSEN
I2C No Hold BUS Enable Bit
0 = I2C hold bus after wake-up.
1 = I2C don't hold bus after wake-up.
Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.

Definition at line 1062 of file i2c_reg.h.

◆ WKSTS

I2C_T::WKSTS

[0x0040] I2C Wake-up Status Register

WKSTS

Offset: 0x40 I2C Wake-up Status Register

BitsFieldDescriptions
[0]WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1
Software can write 1 to clear this bit.
[1]WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
0 = The ACK bit cycle of address match frame isn't done.
1 = The ACK bit cycle of address match frame is done in power-down.
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
[2]WRSTSWK
Read/Write Status Bit in Address Wakeup Frame
0 = Write command be record on the address match wakeup frame.
1 = Read command be record on the address match wakeup frame.
Note: This bit will be cleared when software can write 1 to WKAKDONE bit.

Definition at line 1063 of file i2c_reg.h.


The documentation for this struct was generated from the following file: