M480 BSP V3.05.005
The Board Support Package for M480 Series
Data Fields
USBD_EP_T Struct Reference

#include <usbd_reg.h>

Data Fields

__IO uint32_t BUFSEG
 
__IO uint32_t MXPLD
 
__IO uint32_t CFG
 
__IO uint32_t CFGP
 

Detailed Description

@addtogroup USBD USB Device Controller(USBD)
Memory Mapped Structure for USBD Controller

Definition at line 26 of file usbd_reg.h.

Field Documentation

◆ BUFSEG

USBD_EP_T::BUFSEG

[0x0000] Endpoint n Buffer Segmentation Register

BUFSEG

Offset: 0x000 Endpoint n Buffer Segmentation Register

BitsFieldDescriptions
[8:3]BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
USBD_SRAM address + { BUFSEG, 3'b000}
Where the USBD_SRAM address = USBD_BA+0x100h.
Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description.

Definition at line 179 of file usbd_reg.h.

◆ CFG

USBD_EP_T::CFG

[0x0008] Endpoint n Configuration Register

CFG

Offset: 0x008 Endpoint n Configuration Register

BitsFieldDescriptions
[3:0]EPNUM
Endpoint Number
These bits are used to define the endpoint number of the current endpoint
[4]ISOCH
Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
0 = No Isochronous endpoint.
1 = Isochronous endpoint.
[6:5]STATE
Endpoint STATE
00 = Endpoint is Disabled.
01 = Out endpoint.
10 = IN endpoint.
11 = Undefined.
[7]DSQSYNC
Data Sequence Synchronization
0 = DATA0 PID.
1 = DATA1 PID.
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
hardware will toggle automatically in IN token base on the bit.
[9]CSTALL
Clear STALL Response
0 = Disable the device to clear the STALL handshake in setup stage.
1 = Clear the device to response STALL handshake in setup stage.

Definition at line 181 of file usbd_reg.h.

◆ CFGP

USBD_EP_T::CFGP

[0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register

CFGP

Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register

BitsFieldDescriptions
[0]CLRRDY
Clear Ready
When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
This bit is write 1 only and is always 0 when it is read back.
[1]SSTALL
Set STALL
0 = Disable the device to response STALL.
1 = Set the device to respond STALL automatically.

Definition at line 182 of file usbd_reg.h.

◆ MXPLD

USBD_EP_T::MXPLD

[0x0004] Endpoint n Maximal Payload Register

MXPLD

Offset: 0x004 Endpoint n Maximal Payload Register

BitsFieldDescriptions
[8:0]MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.

Definition at line 180 of file usbd_reg.h.


The documentation for this struct was generated from the following file: