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M480 BSP V3.05.005
The Board Support Package for M480 Series
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SYS register definition header file. More...
Go to the source code of this file.
Data Structures | |
struct | SYS_T |
struct | NMI_T |
SYS register definition header file.
SPDX-License-Identifier: Apache-2.0
Definition in file sys_reg.h.
#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) |
NMI_T::NMIEN: BODOUT Mask
#define NMI_NMIEN_BODOUT_Pos (0) |
@addtogroup NMI_CONST NMI Bit Field Definition Constant Definitions for NMI Controller
NMI_T::NMIEN: BODOUT Position
#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) |
NMI_T::NMIEN: CLKFAIL Mask
#define NMI_NMIEN_CLKFAIL_Pos (4) |
NMI_T::NMIEN: CLKFAIL Position
#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) |
NMI_T::NMIEN: EINT0 Mask
#define NMI_NMIEN_EINT0_Pos (8) |
NMI_T::NMIEN: EINT0 Position
#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) |
NMI_T::NMIEN: EINT1 Mask
#define NMI_NMIEN_EINT1_Pos (9) |
NMI_T::NMIEN: EINT1 Position
#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) |
NMI_T::NMIEN: EINT2 Mask
#define NMI_NMIEN_EINT2_Pos (10) |
NMI_T::NMIEN: EINT2 Position
#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) |
NMI_T::NMIEN: EINT3 Mask
#define NMI_NMIEN_EINT3_Pos (11) |
NMI_T::NMIEN: EINT3 Position
#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) |
NMI_T::NMIEN: EINT4 Mask
#define NMI_NMIEN_EINT4_Pos (12) |
NMI_T::NMIEN: EINT4 Position
#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) |
NMI_T::NMIEN: EINT5 Mask
#define NMI_NMIEN_EINT5_Pos (13) |
NMI_T::NMIEN: EINT5 Position
#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) |
NMI_T::NMIEN: IRC_INT Mask
#define NMI_NMIEN_IRC_INT_Pos (1) |
NMI_T::NMIEN: IRC_INT Position
#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) |
NMI_T::NMIEN: PWRWU_INT Mask
#define NMI_NMIEN_PWRWU_INT_Pos (2) |
NMI_T::NMIEN: PWRWU_INT Position
#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) |
NMI_T::NMIEN: RTC_INT Mask
#define NMI_NMIEN_RTC_INT_Pos (6) |
NMI_T::NMIEN: RTC_INT Position
#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) |
NMI_T::NMIEN: SRAM_PERR Mask
#define NMI_NMIEN_SRAM_PERR_Pos (3) |
NMI_T::NMIEN: SRAM_PERR Position
#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) |
NMI_T::NMIEN: TAMPER_INT Mask
#define NMI_NMIEN_TAMPER_INT_Pos (7) |
NMI_T::NMIEN: TAMPER_INT Position
#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) |
NMI_T::NMIEN: UART0_INT Mask
#define NMI_NMIEN_UART0_INT_Pos (14) |
NMI_T::NMIEN: UART0_INT Position
#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) |
NMI_T::NMIEN: UART1_INT Mask
#define NMI_NMIEN_UART1_INT_Pos (15) |
NMI_T::NMIEN: UART1_INT Position
#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) |
NMI_T::NMISTS: BODOUT Mask
#define NMI_NMISTS_BODOUT_Pos (0) |
NMI_T::NMISTS: BODOUT Position
#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) |
NMI_T::NMISTS: CLKFAIL Mask
#define NMI_NMISTS_CLKFAIL_Pos (4) |
NMI_T::NMISTS: CLKFAIL Position
#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) |
NMI_T::NMISTS: EINT0 Mask
#define NMI_NMISTS_EINT0_Pos (8) |
NMI_T::NMISTS: EINT0 Position
#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) |
NMI_T::NMISTS: EINT1 Mask
#define NMI_NMISTS_EINT1_Pos (9) |
NMI_T::NMISTS: EINT1 Position
#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) |
NMI_T::NMISTS: EINT2 Mask
#define NMI_NMISTS_EINT2_Pos (10) |
NMI_T::NMISTS: EINT2 Position
#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) |
NMI_T::NMISTS: EINT3 Mask
#define NMI_NMISTS_EINT3_Pos (11) |
NMI_T::NMISTS: EINT3 Position
#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) |
NMI_T::NMISTS: EINT4 Mask
#define NMI_NMISTS_EINT4_Pos (12) |
NMI_T::NMISTS: EINT4 Position
#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) |
NMI_T::NMISTS: EINT5 Mask
#define NMI_NMISTS_EINT5_Pos (13) |
NMI_T::NMISTS: EINT5 Position
#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) |
NMI_T::NMISTS: IRC_INT Mask
#define NMI_NMISTS_IRC_INT_Pos (1) |
NMI_T::NMISTS: IRC_INT Position
#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) |
NMI_T::NMISTS: PWRWU_INT Mask
#define NMI_NMISTS_PWRWU_INT_Pos (2) |
NMI_T::NMISTS: PWRWU_INT Position
#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) |
NMI_T::NMISTS: RTC_INT Mask
#define NMI_NMISTS_RTC_INT_Pos (6) |
NMI_T::NMISTS: RTC_INT Position
#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) |
NMI_T::NMISTS: SRAM_PERR Mask
#define NMI_NMISTS_SRAM_PERR_Pos (3) |
NMI_T::NMISTS: SRAM_PERR Position
#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) |
NMI_T::NMISTS: TAMPER_INT Mask
#define NMI_NMISTS_TAMPER_INT_Pos (7) |
NMI_T::NMISTS: TAMPER_INT Position
#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) |
NMI_T::NMISTS: UART0_INT Mask
#define NMI_NMISTS_UART0_INT_Pos (14) |
NMI_T::NMISTS: UART0_INT Position
#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) |
NMI_T::NMISTS: UART1_INT Mask
#define NMI_NMISTS_UART1_INT_Pos (15) |
NMI_T::NMISTS: UART1_INT Position