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M480 BSP V3.05.005
The Board Support Package for M480 Series
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Modules | |
CLK Exported Functions | |
Variables | |
int32_t | g_CLK_i32ErrCode |
#define CLK_CLKDIV0_EADC | ( | x | ) |
#define CLK_CLKDIV0_HCLK | ( | x | ) |
#define CLK_CLKDIV0_SDH0 | ( | x | ) |
#define CLK_CLKDIV0_UART0 | ( | x | ) |
#define CLK_CLKDIV0_UART1 | ( | x | ) |
#define CLK_CLKDIV0_USB | ( | x | ) |
#define CLK_CLKDIV1_SC0 | ( | x | ) |
#define CLK_CLKDIV1_SC1 | ( | x | ) |
#define CLK_CLKDIV1_SC2 | ( | x | ) |
#define CLK_CLKDIV2_EADC1 | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos) |
#define CLK_CLKDIV2_I2S0 | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos) |
#define CLK_CLKDIV3_CCAP | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos) |
#define CLK_CLKDIV3_EMAC | ( | x | ) |
#define CLK_CLKDIV3_SDH1 | ( | x | ) |
#define CLK_CLKDIV3_VSENSE | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) |
#define CLK_CLKDIV4_UART2 | ( | x | ) |
#define CLK_CLKDIV4_UART3 | ( | x | ) |
#define CLK_CLKDIV4_UART4 | ( | x | ) |
#define CLK_CLKDIV4_UART5 | ( | x | ) |
#define CLK_CLKDIV4_UART6 | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) |
#define CLK_CLKDIV4_UART7 | ( | x | ) | (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) |
#define CLK_CLKSEL0_HCLKSEL_HIRC |
#define CLK_CLKSEL0_HCLKSEL_HXT |
#define CLK_CLKSEL0_HCLKSEL_LIRC |
#define CLK_CLKSEL0_HCLKSEL_LXT |
#define CLK_CLKSEL0_HCLKSEL_PLL |
#define CLK_CLKSEL0_SDH0SEL_HCLK |
#define CLK_CLKSEL0_SDH0SEL_HIRC |
#define CLK_CLKSEL0_SDH0SEL_HXT |
#define CLK_CLKSEL0_SDH0SEL_PLL |
#define CLK_CLKSEL0_SDH1SEL_HCLK |
#define CLK_CLKSEL0_SDH1SEL_HIRC |
#define CLK_CLKSEL0_SDH1SEL_HXT |
#define CLK_CLKSEL0_SDH1SEL_PLL |
#define CLK_CLKSEL0_STCLKSEL_HCLK |
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
#define CLK_CLKSEL0_STCLKSEL_HXT |
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
#define CLK_CLKSEL0_STCLKSEL_LXT |
#define CLK_CLKSEL0_USBSEL_PLL |
#define CLK_CLKSEL0_USBSEL_RC48M |
#define CLK_CLKSEL1_CLKOSEL_HCLK |
#define CLK_CLKSEL1_CLKOSEL_HIRC |
#define CLK_CLKSEL1_CLKOSEL_HXT |
#define CLK_CLKSEL1_CLKOSEL_LXT |
#define CLK_CLKSEL1_TMR0SEL_EXT |
#define CLK_CLKSEL1_TMR0SEL_HIRC |
#define CLK_CLKSEL1_TMR0SEL_HXT |
#define CLK_CLKSEL1_TMR0SEL_LIRC |
#define CLK_CLKSEL1_TMR0SEL_LXT |
#define CLK_CLKSEL1_TMR0SEL_PCLK0 |
#define CLK_CLKSEL1_TMR1SEL_EXT |
#define CLK_CLKSEL1_TMR1SEL_HIRC |
#define CLK_CLKSEL1_TMR1SEL_HXT |
#define CLK_CLKSEL1_TMR1SEL_LIRC |
#define CLK_CLKSEL1_TMR1SEL_LXT |
#define CLK_CLKSEL1_TMR1SEL_PCLK0 |
#define CLK_CLKSEL1_TMR2SEL_EXT |
#define CLK_CLKSEL1_TMR2SEL_HIRC |
#define CLK_CLKSEL1_TMR2SEL_HXT |
#define CLK_CLKSEL1_TMR2SEL_LIRC |
#define CLK_CLKSEL1_TMR2SEL_LXT |
#define CLK_CLKSEL1_TMR2SEL_PCLK1 |
#define CLK_CLKSEL1_TMR3SEL_EXT |
#define CLK_CLKSEL1_TMR3SEL_HIRC |
#define CLK_CLKSEL1_TMR3SEL_HXT |
#define CLK_CLKSEL1_TMR3SEL_LIRC |
#define CLK_CLKSEL1_TMR3SEL_LXT |
#define CLK_CLKSEL1_TMR3SEL_PCLK1 |
#define CLK_CLKSEL1_UART0SEL_HIRC |
#define CLK_CLKSEL1_UART0SEL_HXT |
#define CLK_CLKSEL1_UART0SEL_LXT |
#define CLK_CLKSEL1_UART0SEL_PLL |
#define CLK_CLKSEL1_UART1SEL_HIRC |
#define CLK_CLKSEL1_UART1SEL_HXT |
#define CLK_CLKSEL1_UART1SEL_LXT |
#define CLK_CLKSEL1_UART1SEL_PLL |
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 |
#define CLK_CLKSEL1_WDTSEL_LIRC |
#define CLK_CLKSEL1_WDTSEL_LXT |
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 |
#define CLK_CLKSEL1_WWDTSEL_LIRC |
#define CLK_CLKSEL2_BPWM0SEL_PCLK0 |
#define CLK_CLKSEL2_BPWM0SEL_PLL |
#define CLK_CLKSEL2_BPWM1SEL_PCLK1 |
#define CLK_CLKSEL2_BPWM1SEL_PLL |
#define CLK_CLKSEL2_EPWM0SEL_PCLK0 |
#define CLK_CLKSEL2_EPWM0SEL_PLL |
#define CLK_CLKSEL2_EPWM1SEL_PCLK1 |
#define CLK_CLKSEL2_EPWM1SEL_PLL |
#define CLK_CLKSEL2_QSPI0SEL_HIRC |
#define CLK_CLKSEL2_QSPI0SEL_HXT |
#define CLK_CLKSEL2_QSPI0SEL_PCLK0 |
#define CLK_CLKSEL2_QSPI0SEL_PLL |
#define CLK_CLKSEL2_SPI0SEL_HIRC |
#define CLK_CLKSEL2_SPI0SEL_HXT |
#define CLK_CLKSEL2_SPI0SEL_PCLK1 |
#define CLK_CLKSEL2_SPI0SEL_PLL |
#define CLK_CLKSEL2_SPI1SEL_HIRC |
#define CLK_CLKSEL2_SPI1SEL_HXT |
#define CLK_CLKSEL2_SPI1SEL_PCLK0 |
#define CLK_CLKSEL2_SPI1SEL_PLL |
#define CLK_CLKSEL2_SPI2SEL_HIRC |
#define CLK_CLKSEL2_SPI2SEL_HXT |
#define CLK_CLKSEL2_SPI2SEL_PCLK1 |
#define CLK_CLKSEL2_SPI2SEL_PLL |
#define CLK_CLKSEL2_SPI3SEL_HIRC |
#define CLK_CLKSEL2_SPI3SEL_HXT |
#define CLK_CLKSEL2_SPI3SEL_PCLK0 |
#define CLK_CLKSEL2_SPI3SEL_PLL |
#define CLK_CLKSEL3_I2S0SEL_HIRC |
#define CLK_CLKSEL3_I2S0SEL_HXT |
#define CLK_CLKSEL3_I2S0SEL_PCLK0 |
#define CLK_CLKSEL3_I2S0SEL_PLL |
#define CLK_CLKSEL3_QSPI1SEL_HIRC |
#define CLK_CLKSEL3_QSPI1SEL_HXT |
#define CLK_CLKSEL3_QSPI1SEL_PCLK1 |
#define CLK_CLKSEL3_QSPI1SEL_PLL |
#define CLK_CLKSEL3_RTCSEL_LIRC |
#define CLK_CLKSEL3_RTCSEL_LXT |
#define CLK_CLKSEL3_SC0SEL_HIRC |
#define CLK_CLKSEL3_SC0SEL_HXT |
#define CLK_CLKSEL3_SC0SEL_PCLK0 |
#define CLK_CLKSEL3_SC0SEL_PLL |
#define CLK_CLKSEL3_SC1SEL_HIRC |
#define CLK_CLKSEL3_SC1SEL_HXT |
#define CLK_CLKSEL3_SC1SEL_PCLK1 |
#define CLK_CLKSEL3_SC1SEL_PLL |
#define CLK_CLKSEL3_SC2SEL_HIRC |
#define CLK_CLKSEL3_SC2SEL_HXT |
#define CLK_CLKSEL3_SC2SEL_PCLK0 |
#define CLK_CLKSEL3_SC2SEL_PLL |
#define CLK_CLKSEL3_UART2SEL_HIRC |
#define CLK_CLKSEL3_UART2SEL_HXT |
#define CLK_CLKSEL3_UART2SEL_LXT |
#define CLK_CLKSEL3_UART2SEL_PLL |
#define CLK_CLKSEL3_UART3SEL_HIRC |
#define CLK_CLKSEL3_UART3SEL_HXT |
#define CLK_CLKSEL3_UART3SEL_LXT |
#define CLK_CLKSEL3_UART3SEL_PLL |
#define CLK_CLKSEL3_UART4SEL_HIRC |
#define CLK_CLKSEL3_UART4SEL_HXT |
#define CLK_CLKSEL3_UART4SEL_LXT |
#define CLK_CLKSEL3_UART4SEL_PLL |
#define CLK_CLKSEL3_UART5SEL_HIRC |
#define CLK_CLKSEL3_UART5SEL_HXT |
#define CLK_CLKSEL3_UART5SEL_LXT |
#define CLK_CLKSEL3_UART5SEL_PLL |
#define CLK_CLKSEL3_UART6SEL_HIRC |
#define CLK_CLKSEL3_UART6SEL_HXT |
#define CLK_CLKSEL3_UART6SEL_LXT |
#define CLK_CLKSEL3_UART6SEL_PLL |
#define CLK_CLKSEL3_UART7SEL_HIRC |
#define CLK_CLKSEL3_UART7SEL_HXT |
#define CLK_CLKSEL3_UART7SEL_LXT |
#define CLK_CLKSEL3_UART7SEL_PLL |
#define CLK_DISABLE_DPDWKPIN | ( | void | ) |
#define CLK_DISABLE_DPDWKPIN0 | ( | void | ) |
#define CLK_DISABLE_DPDWKPIN1 | ( | void | ) |
#define CLK_DISABLE_DPDWKPIN2 | ( | void | ) |
#define CLK_DISABLE_DPDWKPIN3 | ( | void | ) |
#define CLK_DISABLE_DPDWKPIN4 | ( | void | ) |
#define CLK_DISABLE_RTCWK | ( | void | ) |
#define CLK_DISABLE_SPDACMP | ( | void | ) |
#define CLK_DISABLE_WKTMR | ( | void | ) |
#define CLK_DPDWKPIN0_BOTHEDGE |
#define CLK_DPDWKPIN0_DISABLE |
#define CLK_DPDWKPIN0_FALLING |
#define CLK_DPDWKPIN0_RISING |
#define CLK_DPDWKPIN1_BOTHEDGE |
#define CLK_DPDWKPIN1_DISABLE |
#define CLK_DPDWKPIN1_FALLING |
#define CLK_DPDWKPIN1_RISING |
#define CLK_DPDWKPIN2_BOTHEDGE |
#define CLK_DPDWKPIN2_DISABLE |
#define CLK_DPDWKPIN2_FALLING |
#define CLK_DPDWKPIN2_RISING |
#define CLK_DPDWKPIN3_BOTHEDGE |
#define CLK_DPDWKPIN3_DISABLE |
#define CLK_DPDWKPIN3_FALLING |
#define CLK_DPDWKPIN3_RISING |
#define CLK_DPDWKPIN4_BOTHEDGE |
#define CLK_DPDWKPIN4_DISABLE |
#define CLK_DPDWKPIN4_FALLING |
#define CLK_DPDWKPIN4_RISING |
#define CLK_DPDWKPIN_BOTHEDGE |
#define CLK_DPDWKPIN_DISABLE |
#define CLK_DPDWKPIN_FALLING |
#define CLK_DPDWKPIN_RISING |
#define CLK_ENABLE_RTCWK | ( | void | ) |
#define CLK_ENABLE_SPDACMP | ( | void | ) |
#define CLK_ENABLE_WKTMR | ( | void | ) |
#define CLK_PCLKDIV_APB0DIV_DIV1 |
#define CLK_PCLKDIV_APB0DIV_DIV16 |
#define CLK_PCLKDIV_APB0DIV_DIV2 |
#define CLK_PCLKDIV_APB0DIV_DIV4 |
#define CLK_PCLKDIV_APB0DIV_DIV8 |
#define CLK_PCLKDIV_APB1DIV_DIV1 |
#define CLK_PCLKDIV_APB1DIV_DIV16 |
#define CLK_PCLKDIV_APB1DIV_DIV2 |
#define CLK_PCLKDIV_APB1DIV_DIV4 |
#define CLK_PCLKDIV_APB1DIV_DIV8 |
#define CLK_PCLKDIV_PCLK0DIV1 |
#define CLK_PCLKDIV_PCLK0DIV16 |
#define CLK_PCLKDIV_PCLK0DIV2 |
#define CLK_PCLKDIV_PCLK0DIV4 |
#define CLK_PCLKDIV_PCLK0DIV8 |
#define CLK_PCLKDIV_PCLK1DIV1 |
#define CLK_PCLKDIV_PCLK1DIV16 |
#define CLK_PCLKDIV_PCLK1DIV2 |
#define CLK_PCLKDIV_PCLK1DIV4 |
#define CLK_PCLKDIV_PCLK1DIV8 |
#define CLK_PLLCTL_144MHz_HIRC |
#define CLK_PLLCTL_144MHz_HXT |
#define CLK_PLLCTL_160MHz_HIRC |
#define CLK_PLLCTL_160MHz_HXT |
#define CLK_PLLCTL_192MHz_HIRC |
#define CLK_PLLCTL_192MHz_HXT |
#define CLK_PLLCTL_72MHz_HIRC |
#define CLK_PLLCTL_72MHz_HXT |
#define CLK_PLLCTL_80MHz_HIRC |
#define CLK_PLLCTL_80MHz_HXT |
#define CLK_PLLCTL_NF | ( | x | ) |
#define CLK_PLLCTL_NR | ( | x | ) |
#define CLK_PLLCTL_PLLSRC_HIRC |
#define CLK_PLLCTL_PLLSRC_HXT |
#define CLK_PMUCTL_PDMSEL_DPD |
#define CLK_PMUCTL_PDMSEL_FWPD |
#define CLK_PMUCTL_PDMSEL_LLPD |
#define CLK_PMUCTL_PDMSEL_PD |
#define CLK_PMUCTL_PDMSEL_SPD0 |
#define CLK_PMUCTL_PDMSEL_SPD1 |
#define CLK_PMUCTL_WKTMRIS_1024 |
#define CLK_PMUCTL_WKTMRIS_1048576 |
#define CLK_PMUCTL_WKTMRIS_128 |
#define CLK_PMUCTL_WKTMRIS_131072 |
#define CLK_PMUCTL_WKTMRIS_16384 |
#define CLK_PMUCTL_WKTMRIS_256 |
#define CLK_PMUCTL_WKTMRIS_262144 |
#define CLK_PMUCTL_WKTMRIS_4096 |
#define CLK_PMUCTL_WKTMRIS_512 |
#define CLK_PMUCTL_WKTMRIS_524288 |
#define CLK_PMUCTL_WKTMRIS_65536 |
#define CLK_PMUCTL_WKTMRIS_8192 |
#define CLK_SPDSRETSEL_128K |
#define CLK_SPDSRETSEL_16K |
#define CLK_SPDSRETSEL_32K |
#define CLK_SPDSRETSEL_64K |
#define CLK_SPDSRETSEL_NO |
#define CLK_SPDWKPIN_DEBOUNCEDIS |
#define CLK_SPDWKPIN_DEBOUNCEEN |
#define CLK_SPDWKPIN_ENABLE |
#define CLK_SPDWKPIN_FALLING |
#define CLK_SPDWKPIN_RISING |
#define CLK_SWKDBCTL_SWKDBCLKSEL_1 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_128 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_16 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_2 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_32 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_4 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_64 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_8 |
#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 |
#define MODULE_APBCLK | ( | x | ) |
#define MODULE_APBCLK_ENC | ( | x | ) |
#define MODULE_CLKDIV | ( | x | ) |
#define MODULE_CLKDIV_ENC | ( | x | ) |
#define MODULE_CLKDIV_Msk | ( | x | ) |
#define MODULE_CLKDIV_Msk_ENC | ( | x | ) |
#define MODULE_CLKDIV_Pos | ( | x | ) |
#define MODULE_CLKDIV_Pos_ENC | ( | x | ) |
#define MODULE_CLKSEL | ( | x | ) |
#define MODULE_CLKSEL_ENC | ( | x | ) |
#define MODULE_CLKSEL_Msk | ( | x | ) |
#define MODULE_CLKSEL_Msk_ENC | ( | x | ) |
#define MODULE_CLKSEL_Pos | ( | x | ) |
#define MODULE_CLKSEL_Pos_ENC | ( | x | ) |
#define MODULE_IP_EN_Pos | ( | x | ) |
#define MODULE_IP_EN_Pos_ENC | ( | x | ) |