M480 BSP V3.05.005
The Board Support Package for M480 Series
bpwm_reg.h
Go to the documentation of this file.
1/**************************************************************************/
9#ifndef __BPWM_REG_H__
10#define __BPWM_REG_H__
11
12#if defined ( __CC_ARM )
13#pragma anon_unions
14#endif
15
26typedef struct
27{
67 __IO uint32_t RCAPDAT;
68 __IO uint32_t FCAPDAT;
69} BCAPDAT_T;
70
71typedef struct
72{
73
74
2380 __IO uint32_t CTL0;
2381 __IO uint32_t CTL1;
2383 __I uint32_t RESERVE0[2];
2385 __IO uint32_t CLKSRC;
2386 __IO uint32_t CLKPSC;
2388 __I uint32_t RESERVE1[2];
2390 __IO uint32_t CNTEN;
2391 __IO uint32_t CNTCLR;
2393 __I uint32_t RESERVE2[2];
2395 __IO uint32_t PERIOD;
2397 __I uint32_t RESERVE3[7];
2399 __IO uint32_t CMPDAT[6];
2401 __I uint32_t RESERVE4[10];
2403 __I uint32_t CNT;
2405 __I uint32_t RESERVE5[7];
2407 __IO uint32_t WGCTL0;
2408 __IO uint32_t WGCTL1;
2409 __IO uint32_t MSKEN;
2410 __IO uint32_t MSK;
2412 __I uint32_t RESERVE6[5];
2414 __IO uint32_t POLCTL;
2415 __IO uint32_t POEN;
2417 __I uint32_t RESERVE7[1];
2419 __IO uint32_t INTEN;
2421 __I uint32_t RESERVE8[1];
2423 __IO uint32_t INTSTS;
2425 __I uint32_t RESERVE9[3];
2427 __IO uint32_t EADCTS0;
2428 __IO uint32_t EADCTS1;
2430 __I uint32_t RESERVE10[4];
2432 __IO uint32_t SSCTL;
2433 __O uint32_t SSTRG;
2435 __I uint32_t RESERVE11[2];
2437 __IO uint32_t STATUS;
2439 __I uint32_t RESERVE12[55];
2441 __IO uint32_t CAPINEN;
2442 __IO uint32_t CAPCTL;
2443 __I uint32_t CAPSTS;
2444 BCAPDAT_T CAPDAT[6];
2446 __I uint32_t RESERVE13[5];
2448 __IO uint32_t CAPIEN;
2449 __IO uint32_t CAPIF;
2451 __I uint32_t RESERVE14[43];
2453 __I uint32_t PBUF;
2455 __I uint32_t RESERVE15[5];
2457 __I uint32_t CMPBUF[6];
2459} BPWM_T;
2460
2466#define BPWM_CTL0_CTRLD0_Pos (0)
2467#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos)
2469#define BPWM_CTL0_CTRLD1_Pos (1)
2470#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos)
2472#define BPWM_CTL0_CTRLD2_Pos (2)
2473#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos)
2475#define BPWM_CTL0_CTRLD3_Pos (3)
2476#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos)
2478#define BPWM_CTL0_CTRLD4_Pos (4)
2479#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos)
2481#define BPWM_CTL0_CTRLD5_Pos (5)
2482#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos)
2484#define BPWM_CTL0_IMMLDEN0_Pos (16)
2485#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos)
2487#define BPWM_CTL0_IMMLDEN1_Pos (17)
2488#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos)
2490#define BPWM_CTL0_IMMLDEN2_Pos (18)
2491#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos)
2493#define BPWM_CTL0_IMMLDEN3_Pos (19)
2494#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos)
2496#define BPWM_CTL0_IMMLDEN4_Pos (20)
2497#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos)
2499#define BPWM_CTL0_IMMLDEN5_Pos (21)
2500#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos)
2502#define BPWM_CTL0_DBGHALT_Pos (30)
2503#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos)
2505#define BPWM_CTL0_DBGTRIOFF_Pos (31)
2506#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos)
2508#define BPWM_CTL1_CNTTYPE0_Pos (0)
2509#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos)
2511#define BPWM_CLKSRC_ECLKSRC0_Pos (0)
2512#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos)
2514#define BPWM_CLKPSC_CLKPSC_Pos (0)
2515#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos)
2517#define BPWM_CNTEN_CNTEN0_Pos (0)
2518#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos)
2520#define BPWM_CNTCLR_CNTCLR0_Pos (0)
2521#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos)
2523#define BPWM_PERIOD_PERIOD_Pos (0)
2524#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos)
2526#define BPWM_CMPDAT0_CMPDAT_Pos (0)
2527#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos)
2529#define BPWM_CMPDAT1_CMPDAT_Pos (0)
2530#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos)
2532#define BPWM_CMPDAT2_CMPDAT_Pos (0)
2533#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos)
2535#define BPWM_CMPDAT3_CMPDAT_Pos (0)
2536#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos)
2538#define BPWM_CMPDAT4_CMPDAT_Pos (0)
2539#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos)
2541#define BPWM_CMPDAT5_CMPDAT_Pos (0)
2542#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos)
2544#define BPWM_CNT_CNT_Pos (0)
2545#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos)
2547#define BPWM_CNT_DIRF_Pos (16)
2548#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos)
2550#define BPWM_WGCTL0_ZPCTL0_Pos (0)
2551#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos)
2553#define BPWM_WGCTL0_ZPCTL1_Pos (2)
2554#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos)
2556#define BPWM_WGCTL0_ZPCTL2_Pos (4)
2557#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos)
2559#define BPWM_WGCTL0_ZPCTL3_Pos (6)
2560#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos)
2562#define BPWM_WGCTL0_ZPCTL4_Pos (8)
2563#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos)
2565#define BPWM_WGCTL0_ZPCTL5_Pos (10)
2566#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos)
2568#define BPWM_WGCTL0_ZPCTLn_Pos (0)
2569#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos)
2571#define BPWM_WGCTL0_PRDPCTL0_Pos (16)
2572#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos)
2574#define BPWM_WGCTL0_PRDPCTL1_Pos (18)
2575#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos)
2577#define BPWM_WGCTL0_PRDPCTL2_Pos (20)
2578#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos)
2580#define BPWM_WGCTL0_PRDPCTL3_Pos (22)
2581#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos)
2583#define BPWM_WGCTL0_PRDPCTL4_Pos (24)
2584#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos)
2586#define BPWM_WGCTL0_PRDPCTL5_Pos (26)
2587#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos)
2589#define BPWM_WGCTL0_PRDPCTLn_Pos (16)
2590#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos)
2592#define BPWM_WGCTL1_CMPUCTL0_Pos (0)
2593#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos)
2595#define BPWM_WGCTL1_CMPUCTL1_Pos (2)
2596#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos)
2598#define BPWM_WGCTL1_CMPUCTL2_Pos (4)
2599#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos)
2601#define BPWM_WGCTL1_CMPUCTL3_Pos (6)
2602#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos)
2604#define BPWM_WGCTL1_CMPUCTL4_Pos (8)
2605#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos)
2607#define BPWM_WGCTL1_CMPUCTL5_Pos (10)
2608#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos)
2610#define BPWM_WGCTL1_CMPUCTLn_Pos (0)
2611#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos)
2613#define BPWM_WGCTL1_CMPDCTL0_Pos (16)
2614#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos)
2616#define BPWM_WGCTL1_CMPDCTL1_Pos (18)
2617#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos)
2619#define BPWM_WGCTL1_CMPDCTL2_Pos (20)
2620#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos)
2622#define BPWM_WGCTL1_CMPDCTL3_Pos (22)
2623#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos)
2625#define BPWM_WGCTL1_CMPDCTL4_Pos (24)
2626#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos)
2628#define BPWM_WGCTL1_CMPDCTL5_Pos (26)
2629#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos)
2631#define BPWM_WGCTL1_CMPDCTLn_Pos (16)
2632#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos)
2634#define BPWM_MSKEN_MSKEN0_Pos (0)
2635#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos)
2637#define BPWM_MSKEN_MSKEN1_Pos (1)
2638#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos)
2640#define BPWM_MSKEN_MSKEN2_Pos (2)
2641#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos)
2643#define BPWM_MSKEN_MSKEN3_Pos (3)
2644#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos)
2646#define BPWM_MSKEN_MSKEN4_Pos (4)
2647#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos)
2649#define BPWM_MSKEN_MSKEN5_Pos (5)
2650#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos)
2652#define BPWM_MSKEN_MSKENn_Pos (0)
2653#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos)
2655#define BPWM_MSK_MSKDAT0_Pos (0)
2656#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos)
2658#define BPWM_MSK_MSKDAT1_Pos (1)
2659#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos)
2661#define BPWM_MSK_MSKDAT2_Pos (2)
2662#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos)
2664#define BPWM_MSK_MSKDAT3_Pos (3)
2665#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos)
2667#define BPWM_MSK_MSKDAT4_Pos (4)
2668#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos)
2670#define BPWM_MSK_MSKDAT5_Pos (5)
2671#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos)
2673#define BPWM_MSK_MSKDATn_Pos (0)
2674#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos)
2676#define BPWM_POLCTL_PINV0_Pos (0)
2677#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos)
2679#define BPWM_POLCTL_PINV1_Pos (1)
2680#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos)
2682#define BPWM_POLCTL_PINV2_Pos (2)
2683#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos)
2685#define BPWM_POLCTL_PINV3_Pos (3)
2686#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos)
2688#define BPWM_POLCTL_PINV4_Pos (4)
2689#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos)
2691#define BPWM_POLCTL_PINV5_Pos (5)
2692#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos)
2694#define BPWM_POLCTL_PINVn_Pos (0)
2695#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos)
2697#define BPWM_POEN_POEN0_Pos (0)
2698#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos)
2700#define BPWM_POEN_POEN1_Pos (1)
2701#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos)
2703#define BPWM_POEN_POEN2_Pos (2)
2704#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos)
2706#define BPWM_POEN_POEN3_Pos (3)
2707#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos)
2709#define BPWM_POEN_POEN4_Pos (4)
2710#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos)
2712#define BPWM_POEN_POEN5_Pos (5)
2713#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos)
2715#define BPWM_POEN_POENn_Pos (0)
2716#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos)
2718#define BPWM_INTEN_ZIEN0_Pos (0)
2719#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos)
2721#define BPWM_INTEN_PIEN0_Pos (8)
2722#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos)
2724#define BPWM_INTEN_CMPUIEN0_Pos (16)
2725#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos)
2727#define BPWM_INTEN_CMPUIEN1_Pos (17)
2728#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos)
2730#define BPWM_INTEN_CMPUIEN2_Pos (18)
2731#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos)
2733#define BPWM_INTEN_CMPUIEN3_Pos (19)
2734#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos)
2736#define BPWM_INTEN_CMPUIEN4_Pos (20)
2737#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos)
2739#define BPWM_INTEN_CMPUIEN5_Pos (21)
2740#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos)
2742#define BPWM_INTEN_CMPUIENn_Pos (16)
2743#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos)
2745#define BPWM_INTEN_CMPDIEN0_Pos (24)
2746#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos)
2748#define BPWM_INTEN_CMPDIEN1_Pos (25)
2749#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos)
2751#define BPWM_INTEN_CMPDIEN2_Pos (26)
2752#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos)
2754#define BPWM_INTEN_CMPDIEN3_Pos (27)
2755#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos)
2757#define BPWM_INTEN_CMPDIEN4_Pos (28)
2758#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos)
2760#define BPWM_INTEN_CMPDIEN5_Pos (29)
2761#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos)
2763#define BPWM_INTEN_CMPDIENn_Pos (24)
2764#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos)
2766#define BPWM_INTSTS_ZIF0_Pos (0)
2767#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos)
2769#define BPWM_INTSTS_PIF0_Pos (8)
2770#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos)
2772#define BPWM_INTSTS_CMPUIF0_Pos (16)
2773#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos)
2775#define BPWM_INTSTS_CMPUIF1_Pos (17)
2776#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos)
2778#define BPWM_INTSTS_CMPUIF2_Pos (18)
2779#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos)
2781#define BPWM_INTSTS_CMPUIF3_Pos (19)
2782#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos)
2784#define BPWM_INTSTS_CMPUIF4_Pos (20)
2785#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos)
2787#define BPWM_INTSTS_CMPUIF5_Pos (21)
2788#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos)
2790#define BPWM_INTSTS_CMPUIFn_Pos (16)
2791#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos)
2793#define BPWM_INTSTS_CMPDIF0_Pos (24)
2794#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos)
2796#define BPWM_INTSTS_CMPDIF1_Pos (25)
2797#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos)
2799#define BPWM_INTSTS_CMPDIF2_Pos (26)
2800#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos)
2802#define BPWM_INTSTS_CMPDIF3_Pos (27)
2803#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos)
2805#define BPWM_INTSTS_CMPDIF4_Pos (28)
2806#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos)
2808#define BPWM_INTSTS_CMPDIF5_Pos (29)
2809#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos)
2811#define BPWM_INTSTS_CMPDIFn_Pos (24)
2812#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos)
2814#define BPWM_EADCTS0_TRGSEL0_Pos (0)
2815#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos)
2817#define BPWM_EADCTS0_TRGEN0_Pos (7)
2818#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos)
2820#define BPWM_EADCTS0_TRGSEL1_Pos (8)
2821#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos)
2823#define BPWM_EADCTS0_TRGEN1_Pos (15)
2824#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos)
2826#define BPWM_EADCTS0_TRGSEL2_Pos (16)
2827#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos)
2829#define BPWM_EADCTS0_TRGEN2_Pos (23)
2830#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos)
2832#define BPWM_EADCTS0_TRGSEL3_Pos (24)
2833#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos)
2835#define BPWM_EADCTS0_TRGEN3_Pos (31)
2836#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos)
2838#define BPWM_EADCTS1_TRGSEL4_Pos (0)
2839#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos)
2841#define BPWM_EADCTS1_TRGEN4_Pos (7)
2842#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos)
2844#define BPWM_EADCTS1_TRGSEL5_Pos (8)
2845#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos)
2847#define BPWM_EADCTS1_TRGEN5_Pos (15)
2848#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos)
2850#define BPWM_SSCTL_SSEN0_Pos (0)
2851#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos)
2853#define BPWM_SSCTL_SSRC_Pos (8)
2854#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos)
2856#define BPWM_SSTRG_CNTSEN_Pos (0)
2857#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos)
2859#define BPWM_STATUS_CNTMAX0_Pos (0)
2860#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos)
2862#define BPWM_STATUS_EADCTRG0_Pos (16)
2863#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos)
2865#define BPWM_STATUS_EADCTRG1_Pos (17)
2866#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos)
2868#define BPWM_STATUS_EADCTRG2_Pos (18)
2869#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos)
2871#define BPWM_STATUS_EADCTRG3_Pos (19)
2872#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos)
2874#define BPWM_STATUS_EADCTRG4_Pos (20)
2875#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos)
2877#define BPWM_STATUS_EADCTRG5_Pos (21)
2878#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos)
2880#define BPWM_STATUS_EADCTRGn_Pos (16)
2881#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos)
2883#define BPWM_CAPINEN_CAPINEN0_Pos (0)
2884#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos)
2886#define BPWM_CAPINEN_CAPINEN1_Pos (1)
2887#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos)
2889#define BPWM_CAPINEN_CAPINEN2_Pos (2)
2890#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos)
2892#define BPWM_CAPINEN_CAPINEN3_Pos (3)
2893#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos)
2895#define BPWM_CAPINEN_CAPINEN4_Pos (4)
2896#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos)
2898#define BPWM_CAPINEN_CAPINEN5_Pos (5)
2899#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos)
2901#define BPWM_CAPINEN_CAPINENn_Pos (0)
2902#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos)
2904#define BPWM_CAPCTL_CAPEN0_Pos (0)
2905#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos)
2907#define BPWM_CAPCTL_CAPEN1_Pos (1)
2908#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos)
2910#define BPWM_CAPCTL_CAPEN2_Pos (2)
2911#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos)
2913#define BPWM_CAPCTL_CAPEN3_Pos (3)
2914#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos)
2916#define BPWM_CAPCTL_CAPEN4_Pos (4)
2917#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos)
2919#define BPWM_CAPCTL_CAPEN5_Pos (5)
2920#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos)
2922#define BPWM_CAPCTL_CAPENn_Pos (0)
2923#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos)
2925#define BPWM_CAPCTL_CAPINV0_Pos (8)
2926#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos)
2928#define BPWM_CAPCTL_CAPINV1_Pos (9)
2929#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos)
2931#define BPWM_CAPCTL_CAPINV2_Pos (10)
2932#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos)
2934#define BPWM_CAPCTL_CAPINV3_Pos (11)
2935#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos)
2937#define BPWM_CAPCTL_CAPINV4_Pos (12)
2938#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos)
2940#define BPWM_CAPCTL_CAPINV5_Pos (13)
2941#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos)
2943#define BPWM_CAPCTL_CAPINVn_Pos (8)
2944#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos)
2946#define BPWM_CAPCTL_RCRLDEN0_Pos (16)
2947#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos)
2949#define BPWM_CAPCTL_RCRLDEN1_Pos (17)
2950#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos)
2952#define BPWM_CAPCTL_RCRLDEN2_Pos (18)
2953#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos)
2955#define BPWM_CAPCTL_RCRLDEN3_Pos (19)
2956#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos)
2958#define BPWM_CAPCTL_RCRLDEN4_Pos (20)
2959#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos)
2961#define BPWM_CAPCTL_RCRLDEN5_Pos (21)
2962#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos)
2964#define BPWM_CAPCTL_RCRLDENn_Pos (16)
2965#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos)
2967#define BPWM_CAPCTL_FCRLDEN0_Pos (24)
2968#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos)
2970#define BPWM_CAPCTL_FCRLDEN1_Pos (25)
2971#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos)
2973#define BPWM_CAPCTL_FCRLDEN2_Pos (26)
2974#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos)
2976#define BPWM_CAPCTL_FCRLDEN3_Pos (27)
2977#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos)
2979#define BPWM_CAPCTL_FCRLDEN4_Pos (28)
2980#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos)
2982#define BPWM_CAPCTL_FCRLDEN5_Pos (29)
2983#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos)
2985#define BPWM_CAPCTL_FCRLDENn_Pos (24)
2986#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos)
2988#define BPWM_CAPSTS_CRIFOV0_Pos (0)
2989#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos)
2991#define BPWM_CAPSTS_CRIFOV1_Pos (1)
2992#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos)
2994#define BPWM_CAPSTS_CRIFOV2_Pos (2)
2995#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos)
2997#define BPWM_CAPSTS_CRIFOV3_Pos (3)
2998#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos)
3000#define BPWM_CAPSTS_CRIFOV4_Pos (4)
3001#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos)
3003#define BPWM_CAPSTS_CRIFOV5_Pos (5)
3004#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos)
3006#define BPWM_CAPSTS_CRIFOVn_Pos (0)
3007#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos)
3009#define BPWM_CAPSTS_CFIFOV0_Pos (8)
3010#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos)
3012#define BPWM_CAPSTS_CFIFOV1_Pos (9)
3013#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos)
3015#define BPWM_CAPSTS_CFIFOV2_Pos (10)
3016#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos)
3018#define BPWM_CAPSTS_CFIFOV3_Pos (11)
3019#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos)
3021#define BPWM_CAPSTS_CFIFOV4_Pos (12)
3022#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos)
3024#define BPWM_CAPSTS_CFIFOV5_Pos (13)
3025#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos)
3027#define BPWM_CAPSTS_CFIFOVn_Pos (8)
3028#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos)
3030#define BPWM_RCAPDAT0_RCAPDAT_Pos (0)
3031#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos)
3033#define BPWM_FCAPDAT0_FCAPDAT_Pos (0)
3034#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos)
3036#define BPWM_RCAPDAT1_RCAPDAT_Pos (0)
3037#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos)
3039#define BPWM_FCAPDAT1_FCAPDAT_Pos (0)
3040#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos)
3042#define BPWM_RCAPDAT2_RCAPDAT_Pos (0)
3043#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos)
3045#define BPWM_FCAPDAT2_FCAPDAT_Pos (0)
3046#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos)
3048#define BPWM_RCAPDAT3_RCAPDAT_Pos (0)
3049#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos)
3051#define BPWM_FCAPDAT3_FCAPDAT_Pos (0)
3052#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos)
3054#define BPWM_RCAPDAT4_RCAPDAT_Pos (0)
3055#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos)
3057#define BPWM_FCAPDAT4_FCAPDAT_Pos (0)
3058#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos)
3060#define BPWM_RCAPDAT5_RCAPDAT_Pos (0)
3061#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos)
3063#define BPWM_FCAPDAT5_FCAPDAT_Pos (0)
3064#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos)
3066#define BPWM_CAPIEN_CAPRIENn_Pos (0)
3067#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos)
3069#define BPWM_CAPIEN_CAPFIENn_Pos (8)
3070#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos)
3072#define BPWM_CAPIF_CAPRIF0_Pos (0)
3073#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos)
3075#define BPWM_CAPIF_CAPRIF1_Pos (1)
3076#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos)
3078#define BPWM_CAPIF_CAPRIF2_Pos (2)
3079#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos)
3081#define BPWM_CAPIF_CAPRIF3_Pos (3)
3082#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos)
3084#define BPWM_CAPIF_CAPRIF4_Pos (4)
3085#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos)
3087#define BPWM_CAPIF_CAPRIF5_Pos (5)
3088#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos)
3090#define BPWM_CAPIF_CAPRIFn_Pos (0)
3091#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos)
3093#define BPWM_CAPIF_CAPFIF0_Pos (8)
3094#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos)
3096#define BPWM_CAPIF_CAPFIF1_Pos (9)
3097#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos)
3099#define BPWM_CAPIF_CAPFIF2_Pos (10)
3100#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos)
3102#define BPWM_CAPIF_CAPFIF3_Pos (11)
3103#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos)
3105#define BPWM_CAPIF_CAPFIF4_Pos (12)
3106#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos)
3108#define BPWM_CAPIF_CAPFIF5_Pos (13)
3109#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos)
3111#define BPWM_CAPIF_CAPFIFn_Pos (8)
3112#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos)
3114#define BPWM_PBUF_PBUF_Pos (0)
3115#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos)
3117#define BPWM_CMPBUF0_CMPBUF_Pos (0)
3118#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos)
3120#define BPWM_CMPBUF1_CMPBUF_Pos (0)
3121#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos)
3123#define BPWM_CMPBUF2_CMPBUF_Pos (0)
3124#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos)
3126#define BPWM_CMPBUF3_CMPBUF_Pos (0)
3127#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos)
3129#define BPWM_CMPBUF4_CMPBUF_Pos (0)
3130#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos)
3132#define BPWM_CMPBUF5_CMPBUF_Pos (0)
3133#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /* BPWM_CONST */ /* end of BPWM register group */ /* end of REGISTER group */
3138
3139#if defined ( __CC_ARM )
3140#pragma no_anon_unions
3141#endif
3142
3143#endif /* __BPWM_REG_H__ */
__IO uint32_t FCAPDAT
Definition: bpwm_reg.h:68
__IO uint32_t RCAPDAT
Definition: bpwm_reg.h:67
__IO uint32_t MSKEN
Definition: bpwm_reg.h:2409
__IO uint32_t CAPINEN
Definition: bpwm_reg.h:2441
__IO uint32_t CLKSRC
Definition: bpwm_reg.h:2385
__IO uint32_t MSK
Definition: bpwm_reg.h:2410
__O uint32_t SSTRG
Definition: bpwm_reg.h:2433
__IO uint32_t INTSTS
Definition: bpwm_reg.h:2423
__IO uint32_t CNTCLR
Definition: bpwm_reg.h:2391
__IO uint32_t WGCTL1
Definition: bpwm_reg.h:2408
__IO uint32_t PERIOD
Definition: bpwm_reg.h:2395
__IO uint32_t CTL1
Definition: bpwm_reg.h:2381
__IO uint32_t STATUS
Definition: bpwm_reg.h:2437
__IO uint32_t CTL0
Definition: bpwm_reg.h:2380
__IO uint32_t CAPIF
Definition: bpwm_reg.h:2449
__I uint32_t CNT
Definition: bpwm_reg.h:2403
__IO uint32_t WGCTL0
Definition: bpwm_reg.h:2407
__IO uint32_t EADCTS0
Definition: bpwm_reg.h:2427
__I uint32_t CAPSTS
Definition: bpwm_reg.h:2443
__IO uint32_t CAPIEN
Definition: bpwm_reg.h:2448
__IO uint32_t CAPCTL
Definition: bpwm_reg.h:2442
__IO uint32_t CLKPSC
Definition: bpwm_reg.h:2386
__IO uint32_t POEN
Definition: bpwm_reg.h:2415
__IO uint32_t POLCTL
Definition: bpwm_reg.h:2414
__IO uint32_t CNTEN
Definition: bpwm_reg.h:2390
__I uint32_t PBUF
Definition: bpwm_reg.h:2453
__IO uint32_t INTEN
Definition: bpwm_reg.h:2419
__IO uint32_t SSCTL
Definition: bpwm_reg.h:2432
__IO uint32_t EADCTS1
Definition: bpwm_reg.h:2428