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M480 BSP V3.05.005
The Board Support Package for M480 Series
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#include <ecap_reg.h>
Data Fields | |
__IO uint32_t | CNT |
__IO uint32_t | HLD0 |
__IO uint32_t | HLD1 |
__IO uint32_t | HLD2 |
__IO uint32_t | CNTCMP |
__IO uint32_t | CTL0 |
__IO uint32_t | CTL1 |
__IO uint32_t | STATUS |
@addtogroup ECAP Enhanced Input Capture Timer(ECAP) Memory Mapped Structure for ECAP Controller
Definition at line 26 of file ecap_reg.h.
ECAP_T::CNT |
[0x0000] Input Capture Counter
Bits | Field | Descriptions |
[23:0] | CNT | Input Capture Timer/Counter
The input Capture Timer/Counter is a 24-bit up-counting counter The clock source for the counter is from the clock divider |
Definition at line 516 of file ecap_reg.h.
ECAP_T::CNTCMP |
[0x0010] Input Capture Compare Register
Bits | Field | Descriptions |
[23:0] | CNTCMP | Input Capture Counter Compare Register
If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. |
Definition at line 520 of file ecap_reg.h.
ECAP_T::CTL0 |
[0x0014] Input Capture Control Register 0
Bits | Field | Descriptions |
[2:0] | NFCLKSEL | Noise Filter Clock Pre-divide Selection
To determine the sampling frequency of the Noise Filter clock 000 = CAP_CLK. 001 = CAP_CLK/2. 010 = CAP_CLK/4. 011 = CAP_CLK/16. 100 = CAP_CLK/32. 101 = CAP_CLK/64. |
[3] | CAPNFDIS | Input Capture Noise Filter Disable Control
0 = Noise filter of Input Capture Enabled. 1 = Noise filter of Input Capture Disabled (Bypass). |
[4] | IC0EN | Port Pin IC0 Input to Input Capture Unit Enable Control
0 = IC0 input to Input Capture Unit Disabled. 1 = IC0 input to Input Capture Unit Enabled. |
[5] | IC1EN | Port Pin IC1 Input to Input Capture Unit Enable Control
0 = IC1 input to Input Capture Unit Disabled. 1 = IC1 input to Input Capture Unit Enabled. |
[6] | IC2EN | Port Pin IC2 Input to Input Capture Unit Enable Control
0 = IC2 input to Input Capture Unit Disabled. 1 = IC2 input to Input Capture Unit Enabled. |
[9:8] | CAPSEL0 | CAP0 Input Source Selection
00 = CAP0 input is from port pin ICAP0. 01 = Reserved. 10 = CAP0 input is from signal CHA of QEI controller unit n. 11 = Reserved. Note: Input capture unit n matches QEIn, where n = 0~1. |
[11:10] | CAPSEL1 | CAP1 Input Source Selection
00 = CAP1 input is from port pin ICAP1. 01 = Reserved. 10 = CAP1 input is from signal CHB of QEI controller unit n. 11 = Reserved. Note: Input capture unit n matches QEIn, where n = 0~1. |
[13:12] | CAPSEL2 | CAP2 Input Source Selection
00 = CAP2 input is from port pin ICAP2. 01 = Reserved. 10 = CAP2 input is from signal CHX of QEI controller unit n. 11 = Reserved. Note: Input capture unit n matches QEIn, where n = 0~1. |
[16] | CAPIEN0 | Input Capture Channel 0 Interrupt Enable Control
0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. 1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. |
[17] | CAPIEN1 | Input Capture Channel 1 Interrupt Enable Control
0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. 1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. |
[18] | CAPIEN2 | Input Capture Channel 2 Interrupt Enable Control
0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. 1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. |
[20] | OVIEN | CAPOVF Trigger Input Capture Interrupt Enable Control
0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. 1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. |
[21] | CMPIEN | CAPCMPF Trigger Input Capture Interrupt Enable Control
0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. 1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. |
[24] | CNTEN | Input Capture Counter Start Counting Control
Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . 0 = ECAP_CNT stop counting. 1 = ECAP_CNT starts up-counting. |
[25] | CMPCLREN | Input Capture Counter Cleared by Compare-match Control
If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. 0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. 1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. |
[28] | CMPEN | Compare Function Enable Control
The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. 0 = The compare function Disabled. 1 = The compare function Enabled. |
[29] | CAPEN | Input Capture Timer/Counter Enable Control
0 = Input Capture function Disabled. 1 = Input Capture function Enabled. |
Definition at line 521 of file ecap_reg.h.
ECAP_T::CTL1 |
[0x0018] Input Capture Control Register 1
Bits | Field | Descriptions |
[1:0] | EDGESEL0 | Channel 0 Captured Edge Selection
Input capture0 can detect falling edge change only, rising edge change only or both edge change 00 = Detect rising edge only. 01 = Detect falling edge only. 1x = Detect both rising and falling edge. |
[3:2] | EDGESEL1 | Channel 1 Captured Edge Selection
Input capture1 can detect falling edge change only, rising edge change only or both edge change 00 = Detect rising edge only. 01 = Detect falling edge only. 1x = Detect both rising and falling edge. |
[5:4] | EDGESEL2 | Channel 2 Captured Edge Selection
Input capture2 can detect falling edge change only, rising edge change only or both edge changes 00 = Detect rising edge only. 01 = Detect falling edge only. 1x = Detect both rising and falling edge. |
[8] | CAP0RLDEN | Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
0 = The reload triggered by Event CAPTE0 Disabled. 1 = The reload triggered by Event CAPTE0 Enabled. |
[9] | CAP1RLDEN | Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
0 = The reload triggered by Event CAPTE1 Disabled. 1 = The reload triggered by Event CAPTE1 Enabled. |
[10] | CAP2RLDEN | Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
0 = The reload triggered by Event CAPTE2 Disabled. 1 = The reload triggered by Event CAPTE2 Enabled. |
[11] | OVRLDEN | Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
0 = The reload triggered by CAPOV Disabled. 1 = The reload triggered by CAPOV Enabled. |
[14:12] | CLKSEL | Capture Timer Clock Divide Selection
The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. 000 = CAP_CLK/1. 001 = CAP_CLK/4. 010 = CAP_CLK/16. 011 = CAP_CLK/32. 100 = CAP_CLK/64. 101 = CAP_CLK/96. 110 = CAP_CLK/112. 111 = CAP_CLK/128. |
[17:16] | CNTSRCSEL | Capture Timer/Counter Clock Source Selection
Select the capture timer/counter clock source. 00 = CAP_CLK (default). 01 = CAP0. 10 = CAP1. 11 = CAP2. |
[20] | CAP0CLREN | Capture Counter Cleared by Capture Event0 Control
0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. 1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. |
[21] | CAP1CLREN | Capture Counter Cleared by Capture Event1 Control
0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. 1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. |
[22] | CAP2CLREN | Capture Counter Cleared by Capture Event2 Control
0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. 1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. |
Definition at line 522 of file ecap_reg.h.
ECAP_T::HLD0 |
[0x0004] Input Capture Hold Register 0
Bits | Field | Descriptions |
[23:0] | HOLD | Input Capture Counter Hold Register
When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 517 of file ecap_reg.h.
ECAP_T::HLD1 |
[0x0008] Input Capture Hold Register 1
Bits | Field | Descriptions |
[23:0] | HOLD | Input Capture Counter Hold Register
When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 518 of file ecap_reg.h.
ECAP_T::HLD2 |
[0x000c] Input Capture Hold Register 2
Bits | Field | Descriptions |
[23:0] | HOLD | Input Capture Counter Hold Register
When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 519 of file ecap_reg.h.
ECAP_T::STATUS |
[0x001c] Input Capture Status Register
Bits | Field | Descriptions |
[0] | CAPTF0 | Input Capture Channel 0 Triggered Flag
When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. 0 = No valid edge change has been detected at CAP0 input since last clear. 1 = At least a valid edge change has been detected at CAP0 input since last clear. Note: This bit is only cleared by writing 1 to it. |
[1] | CAPTF1 | Input Capture Channel 1 Triggered Flag
When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. 0 = No valid edge change has been detected at CAP1 input since last clear. 1 = At least a valid edge change has been detected at CAP1 input since last clear. Note: This bit is only cleared by writing 1 to it. |
[2] | CAPTF2 | Input Capture Channel 2 Triggered Flag
When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. 0 = No valid edge change has been detected at CAP2 input since last clear. 1 = At least a valid edge change has been detected at CAP2 input since last clear. Note: This bit is only cleared by writing 1 to it. |
[4] | CAPCMPF | Input Capture Compare-match Flag
If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. 0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. 1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. Note: This bit is only cleared by writing 1 to it. |
[5] | CAPOVF | Input Capture Counter Overflow Flag
Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. 0 = No overflow event has occurred since last clear. 1 = Overflow event(s) has/have occurred since last clear. Note: This bit is only cleared by writing 1 to it. |
[6] | CAP0 | Value of Input Channel 0, CAP0 (Read Only)
Reflecting the value of input channel 0, CAP0 (The bit is read only and write is ignored) |
[7] | CAP1 | Value of Input Channel 1, CAP1 (Read Only)
Reflecting the value of input channel 1, CAP1 (The bit is read only and write is ignored) |
[8] | CAP2 | Value of Input Channel 2, CAP2 (Read Only)
Reflecting the value of input channel 2, CAP2. (The bit is read only and write is ignored) |
Definition at line 523 of file ecap_reg.h.