44 uint32_t u32MasterSlave,
46 uint32_t u32DataWidth,
49 uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
51 if(u32DataWidth == 32U)
67 if(u32BusClock >= u32HCLKFreq)
72 else if (qspi ==
QSPI1)
97 else if (qspi ==
QSPI1)
118 if(u32BusClock >= u32HCLKFreq)
123 u32RetValue = u32ClkSrc;
125 else if(u32BusClock >= u32ClkSrc)
130 u32RetValue = u32ClkSrc;
132 else if(u32BusClock == 0U)
137 u32RetValue = (u32ClkSrc / (0xFFU + 1U));
141 u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U;
147 u32RetValue = (u32ClkSrc / (0xFFU + 1U));
153 u32RetValue = (u32ClkSrc / (u32Div + 1U));
175 else if (qspi ==
QSPI1)
198 SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk;
200 else if (qspi ==
QSPI1)
203 SYS->IPRST2 &= ~SYS_IPRST2_QSPI1RST_Msk;
269 uint32_t u32ClkSrc, u32HCLKFreq;
270 uint32_t u32Div, u32RetValue;
275 if(u32BusClock >= u32HCLKFreq)
280 else if (qspi ==
QSPI1)
305 else if (qspi ==
QSPI1)
326 if(u32BusClock >= u32HCLKFreq)
331 u32RetValue = u32ClkSrc;
333 else if(u32BusClock >= u32ClkSrc)
338 u32RetValue = u32ClkSrc;
340 else if(u32BusClock == 0U)
345 u32RetValue = (u32ClkSrc / (0xFFU + 1U));
349 u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U;
355 u32RetValue = (u32ClkSrc / (0xFFU + 1U));
361 u32RetValue = (u32ClkSrc / (u32Div + 1U));
418 else if (qspi ==
QSPI1)
440 return (u32ClkSrc / (u32Div + 1U));
551 qspi->
CTL &= ~QSPI_CTL_UNITIEN_Msk;
557 qspi->
SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
563 qspi->
SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
569 qspi->
SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
575 qspi->
SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
581 qspi->
FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
587 qspi->
FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
593 qspi->
FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
599 qspi->
FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
605 qspi->
FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
631 uint32_t u32IntFlag = 0U, u32TmpVal;
787 uint32_t u32Flag = 0U, u32TmpValue;
NuMicro peripheral access layer header file.
#define CLK_CLKSEL2_QSPI0SEL_PLL
#define CLK_CLKSEL2_QSPI0SEL_PCLK0
#define CLK_CLKSEL2_QSPI0SEL_HXT
#define CLK_CLKSEL3_QSPI1SEL_PCLK1
#define CLK_CLKSEL3_QSPI1SEL_PLL
#define CLK_CLKSEL3_QSPI1SEL_HXT
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
#define QSPI_UNIT_INT_MASK
#define QSPI_FIFO_RXOV_INT_MASK
#define QSPI_TX_EMPTY_MASK
#define QSPI_SS_ACTIVE_LOW
#define QSPI_FIFO_RXTH_INT_MASK
#define QSPI_RX_FULL_MASK
#define QSPI_TXRX_RESET_MASK
#define QSPI_QSPIEN_STS_MASK
#define QSPI_SSLINE_STS_MASK
#define QSPI_FIFO_RXTO_INT_MASK
#define QSPI_SLVBE_INT_MASK
#define QSPI_SSINACT_INT_MASK
#define QSPI_RX_EMPTY_MASK
#define QSPI_TX_FULL_MASK
#define QSPI_TXUF_INT_MASK
#define QSPI_SSACT_INT_MASK
#define QSPI_FIFO_TXTH_INT_MASK
#define QSPI_SLVUR_INT_MASK
void QSPI_Close(QSPI_T *qspi)
Disable QSPI controller.
void QSPI_ClearTxFIFO(QSPI_T *qspi)
Clear TX FIFO buffer.
void QSPI_ClearRxFIFO(QSPI_T *qspi)
Clear RX FIFO buffer.
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
Set the QSPI bus clock.
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
Enable interrupt function.
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
Clear interrupt flag.
uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make QSPI module be ready to transfer.
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
uint32_t QSPI_GetBusClock(QSPI_T *qspi)
Get the actual frequency of QSPI bus clock. Only available in Master mode.
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
Get interrupt flag.
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
Disable interrupt function.
void QSPI_DisableAutoSS(QSPI_T *qspi)
Disable the automatic slave selection function.
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
Get QSPI status.
#define QSPI_FIFOCTL_RXFBCLR_Msk
#define QSPI_STATUS_TXRXRST_Msk
#define QSPI_SSCTL_AUTOSS_Msk
#define QSPI_SSCTL_SS_Msk
#define SYS_IPRST2_QSPI1RST_Msk
#define QSPI_STATUS_BUSY_Msk
#define QSPI_STATUS_RXTOIF_Msk
#define CLK_CLKSEL2_QSPI0SEL_Msk
#define QSPI_STATUS_RXOVIF_Msk
#define QSPI_SSCTL_SLVBEIEN_Msk
#define QSPI_STATUS_SSACTIF_Msk
#define QSPI_STATUS_TXFULL_Msk
#define QSPI_STATUS_SLVURIF_Msk
#define QSPI_FIFOCTL_RXTH_Pos
#define QSPI_FIFOCTL_TXTH_Pos
#define QSPI_SSCTL_SSACTIEN_Msk
#define QSPI_FIFOCTL_TXTH_Msk
#define QSPI_CTL_QSPIEN_Msk
#define QSPI_STATUS_TXEMPTY_Msk
#define QSPI_CTL_DWIDTH_Pos
#define QSPI_STATUS_UNITIF_Msk
#define QSPI_FIFOCTL_TXUFIEN_Msk
#define QSPI_STATUS_RXTHIF_Msk
#define QSPI_STATUS_TXTHIF_Msk
#define QSPI_STATUS_TXUFIF_Msk
#define QSPI_FIFOCTL_RXTOIEN_Msk
#define QSPI_CTL_UNITIEN_Msk
#define QSPI_STATUS_SSLINE_Msk
#define CLK_CLKSEL3_QSPI1SEL_Msk
#define QSPI_FIFOCTL_TXFBCLR_Msk
#define QSPI_SSCTL_SSACTPOL_Msk
#define QSPI_STATUS_SLVBEIF_Msk
#define QSPI_FIFOCTL_RXTHIEN_Msk
#define QSPI_FIFOCTL_RXOVIEN_Msk
#define QSPI_CLKDIV_DIVIDER_Msk
#define QSPI_FIFOCTL_RXTH_Msk
#define QSPI_STATUS_SSINAIF_Msk
#define QSPI_SSCTL_SLVURIEN_Msk
#define QSPI_STATUS_QSPIENSTS_Msk
#define QSPI_STATUS_RXEMPTY_Msk
#define QSPI_SSCTL_SSINAIEN_Msk
#define SYS_IPRST1_QSPI0RST_Msk
#define QSPI_FIFOCTL_TXTHIEN_Msk
#define QSPI_CLKDIV_DIVIDER_Pos
#define QSPI_STATUS_RXFULL_Msk