M480 BSP V3.05.005
The Board Support Package for M480 Series
clk.h
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1/**************************************************************************/
9#ifndef __CLK_H__
10#define __CLK_H__
11
12#ifdef __cplusplus
13extern "C"
14{
15#endif
16
17
31#define FREQ_25MHZ 25000000UL
32#define FREQ_50MHZ 50000000UL
33#define FREQ_72MHZ 72000000UL
34#define FREQ_80MHZ 80000000UL
35#define FREQ_100MHZ 100000000UL
36#define FREQ_125MHZ 125000000UL
37#define FREQ_160MHZ 160000000UL
38#define FREQ_192MHZ 192000000UL
39#define FREQ_200MHZ 200000000UL
40#define FREQ_250MHZ 250000000UL
41#define FREQ_500MHZ 500000000UL
43/*---------------------------------------------------------------------------------------------------------*/
44/* CLKSEL0 constant definitions. (Write-protection) */
45/*---------------------------------------------------------------------------------------------------------*/
46#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos)
47#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos)
48#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos)
49#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos)
50#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos)
52#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos)
53#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos)
54#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos)
55#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos)
56#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos)
57#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos)
59#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)
60#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)
61#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)
62#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)
65#if(0)
66#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos)
67#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos)
69#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos)
70#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos)
71#endif
72
73#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)
74#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)
75#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)
76#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)
78#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos)
79#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos)
80#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos)
81#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos)
83#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos)
84#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos)
85#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos)
86#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos)
88#define CLK_CLKSEL0_USBSEL_RC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos)
89#define CLK_CLKSEL0_USBSEL_PLL (0x1UL << CLK_CLKSEL0_USBSEL_Pos)
91/*---------------------------------------------------------------------------------------------------------*/
92/* CLKSEL1 constant definitions. */
93/*---------------------------------------------------------------------------------------------------------*/
94#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos)
95#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos)
96#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos)
98#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos)
99#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos)
100#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos)
101#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos)
102#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos)
103#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos)
105#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos)
106#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos)
107#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos)
108#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos)
109#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos)
110#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos)
112#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos)
113#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos)
114#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos)
115#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos)
116#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos)
117#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos)
119#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos)
120#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos)
121#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos)
122#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos)
123#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos)
124#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos)
126#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos)
127#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos)
128#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos)
129#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos)
131#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos)
132#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos)
133#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos)
134#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos)
136#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos)
137#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos)
138#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos)
139#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos)
141#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos)
142#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos)
145/*---------------------------------------------------------------------------------------------------------*/
146/* CLKSEL2 constant definitions. */
147/*---------------------------------------------------------------------------------------------------------*/
148#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos)
149#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos)
150#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos)
151#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos)
153#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos)
154#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos)
155#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos)
156#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos)
158#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos)
159#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos)
160#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos)
161#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos)
163#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos)
164#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos)
166#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos)
167#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos)
169#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos)
170#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos)
172#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos)
173#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos)
175#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos)
176#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos)
177#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos)
178#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos)
180#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos)
181#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos)
182#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos)
183#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos)
186/*---------------------------------------------------------------------------------------------------------*/
187/* CLKSEL3 constant definitions. */
188/*---------------------------------------------------------------------------------------------------------*/
189#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos)
190#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos)
191#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos)
192#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos)
194#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos)
195#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos)
196#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos)
197#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos)
199#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos)
200#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos)
201#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos)
202#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos)
204#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos)
205#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos)
207#define CLK_CLKSEL3_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL3_QSPI1SEL_Pos)
208#define CLK_CLKSEL3_QSPI1SEL_PLL (0x1UL << CLK_CLKSEL3_QSPI1SEL_Pos)
209#define CLK_CLKSEL3_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL3_QSPI1SEL_Pos)
210#define CLK_CLKSEL3_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_QSPI1SEL_Pos)
212#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos)
213#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos)
214#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos)
215#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos)
217#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos)
218#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos)
219#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos)
220#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos)
222#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos)
223#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos)
224#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos)
225#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos)
227#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos)
228#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos)
229#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos)
230#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos)
232#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos)
233#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos)
234#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos)
235#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos)
237#define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos)
238#define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos)
239#define CLK_CLKSEL3_UART6SEL_PLL (0x1UL << CLK_CLKSEL3_UART6SEL_Pos)
240#define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos)
242#define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos)
243#define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos)
244#define CLK_CLKSEL3_UART7SEL_PLL (0x1UL << CLK_CLKSEL3_UART7SEL_Pos)
245#define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos)
247/*---------------------------------------------------------------------------------------------------------*/
248/* CLKDIV0 constant definitions. */
249/*---------------------------------------------------------------------------------------------------------*/
250#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos)
251#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos)
252#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos)
253#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos)
254#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos)
255#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos)
257/*---------------------------------------------------------------------------------------------------------*/
258/* CLKDIV1 constant definitions. */
259/*---------------------------------------------------------------------------------------------------------*/
260#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos)
261#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos)
262#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos)
264/*---------------------------------------------------------------------------------------------------------*/
265/* CLKDIV2 constant definitions. */
266/*---------------------------------------------------------------------------------------------------------*/
267#define CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos)
268#define CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos)
270/*---------------------------------------------------------------------------------------------------------*/
271/* CLKDIV3 constant definitions. */
272/*---------------------------------------------------------------------------------------------------------*/
273#define CLK_CLKDIV3_CCAP(x) (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos)
274#define CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos)
275#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos)
276#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos)
278/*---------------------------------------------------------------------------------------------------------*/
279/* CLKDIV4 constant definitions. */
280/*---------------------------------------------------------------------------------------------------------*/
281#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos)
282#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos)
283#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos)
284#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos)
285#define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos)
286#define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos)
288/*---------------------------------------------------------------------------------------------------------*/
289/* PCLKDIV constant definitions. */
290/*---------------------------------------------------------------------------------------------------------*/
291#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)
292#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)
293#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)
294#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos)
295#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos)
296#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos)
297#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos)
298#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)
299#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)
300#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)
301//
302#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)
303#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)
304#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)
305#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos)
306#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos)
307#define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos)
308#define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos)
309#define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)
310#define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)
311#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)
313/*---------------------------------------------------------------------------------------------------------*/
314/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
315/*---------------------------------------------------------------------------------------------------------*/
316#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL
317#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
319#define CLK_PLLCTL_NF(x) (((x)-2UL))
320#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9)
322#define CLK_PLLCTL_NO_1 0x0000UL
323#define CLK_PLLCTL_NO_2 0x4000UL
324#define CLK_PLLCTL_NO_4 0xC000UL
326#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4)
327#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4)
328#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2)
329#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2)
330#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2)
332#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4)
333#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4)
334#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2)
335#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2)
336#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2)
338/*---------------------------------------------------------------------------------------------------------*/
339/* MODULE constant definitions. */
340/*---------------------------------------------------------------------------------------------------------*/
341
342/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
343
344#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL)
345#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL)
346#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL)
347#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL)
348#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL)
349#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL)
350#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL)
351#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL)
352#define MODULE_NoMsk 0x0UL
353#define NA MODULE_NoMsk
355#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30)
356#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28)
357#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25)
358#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20)
359#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18)
360#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10)
361#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5)
362#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0)
364#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0))
365#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0))
366#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0))
367#define USBH_MODULE ((0UL<<30)|(0UL<<28) |(0x1UL<<25) |(8UL<<20) |(0UL<<18) |(0xFUL<<10) |(4UL<<5) |(16UL<<0))
368#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0))
369#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0))
370#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0))
371#define CCAP_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFFUL<<10) |(0UL<<5) |(8UL<<0))
372#define SEN_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0))
373#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0))
374#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0))
375#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0))
376#define FMCIDLE_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0))
377#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0))
378#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0))
379#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0))
380#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0))
381#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0))
382#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0))
383#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0))
384#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0))
385#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0))
386#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0))
387#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0))
388#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0))
389#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0))
390#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0))
391#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0))
392#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0))
393#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0))
394#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0))
395#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0))
396#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0))
397#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0))
398#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0))
399#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0))
400#define UART6_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(20UL<<20) |(3UL<<18) |(0xFUL<<10) |(16UL<<5) |(22UL<<0))
401#define UART7_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(22UL<<20) |(3UL<<18) |(0xFUL<<10) |(20UL<<5) |(23UL<<0))
402#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0))
403#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0))
404#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0))
405#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(0xFUL<<10) |(4UL<<5) |(27UL<<0))
406#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0))
407#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFUL<<10) |(0UL<<5) |(29UL<<0))
408#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0))
409#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0))
410#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0))
411#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0))
412#define QSPI1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0))
413#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0))
414#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0))
415#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0))
416#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0))
417#define CAN2_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0))
418#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0))
419#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0))
420#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0))
421#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0))
422#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0))
423#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0))
424#define TRNG_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0))
425#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0))
426#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0))
427#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0))
428#define EADC1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(31UL<<0))
430/*---------------------------------------------------------------------------------------------------------*/
431/* PDMSEL constant definitions. */
432/*---------------------------------------------------------------------------------------------------------*/
433#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos)
434#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos)
435#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos)
436#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos)
437#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos)
438#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos)
440/*---------------------------------------------------------------------------------------------------------*/
441/* WKTMRIS constant definitions. */
442/*---------------------------------------------------------------------------------------------------------*/
443#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos)
444#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos)
445#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos)
446#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos)
447#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos)
448#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos)
449#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos)
450#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos)
451#define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos)
452#define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos)
453#define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos)
454#define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos)
456/*---------------------------------------------------------------------------------------------------------*/
457/* SWKDBCLKSEL constant definitions. */
458/*---------------------------------------------------------------------------------------------------------*/
459#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
460#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
461#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
462#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
463#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
464#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
465#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
466#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
467#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
468#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
469#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
470#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
471#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
472#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
473#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
474#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
476/*---------------------------------------------------------------------------------------------------------*/
477/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
478/*---------------------------------------------------------------------------------------------------------*/
479#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos)
480#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos)
481#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos)
482#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos)
484#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos)
485#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos)
486#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos)
487#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos)
489#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos)
490#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos)
491#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos)
492#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos)
494#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos)
495#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos)
496#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos)
497#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos)
499#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos)
500#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos)
501#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos)
502#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos)
504#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos)
505#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos)
506#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos)
507#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos)
509/*---------------------------------------------------------------------------------------------------------*/
510/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
511/*---------------------------------------------------------------------------------------------------------*/
512#define CLK_SPDWKPIN_ENABLE (0x1UL << 0)
513#define CLK_SPDWKPIN_RISING (0x1UL << 1)
514#define CLK_SPDWKPIN_FALLING (0x1UL << 2)
515#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8)
516#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8)
518#define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos)
519#define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos)
520#define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos)
521#define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos)
522#define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos)
524#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk)
525#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk)
526#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk)
527#define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk)
528#define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk)
529#define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk)
530#define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk)
531#define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk)
532#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk)
533#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk)
534#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk)
535#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk)
537#define CLK_TIMEOUT_ERR (-1) /* end of group CLK_EXPORTED_CONSTANTS */
540
541extern int32_t g_CLK_i32ErrCode;
542
570#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
571
599#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
600
601/*---------------------------------------------------------------------------------------------------------*/
602/* static inline functions */
603/*---------------------------------------------------------------------------------------------------------*/
604/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
605__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
606__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
607
617__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
618{
619 SysTick->LOAD = us * CyclesPerUs;
620 SysTick->VAL = 0x0UL;
621 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
622
623 /* Waiting for down-count to zero */
624 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
625 {
626 }
627
628 /* Disable SysTick counter */
629 SysTick->CTRL = 0UL;
630}
631
640__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
641{
642 uint32_t delay;
643
644 /* It should <= 349525us for each delay loop */
645 delay = 349525UL;
646
647 do
648 {
649 if(us > delay)
650 {
651 us -= delay;
652 }
653 else
654 {
655 delay = us;
656 us = 0UL;
657 }
658
659 SysTick->LOAD = delay * CyclesPerUs;
660 SysTick->VAL = (0x0UL);
661 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
662
663 /* Waiting for down-count to zero */
664 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
665
666 /* Disable SysTick counter */
667 SysTick->CTRL = 0UL;
668
669 }
670 while(us > 0UL);
671
672}
673
674
675void CLK_DisableCKO(void);
676void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
677void CLK_PowerDown(void);
678void CLK_Idle(void);
679uint32_t CLK_GetHXTFreq(void);
680uint32_t CLK_GetLXTFreq(void);
681uint32_t CLK_GetHCLKFreq(void);
682uint32_t CLK_GetPCLK0Freq(void);
683uint32_t CLK_GetPCLK1Freq(void);
684uint32_t CLK_GetCPUFreq(void);
685uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
686void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
687void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
688void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
689void CLK_EnableXtalRC(uint32_t u32ClkMask);
690void CLK_DisableXtalRC(uint32_t u32ClkMask);
691void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
692void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
693uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
694void CLK_DisablePLL(void);
695uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
696void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
697void CLK_DisableSysTick(void);
698void CLK_SetPowerDownMode(uint32_t u32PDMode);
699void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
700uint32_t CLK_GetPMUWKSrc(void);
701void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
702uint32_t CLK_GetPLLClockFreq(void);
703uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
704uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
705 /* end of group CLK_EXPORTED_FUNCTIONS */
707 /* end of group CLK_Driver */
709 /* end of group Standard_Driver */
711
712#ifdef __cplusplus
713}
714#endif
715
716#endif /* __CLK_H__ */
717
718/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
int32_t g_CLK_i32ErrCode
Definition: clk.c:20
void CLK_Idle(void)
Enter to Idle mode.
Definition: clk.c:104
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
Set SysTick clock source.
Definition: clk.c:577
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
Definition: clk.c:246
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
Definition: clk.c:792
void CLK_DisableCKO(void)
Disable clock divider output function.
Definition: clk.c:32
void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
Set Wake-up pin trigger type at Deep Power down mode.
Definition: clk.c:1107
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
Enable module clock.
Definition: clk.c:687
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable clock divider output module clock, enable clock divider output function and set ...
Definition: clk.c:55
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
Disable module clock.
Definition: clk.c:770
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:964
uint32_t CLK_GetPMUWKSrc(void)
Get power manager wake up source.
Definition: clk.c:1155
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
Definition: clk.c:145
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:206
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
This function execute long delay function.
Definition: clk.h:640
void CLK_PowerDown(void)
Enter to Power-down mode.
Definition: clk.c:74
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:166
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.h:617
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
Get selected module clock divider number.
Definition: clk.c:1332
void CLK_DisablePLL(void)
Disable PLL.
Definition: clk.c:945
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
Definition: clk.c:259
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
Get selected module clock source.
Definition: clk.c:1283
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:335
void CLK_SetPowerDownMode(uint32_t u32PDMode)
Power-down mode selected.
Definition: clk.c:1051
void CLK_DisableXtalRC(uint32_t u32ClkMask)
Disable clock source.
Definition: clk.c:610
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:1030
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:505
void CLK_EnableXtalRC(uint32_t u32ClkMask)
Enable clock source.
Definition: clk.c:594
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:999
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
Definition: clk.c:273
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1197
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
Set specified GPIO as wake up source at Stand-by Power down mode.
Definition: clk.c:1176
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
Definition: clk.c:122
uint32_t CyclesPerUs
Definition: system_M480.c:22